)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b0cad0e896eeae3a1243d26bd13490a289630f6d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"ed6f5080_59597947","updated":"2024-04-05 23:01:00.000000000","message":"Tomas,\nI found (and fixed) this strange use of registers.\nNobody complained since it got broken 7 years ago!\nFor me it\u0027s incorrect to mix CPU and DWT registers together; DWT features should be handled by breakpoint and watchpoint commands, not by manually setting the registers. If some feature is missing, the bp/wp commands should be extended.\nWhat do you think about dropping this abuse of \u0027reg\u0027 command?\nBy the way, GDB ignores the DWT registers.","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"975bb9df7e1069f811f0a46122f365cca8bf2d35","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"496dd8a9_28763df6","in_reply_to":"1b1a803a_7ba825ea","updated":"2024-04-09 05:38:43.000000000","message":"\u003e I have just checked the ARM docs for armv7m, armv8m, CM4, CM33, CM85.\n\u003e All of them support MCR/MRC but the coprocessor to be connected is not provided by ARM. Or, I haven\u0027t found any coprocessor proposed by ARM for MCR/MRC on Cortex-M.\n\u003e So, the commands present in HLA should be exposed also in Cortex-M, even if there is no \"standard\" use case, so far.\n\nIndeed! But there is no support for Cortex-M mcr/mrc in OpenOCD. It should use a target algo because M profile lacks exec opcode capability.\n\nCurrently hla target mcr just shows:\n```\n\u003e arm mcr 10 0 0 0 0 0\nhla_target doesn\u0027t implement MCR\n```\n\nAnd the same response used to give cortex_m target, until I cleaned off the command access:\n\n7101: target/arm: do not expose \u0027arm reg\u0027, \u0027arm mcr/mrc\u0027 commands on Cortex-M | https://review.openocd.org/c/openocd/+/7101\n\nFeel free to revert 7101, preferably not before functional arm-\u003emrc/mrrc/mcr/mcrr is implemented.","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"2e5b4ca3d5b3f4515715d23697a1a427d20b4fcc","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"fc7c8b47_27fba5ab","in_reply_to":"496dd8a9_28763df6","updated":"2024-04-09 08:45:07.000000000","message":"You are right, not implemented yet!","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c893cc394ce2e0eaef800c3eac1c90eb89ee0a9d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"89b2212f_81bf5438","in_reply_to":"502a6513_a5b23cf3","updated":"2024-04-07 21:09:52.000000000","message":"Background: I\u0027m looking to make few minor steps ahead in the reset framework, cleaning up and aligning code between targets.\nI want to generalize the register_cache_invalidate() to call it in target.c and I got these registers that are not cached, don\u0027t handle valid/dirty/exist...\n\nI don\u0027t know about risc-v, but since that code grew independently in the fork and got merged in a big chunk, I can expect something questionable inside.\n\nAlso on Cortex-M CPU there are many registers accessible through MCR/MRC or memory mapped.\nI see an interest in having generic commands to handle them so mcr/mrc and mdw/mww commands. I\u0027m even thinking about adding SVD support to easily point to memory mapped registers and their bits map.\nBut considering all of them as candidates for \u0027reg\u0027 command ... I prefer to keep it simple and limit the register cache, close to what GDB wants.\n(by the way, mcr/mrc commands exist in HLA, not in normal cortex-m! BUG! I will send a patch)\n\n\u003e David Brownel\u0027s explanation in the commit message sounds reasonable\n\nYes, but for an end user it would be much better to have the extra functionalities well coded in bp/wp commands and documented.\n\n\u003e Also I don\u0027t see a reason why `reg` command should be strictly limited to the base CPU registers or those used in gdb - see how much registers are exposed e.g. for a RISC-V core...\n\nFor simpler code and to avoid the list to explode. I\u0027m curious to check what\u0027s the list for risc-v.","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"7cc581573aa3a27283fc1d5fa82f33862033c6f3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"8cd2cef4_c339aa4b","in_reply_to":"89b2212f_81bf5438","updated":"2024-04-08 04:56:00.000000000","message":"\u003e Also on Cortex-M CPU there are many registers accessible through MCR/MRC or memory mapped.\n\nDid you mean Cortex-A?\n\n\u003e \u003e Also I don\u0027t see a reason why `reg` command should be strictly limited to the base CPU registers or those used in gdb - see how much registers are exposed e.g. for a RISC-V core...\n\u003e \n\u003e For simpler code and to avoid the list to explode. I\u0027m curious to check what\u0027s the list for risc-v.\n\nYes, it\u0027s kind of explosion, more than 400 registers.","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c5a4451ca0071ae3a460d75893f82d00ec31ace0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"1b1a803a_7ba825ea","in_reply_to":"8cd2cef4_c339aa4b","updated":"2024-04-08 14:11:13.000000000","message":"\u003e \u003e Also on Cortex-M CPU there are many registers accessible through MCR/MRC or memory mapped.\n\u003e \n\u003e Did you mean Cortex-A?\n\nI have just checked the ARM docs for armv7m, armv8m, CM4, CM33, CM85.\nAll of them support MCR/MRC but the coprocessor to be connected is not provided by ARM. Or, I haven\u0027t found any coprocessor proposed by ARM for MCR/MRC on Cortex-M.\nSo, the commands present in HLA should be exposed also in Cortex-M, even if there is no \"standard\" use case, so far.\nFor the moment only Cortex-A has a long list of such registers.\nOn Cortex-M, only memory mapped.\n\n\u003e \u003e \u003e Also I don\u0027t see a reason why `reg` command should be strictly limited to the base CPU registers or those used in gdb - see how much registers are exposed e.g. for a RISC-V core...\n\u003e \u003e \n\u003e \u003e For simpler code and to avoid the list to explode. I\u0027m curious to check what\u0027s the list for risc-v.\n\u003e \n\u003e Yes, it\u0027s kind of explosion, more than 400 registers.\n\nIn mean time I will try to keep them all and verify there is nothing broken, but I still find it kind of abuse of \"reg\" implementation.","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c86d928e7d66193c47c869db17a5006d7fa5f199","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"502a6513_a5b23cf3","in_reply_to":"ed6f5080_59597947","updated":"2024-04-06 03:14:41.000000000","message":"I have no strong opinion here.\nDavid Brownel\u0027s explanation in the commit message sounds reasonable\n(damn the gerrit doesn\u0027t allow me to copy that text from the blame bubble).\nAlso I don\u0027t see a reason why `reg` command should be strictly limited to the base CPU registers or those used in gdb - see how much registers are exposed e.g. for a RISC-V core...\nOn the other hand AFAIK I never used any of DWT regs. Also there is no problem to access them as any other memory location if one needs something special, not handled by standard watchpoint cmd.","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"}],"src/target/register.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"bb5e84c4dd4c0cfd50e6f22b5910b731fa7a46f1","unresolved":true,"context_lines":[{"line_number":21,"context_line":" *"},{"line_number":22,"context_line":" * OpenOCD uses machine registers internally, and exposes them by name"},{"line_number":23,"context_line":" * to Tcl scripts.  Sets of related registers are grouped into caches."},{"line_number":24,"context_line":" * For example, a CPU core will expose a set of registers, and there"},{"line_number":25,"context_line":" * may be separate registers associated with debug or trace modules."},{"line_number":26,"context_line":" */"},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"struct reg *register_get_by_number(struct reg_cache *first,"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"fd3c99c5_42060396","line":25,"range":{"start_line":24,"start_character":0,"end_line":25,"end_character":68},"updated":"2024-04-05 23:16:19.000000000","message":"This comment implies a mix a CPU core registers and other register...","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"711e996fe6c907c63c5c6723291f0105ad9246ff","unresolved":false,"context_lines":[{"line_number":21,"context_line":" *"},{"line_number":22,"context_line":" * OpenOCD uses machine registers internally, and exposes them by name"},{"line_number":23,"context_line":" * to Tcl scripts.  Sets of related registers are grouped into caches."},{"line_number":24,"context_line":" * For example, a CPU core will expose a set of registers, and there"},{"line_number":25,"context_line":" * may be separate registers associated with debug or trace modules."},{"line_number":26,"context_line":" */"},{"line_number":27,"context_line":""},{"line_number":28,"context_line":"struct reg *register_get_by_number(struct reg_cache *first,"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"565b7ed8_38e9346c","line":25,"range":{"start_line":24,"start_character":0,"end_line":25,"end_character":68},"in_reply_to":"fd3c99c5_42060396","updated":"2024-05-04 08:24:20.000000000","message":"Ack","commit_id":"05296eba04f9bc661d0640012168ab94a26bb15c"}]}