)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"3bb8b6ed28ebf893ed95ea265d9059b1f7def8d9","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"081c1188_10fc2f04","updated":"2026-09-03 08:25:39.000000000","message":"The only problem I have with RTT riscv support is that whether it works depends on the target device, as background memory access is not guaranteed. So my concern is that we get annoyed users and bug reports. I\u0027m working on RTTv2 which addresses this and other issues, including multi-target support, but I don\u0027t think it will be ready before 1.0.","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0accd5508cc59ba196645833ab62d2d1827fb1e5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"5621d625_690dceb3","updated":"2026-09-02 07:25:56.000000000","message":"This patch does not merge anymore because some new include files have been added in `riscv.c`.\nWould you mind rebasing it on current master branch?","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"fa73c3d4987274f4c6a5404aa3ed43ed2f5d2385","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"dedffdc9_7745587a","updated":"2026-09-02 07:18:00.000000000","message":"To respect the first committer, this should be merged instead of 9930.\nThe patch looks correct to me, but I would like to have more comments from riscv and rtt experts.","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"cdbcd29c1b738be5943560a0de8e11658db3bc7b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"621349c4_484882c2","in_reply_to":"081c1188_10fc2f04","updated":"2026-09-03 09:18:28.000000000","message":"And I remember some comment in other threads saying that there is no reliable way to detect if the riscv target allows background memory access. If it\u0027s true, no way to block RTT when not possible.\nNevertheless, since it will work on some targets, what should we do? Add a warning?","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"ae2c5dd5bb28dc89774f7f4525c2ffc62551edad","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2490195b_a6248569","in_reply_to":"2008ab3f_51177686","updated":"2026-09-17 14:05:20.000000000","message":"\u003e That\u0027s interesting, I thought it can be detected by target.memory.read_while_running* provided via riscv info command?\n\nIn short, for a sensible RISC-V implementation this should work, but it is not required by the specification.\n\nA warning seems sufficient.","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"},{"author":{"_account_id":1002270,"name":"Evgeniy Morozov","email":"morozov.evgeniy.95@gmail.com","username":"Morozov-5F"},"change_message_id":"ac4dc31631df60bec65f981aa1740a771c54b348","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2008ab3f_51177686","in_reply_to":"2436ccfb_daf9c49a","updated":"2026-09-03 09:42:47.000000000","message":"Up to you folks, I\u0027ve already forgotten this patch exists :D I don\u0027t want to be an obstacle, go ahead and rebase it and add anything you feel necessary!","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"b03525fb5208412bfc62058215522b1a9a9f2149","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"83e82bbe_d0d37919","in_reply_to":"2490195b_a6248569","updated":"2026-09-17 14:08:19.000000000","message":"Thanks, can you take a look here please: https://review.openocd.org/c/openocd/+/9982/1\n\nFollow-up question: would it be sufficient / possible to check whether the sysbus method is available?","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"3f8ff42dc25786addd9ffa91db0e76bce6f41ee1","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2436ccfb_daf9c49a","in_reply_to":"621349c4_484882c2","updated":"2026-09-03 09:37:39.000000000","message":"\u003e And I remember some comment in other threads saying that there is no reliable way to detect if the riscv target allows background memory access.\n\nThat\u0027s interesting, I thought it can be detected by `target.memory.read_while_running*` provided via `riscv info` command?\nCan one of the riscv experts comment on that?\n\n\u003e Nevertheless, since it will work on some targets, what should we do? Add a warning?\n\nAt least I would add a warning in the RTT documentation. I can push a patch based on this one and also rebase it if the author will not respond.","commit_id":"55ec6f02058a3d1538557c023aab76332ac4740c"}]}