)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001982,"name":"Ian Thompson","email":"ianst@cadence.com","username":"ianstcdns"},"change_message_id":"b24b12086c130423c9917548135e133ec52849b9","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"0885308a_d937154b","updated":"2024-05-14 23:01:42.000000000","message":"Minor patch to avoid errors with newer LX8 cores.  Thanks in advance for reviewing.","commit_id":"c73356431f4286b7f5277040c14ee616d671aab8"},{"author":{"_account_id":1001982,"name":"Ian Thompson","email":"ianst@cadence.com","username":"ianstcdns"},"change_message_id":"f3a919bdf0abf59d870eb24e4606e9b2d1af7fff","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"f4554142_84392e32","updated":"2024-06-14 16:18:16.000000000","message":"Patch is minor... any spare bandwidth to review would be much appreciated.","commit_id":"c73356431f4286b7f5277040c14ee616d671aab8"},{"author":{"_account_id":1001982,"name":"Ian Thompson","email":"ianst@cadence.com","username":"ianstcdns"},"change_message_id":"1c55f00ef10322a48405e225d2bd26841f1d7a52","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"f59333cd_692f8f83","in_reply_to":"0885308a_d937154b","updated":"2024-05-14 23:02:55.000000000","message":"This includes registers INTSET, INTSET1, INTSET2, etc. and the same pattern for INTCLEAR*.","commit_id":"c73356431f4286b7f5277040c14ee616d671aab8"}]}