)]}'
{"src/flash/nor/stm32f1x.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b2888563c338ed23164179b02e4d34d9386581f3","unresolved":true,"context_lines":[{"line_number":880,"context_line":"\t\t/* GigaDevice GD32F1x0 \u0026 GD32F3x0 \u0026 GD32E23x series devices"},{"line_number":881,"context_line":"\t\t   share DEV_ID with STM32F101/2/3 medium-density line,"},{"line_number":882,"context_line":"\t\t   however they use a REV_ID different from any STM32 device."},{"line_number":883,"context_line":"\t\t   The main difference is another offset of user option bits"},{"line_number":884,"context_line":"\t\t   (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register"},{"line_number":885,"context_line":"\t\t   (FLASH_OBR/FMC_OBSTAT 0x4002201C)."},{"line_number":886,"context_line":"\t\t   This caused problems e.g. during flash block programming"},{"line_number":887,"context_line":"\t\t   because of unexpected active hardware watchog. */"},{"line_number":888,"context_line":"\t\tswitch (rev_id) {"},{"line_number":889,"context_line":"\t\tcase 0x1303: /* gd32f1x0 */"},{"line_number":890,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 16;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"0324847e_6485fa7a","line":887,"range":{"start_line":883,"start_character":5,"end_line":887,"end_character":51},"updated":"2024-06-21 18:54:14.000000000","message":"Marc,\nbe careful with not listed rev_id. The simple and short flash write/verify test may pass although the option bits are missplaced","commit_id":"33f0e33d46f915d3214de7c45120015a88ae07e9"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"904efa80ea1a63a1a8403cdbca17c98d0b4b78b2","unresolved":true,"context_lines":[{"line_number":880,"context_line":"\t\t/* GigaDevice GD32F1x0 \u0026 GD32F3x0 \u0026 GD32E23x series devices"},{"line_number":881,"context_line":"\t\t   share DEV_ID with STM32F101/2/3 medium-density line,"},{"line_number":882,"context_line":"\t\t   however they use a REV_ID different from any STM32 device."},{"line_number":883,"context_line":"\t\t   The main difference is another offset of user option bits"},{"line_number":884,"context_line":"\t\t   (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register"},{"line_number":885,"context_line":"\t\t   (FLASH_OBR/FMC_OBSTAT 0x4002201C)."},{"line_number":886,"context_line":"\t\t   This caused problems e.g. during flash block programming"},{"line_number":887,"context_line":"\t\t   because of unexpected active hardware watchog. */"},{"line_number":888,"context_line":"\t\tswitch (rev_id) {"},{"line_number":889,"context_line":"\t\tcase 0x1303: /* gd32f1x0 */"},{"line_number":890,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 16;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"12084cd1_519416b5","line":887,"range":{"start_line":883,"start_character":5,"end_line":887,"end_character":51},"in_reply_to":"0324847e_6485fa7a","updated":"2024-06-22 07:28:35.000000000","message":"Indeed, the configuration bits (watchdog, etc.) are somewhat different. RDP, write protection bits etc. is compatible. Since we heavily reuse drivers, what do you suggest to do in this case?","commit_id":"33f0e33d46f915d3214de7c45120015a88ae07e9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"8272e64e1876e9936cdd05ea2a3343d690e1f41b","unresolved":true,"context_lines":[{"line_number":880,"context_line":"\t\t/* GigaDevice GD32F1x0 \u0026 GD32F3x0 \u0026 GD32E23x series devices"},{"line_number":881,"context_line":"\t\t   share DEV_ID with STM32F101/2/3 medium-density line,"},{"line_number":882,"context_line":"\t\t   however they use a REV_ID different from any STM32 device."},{"line_number":883,"context_line":"\t\t   The main difference is another offset of user option bits"},{"line_number":884,"context_line":"\t\t   (like WDG_SW, nRST_STOP, nRST_STDBY) in option byte register"},{"line_number":885,"context_line":"\t\t   (FLASH_OBR/FMC_OBSTAT 0x4002201C)."},{"line_number":886,"context_line":"\t\t   This caused problems e.g. during flash block programming"},{"line_number":887,"context_line":"\t\t   because of unexpected active hardware watchog. */"},{"line_number":888,"context_line":"\t\tswitch (rev_id) {"},{"line_number":889,"context_line":"\t\tcase 0x1303: /* gd32f1x0 */"},{"line_number":890,"context_line":"\t\t\tstm32x_info-\u003euser_data_offset \u003d 16;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"cbe60860_43455dc0","line":887,"range":{"start_line":883,"start_character":5,"end_line":887,"end_character":51},"in_reply_to":"12084cd1_519416b5","updated":"2024-06-22 11:31:36.000000000","message":"I guess that all (or most of?) newer GD32 devices have the same user_data_offset and option_offset (except GD32VF103, which is intentionally compatible with STM32F103). If we know the numerical range of revisions GD uses, we could at least use the correct options for any device in the range.\n\nUntil we know some system in GD revision we have to add revisions on device by device basis. Of course we may add an flash driver option to prefer GD32 over STM32 in probe but would it work for not yet tested GD32 devices? Who knows...","commit_id":"33f0e33d46f915d3214de7c45120015a88ae07e9"}]}