)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"0d27a3f1866f0f68361e94c5ffcde1737181e002","unresolved":true,"context_lines":[{"line_number":7,"context_line":"target/mips32: add dsp access support for gdb"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Change order of dsp register name array and removed hi0 and lo0"},{"line_number":10,"context_line":"to comply with gdb definition."},{"line_number":11,"context_line":"Add dsp registers into reg_list for gdb to access them."},{"line_number":12,"context_line":"Add dsp module enable detection to avoid DSP Disabled exception"},{"line_number":13,"context_line":"while reading dsp accumulators."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"9b2bbb93_44a9f199","line":10,"updated":"2024-09-17 08:17:34.000000000","message":"It will be good to add some thing like, hi0 and lo0 is not used anywhere, or some words why you thing it is safe to remove it.","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"d5bf3bfe988be8144b1f13e807d434a3cd309cd0","unresolved":false,"context_lines":[{"line_number":7,"context_line":"target/mips32: add dsp access support for gdb"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Change order of dsp register name array and removed hi0 and lo0"},{"line_number":10,"context_line":"to comply with gdb definition."},{"line_number":11,"context_line":"Add dsp registers into reg_list for gdb to access them."},{"line_number":12,"context_line":"Add dsp module enable detection to avoid DSP Disabled exception"},{"line_number":13,"context_line":"while reading dsp accumulators."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"3f32d628_710aa802","line":10,"in_reply_to":"9b2bbb93_44a9f199","updated":"2024-09-18 08:51:39.000000000","message":"I have updated the commit message. \n\nThe code before does not store the actual dsp register contents, the name register only map to the dsp register reading arrays within the reading/writing functions.\n\nChanging the order and content is because of the name array now map to dsp registers stored in the range from `MIPS32_REGLIST_DSP_INDEX` to `MIPS32_REGLIST_DSP_DSPCTL_INDEX` in `mips32_regs`, which does not contain hi0\u0026lo0.","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"f36068df_453a716f","updated":"2024-09-14 08:36:55.000000000","message":"Fixed, let me know if there are more explainations or fixes are needed!","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"fa12edf6112dc0a5332946b9a4371db117e1aa93","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"fe746e29_24ccf9b6","updated":"2024-09-09 07:17:08.000000000","message":"Hi folks, I\u0027ll try to review it this week. Beside, do any one is on the conferences in VIenna next weak?","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"ecadd01e_829d0664","updated":"2024-09-13 10:31:06.000000000","message":"Hi! Thank your for you patch. Looks good, just some minor fixes are needed.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"47a49b30fc85b69c3d0537a88049d1ae3ba6b3dd","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"a9615adc_2cdfcf82","updated":"2024-09-07 14:37:02.000000000","message":"Looks ok to me, but I cannot test it\nOleksij, any comment?","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"0a83562f3fe8eb69b886a326a3fb6d3ef7aca290","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"88049d29_8d6b80f1","in_reply_to":"a9615adc_2cdfcf82","updated":"2024-09-09 06:09:09.000000000","message":"Hi, the code was tested on pic32mz ef, I can upload the logs or screenshots/screencap for review.\n\nBTW, the behavior of the `monitor mips32 dsp` command and `info reg` command are not the same.\n\nThe monitor command reads/writes current register content on execute, while `info reg` command displays the cached contents upon entering debug state, then writes the contents back on exiting debug state.\n\nTherefore using `set $hi/lo[1-3]`/`info register` and `mon mips32 dsp hi/lo[1-3] [data]` would display different contents(setting the dirty field does not update the cached registers somehow), and the monitor command will be overwritten by gdb when dsp module is present and enabled.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0fe52d2e3ceb7aaa319db4e62cacf4b24c22cfe6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"8a5f689f_728bd6ec","in_reply_to":"fe746e29_24ccf9b6","updated":"2024-09-11 12:44:17.000000000","message":"Thanks!\nNo, I will not attend ELC this year.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"e3590a9a9688ccb94e2c069d5bc9aa062281048f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"b2df57cc_d6ebf903","updated":"2024-09-18 22:49:58.000000000","message":"Looks good for me. Thank you! :)","commit_id":"3e55ef2625b5d73702f055a89f4bc84806d086a2"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"4a83b82eade4aedb0b283acde5ddecc20ef3327f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"8d641b60_633dea71","updated":"2024-09-23 08:24:51.000000000","message":"Thank you for your time!","commit_id":"3e55ef2625b5d73702f055a89f4bc84806d086a2"}],"src/target/mips32.c":[{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":226,"context_line":""},{"line_number":227,"context_line":"static const struct {"},{"line_number":228,"context_line":"\tconst char *name;"},{"line_number":229,"context_line":"} mips32_dsp_regs[MIPS32NUMDSPREGS] \u003d {"},{"line_number":230,"context_line":"\t{ \"hi1\"},"},{"line_number":231,"context_line":"\t{ \"lo1\"},"},{"line_number":232,"context_line":"\t{ \"hi2\"},"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"dea01612_d02f5897","line":229,"updated":"2024-09-13 10:31:06.000000000","message":"Please provide an explanation in the commit message for the removal of hi0 and lo0 registers and justify reordering of this registers. I assume, nothing will break.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":226,"context_line":""},{"line_number":227,"context_line":"static const struct {"},{"line_number":228,"context_line":"\tconst char *name;"},{"line_number":229,"context_line":"} mips32_dsp_regs[MIPS32NUMDSPREGS] \u003d {"},{"line_number":230,"context_line":"\t{ \"hi1\"},"},{"line_number":231,"context_line":"\t{ \"lo1\"},"},{"line_number":232,"context_line":"\t{ \"hi2\"},"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"34ac0f7e_edef764d","line":229,"in_reply_to":"dea01612_d02f5897","updated":"2024-09-14 08:36:55.000000000","message":"The code has been tested on pic32mz ef, and nothing is broken, removing hi0 and lo0 is because of the structure of mips-dsp.xml([check here](https://fossies.org/linux/gdb/gdb/features/mips-dsp.xml)) only contain register definations of accumulator(hi, lo) 1~3 and dspctl, and the name array only store the relative position of the dsp registers in core_regs. \n\nIt is also the reason of changing the name order.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":1063,"context_line":"\tdsp_enabled \u003d (status_value \u0026 BIT(MIPS32_CP0_STATUS_MX_SHIFT)) !\u003d 0;"},{"line_number":1064,"context_line":"\tif (dsp_present) {"},{"line_number":1065,"context_line":"\t\tmips32-\u003edsp_imp \u003d ((ejtag_info-\u003econfig[3] \u0026 MIPS32_CONFIG3_DSPREV_MASK) \u003e\u003e MIPS32_CONFIG3_DSPREV_SHIFT) + 1;"},{"line_number":1066,"context_line":"\t\tLOG_USER(\"DSP implemented: %s, rev %d\", dsp_enabled ? \"yes\" : \"yes, disabled\", mips32-\u003edsp_imp);"},{"line_number":1067,"context_line":"\t} else {"},{"line_number":1068,"context_line":"\t\tLOG_USER(\"DSP implemented: %s\", \"no\");"},{"line_number":1069,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"6290286c_0b461de6","line":1066,"updated":"2024-09-13 10:31:06.000000000","message":"I prefer something like this:\n+   if (dsp_enabled) {\n+       LOG_USER(\"DSP implemented and enabled, rev %d\", mips32-\u003edsp_imp);\n+   } else {\n+       LOG_USER(\"DSP implemented but disabled, rev %d\", mips32-\u003edsp_imp);\n+   }","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":1063,"context_line":"\tdsp_enabled \u003d (status_value \u0026 BIT(MIPS32_CP0_STATUS_MX_SHIFT)) !\u003d 0;"},{"line_number":1064,"context_line":"\tif (dsp_present) {"},{"line_number":1065,"context_line":"\t\tmips32-\u003edsp_imp \u003d ((ejtag_info-\u003econfig[3] \u0026 MIPS32_CONFIG3_DSPREV_MASK) \u003e\u003e MIPS32_CONFIG3_DSPREV_SHIFT) + 1;"},{"line_number":1066,"context_line":"\t\tLOG_USER(\"DSP implemented: %s, rev %d\", dsp_enabled ? \"yes\" : \"yes, disabled\", mips32-\u003edsp_imp);"},{"line_number":1067,"context_line":"\t} else {"},{"line_number":1068,"context_line":"\t\tLOG_USER(\"DSP implemented: %s\", \"no\");"},{"line_number":1069,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8704cdc9_cbaca966","line":1066,"in_reply_to":"6290286c_0b461de6","updated":"2024-09-14 08:36:55.000000000","message":"Done","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":2182,"context_line":"\t\tcommand_print(CMD, \"0x%8.8x\", value);"},{"line_number":2183,"context_line":""},{"line_number":2184,"context_line":"\tmips32-\u003ecore_regs.dsp[index] \u003d value;"},{"line_number":2185,"context_line":"\tmips32-\u003ecore_cache-\u003ereg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty \u003d 1;"},{"line_number":2186,"context_line":""},{"line_number":2187,"context_line":"\treturn retval;"},{"line_number":2188,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8fd5fac7_793ddc41","line":2185,"updated":"2024-09-13 10:31:06.000000000","message":"Should we overwrite the value and mark it as dirty only if the value is actually changed and read did not failed?","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":2182,"context_line":"\t\tcommand_print(CMD, \"0x%8.8x\", value);"},{"line_number":2183,"context_line":""},{"line_number":2184,"context_line":"\tmips32-\u003ecore_regs.dsp[index] \u003d value;"},{"line_number":2185,"context_line":"\tmips32-\u003ecore_cache-\u003ereg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty \u003d 1;"},{"line_number":2186,"context_line":""},{"line_number":2187,"context_line":"\treturn retval;"},{"line_number":2188,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"31f6b1fb_8a389bcb","line":2185,"in_reply_to":"8fd5fac7_793ddc41","updated":"2024-09-14 08:36:55.000000000","message":"Done","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":2216,"context_line":"\t\tcommand_print(CMD, \"Error: could not write to dsp register %s\", CMD_ARGV[0]);"},{"line_number":2217,"context_line":""},{"line_number":2218,"context_line":"\tmips32-\u003ecore_regs.dsp[index] \u003d value;"},{"line_number":2219,"context_line":"\tmips32-\u003ecore_cache-\u003ereg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty \u003d 1;"},{"line_number":2220,"context_line":""},{"line_number":2221,"context_line":"\treturn retval;"},{"line_number":2222,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"5e527ac4_fc32a38a","line":2219,"updated":"2024-09-13 10:31:06.000000000","message":"Same here, update value and dirty flag only if we was able to write to the register.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":2216,"context_line":"\t\tcommand_print(CMD, \"Error: could not write to dsp register %s\", CMD_ARGV[0]);"},{"line_number":2217,"context_line":""},{"line_number":2218,"context_line":"\tmips32-\u003ecore_regs.dsp[index] \u003d value;"},{"line_number":2219,"context_line":"\tmips32-\u003ecore_cache-\u003ereg_list[MIPS32_REGLIST_DSP_INDEX + index].dirty \u003d 1;"},{"line_number":2220,"context_line":""},{"line_number":2221,"context_line":"\treturn retval;"},{"line_number":2222,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"4e5febdd_f0f3e90e","line":2219,"in_reply_to":"5e527ac4_fc32a38a","updated":"2024-09-14 08:36:55.000000000","message":"Done","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"0d27a3f1866f0f68361e94c5ffcde1737181e002","unresolved":true,"context_lines":[{"line_number":1066,"context_line":"\t\tif (dsp_enabled)"},{"line_number":1067,"context_line":"\t\t\tLOG_USER(\"DSP implemented: rev %d, enabled\", mips32-\u003edsp_imp);"},{"line_number":1068,"context_line":"\t\telse"},{"line_number":1069,"context_line":"\t\t\tLOG_USER(\"DSP implemented: rev %d, disabled\", mips32-\u003edsp_imp);"},{"line_number":1070,"context_line":""},{"line_number":1071,"context_line":"\t} else {"},{"line_number":1072,"context_line":"\t\tLOG_USER(\"DSP implemented: %s\", \"no\");"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"049d7076_159e3fe4","line":1069,"updated":"2024-09-17 08:17:34.000000000","message":"If you decided to go with this wording, then it is enough to have one\nLOG_USER(\"DSP implemented: rev %d, %s\"","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"d5bf3bfe988be8144b1f13e807d434a3cd309cd0","unresolved":false,"context_lines":[{"line_number":1066,"context_line":"\t\tif (dsp_enabled)"},{"line_number":1067,"context_line":"\t\t\tLOG_USER(\"DSP implemented: rev %d, enabled\", mips32-\u003edsp_imp);"},{"line_number":1068,"context_line":"\t\telse"},{"line_number":1069,"context_line":"\t\t\tLOG_USER(\"DSP implemented: rev %d, disabled\", mips32-\u003edsp_imp);"},{"line_number":1070,"context_line":""},{"line_number":1071,"context_line":"\t} else {"},{"line_number":1072,"context_line":"\t\tLOG_USER(\"DSP implemented: %s\", \"no\");"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"3c580c61_97c615ac","line":1069,"in_reply_to":"049d7076_159e3fe4","updated":"2024-09-18 08:51:39.000000000","message":"Done","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"}],"src/target/mips32_pracc.c":[{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":949,"context_line":"\t\t/* Struct of mips32_dsp_regs: {ac{hi, lo}1-3, dspctl} */"},{"line_number":950,"context_line":"\t\tuint32_t *dspr \u003d mips32-\u003ecore_regs.dsp;"},{"line_number":951,"context_line":"\t\t/* Starts from ac1 */"},{"line_number":952,"context_line":"\t\tfor (int i \u003d 0; i !\u003d 3; i++) {"},{"line_number":953,"context_line":"\t\t\tpracc_add_li32(\u0026ctx, 2, dspr[i * 2], 0);"},{"line_number":954,"context_line":"\t\t\tpracc_add_li32(\u0026ctx, 3, dspr[(i * 2) + 1], 0);"},{"line_number":955,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"9673437c_3e76f8c0","line":952,"updated":"2024-09-13 10:31:06.000000000","message":"3 ist the ARRAY_SIZE(mips32-\u003ecore_regs.dsp) / 2?","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":949,"context_line":"\t\t/* Struct of mips32_dsp_regs: {ac{hi, lo}1-3, dspctl} */"},{"line_number":950,"context_line":"\t\tuint32_t *dspr \u003d mips32-\u003ecore_regs.dsp;"},{"line_number":951,"context_line":"\t\t/* Starts from ac1 */"},{"line_number":952,"context_line":"\t\tfor (int i \u003d 0; i !\u003d 3; i++) {"},{"line_number":953,"context_line":"\t\t\tpracc_add_li32(\u0026ctx, 2, dspr[i * 2], 0);"},{"line_number":954,"context_line":"\t\t\tpracc_add_li32(\u0026ctx, 3, dspr[(i * 2) + 1], 0);"},{"line_number":955,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8d46ba74_ac0aa223","line":952,"in_reply_to":"9673437c_3e76f8c0","updated":"2024-09-14 08:36:55.000000000","message":"Kind of, `mips32-\u003ecore_regs.dsp` has 7 registers. I changed it to `(...dsp - 1) / 2`.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":1182,"context_line":""},{"line_number":1183,"context_line":"\t\t/* Struct of mips32_dsp_regs: {ac{hi, lo}1-3, dspctl} */"},{"line_number":1184,"context_line":"\t\t/* Starts from ac1 */"},{"line_number":1185,"context_line":"\t\tfor (int i \u003d 0; i !\u003d 3; i++) {"},{"line_number":1186,"context_line":"\t\t\tsize_t offset_hi \u003d offset_dsp + ((i * 2) * 4);"},{"line_number":1187,"context_line":"\t\t\tsize_t offset_lo \u003d offset_dsp + (((i * 2) + 1) * 4);"},{"line_number":1188,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"3d062bfb_8aee2992","line":1185,"updated":"2024-09-13 10:31:06.000000000","message":"3 ist the ARRAY_SIZE(mips32-\u003ecore_regs.dsp) / 2?","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":1182,"context_line":""},{"line_number":1183,"context_line":"\t\t/* Struct of mips32_dsp_regs: {ac{hi, lo}1-3, dspctl} */"},{"line_number":1184,"context_line":"\t\t/* Starts from ac1 */"},{"line_number":1185,"context_line":"\t\tfor (int i \u003d 0; i !\u003d 3; i++) {"},{"line_number":1186,"context_line":"\t\t\tsize_t offset_hi \u003d offset_dsp + ((i * 2) * 4);"},{"line_number":1187,"context_line":"\t\t\tsize_t offset_lo \u003d offset_dsp + (((i * 2) + 1) * 4);"},{"line_number":1188,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"cc4c0a99_91fb5a82","line":1185,"in_reply_to":"3d062bfb_8aee2992","updated":"2024-09-14 08:36:55.000000000","message":"Same above.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":1184,"context_line":"\t\t/* Starts from ac1 */"},{"line_number":1185,"context_line":"\t\tfor (int i \u003d 0; i !\u003d 3; i++) {"},{"line_number":1186,"context_line":"\t\t\tsize_t offset_hi \u003d offset_dsp + ((i * 2) * 4);"},{"line_number":1187,"context_line":"\t\t\tsize_t offset_lo \u003d offset_dsp + (((i * 2) + 1) * 4);"},{"line_number":1188,"context_line":""},{"line_number":1189,"context_line":"\t\t\t/* DSP Ac registers starts from 1, therefore i + 1 */"},{"line_number":1190,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MFHI(8, i + 1));"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"00efddd3_86a112be","line":1187,"updated":"2024-09-13 10:31:06.000000000","message":"It will be good to demystify this numbers.","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":1184,"context_line":"\t\t/* Starts from ac1 */"},{"line_number":1185,"context_line":"\t\tfor (int i \u003d 0; i !\u003d 3; i++) {"},{"line_number":1186,"context_line":"\t\t\tsize_t offset_hi \u003d offset_dsp + ((i * 2) * 4);"},{"line_number":1187,"context_line":"\t\t\tsize_t offset_lo \u003d offset_dsp + (((i * 2) + 1) * 4);"},{"line_number":1188,"context_line":""},{"line_number":1189,"context_line":"\t\t\t/* DSP Ac registers starts from 1, therefore i + 1 */"},{"line_number":1190,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MFHI(8, i + 1));"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"de898d8e_059ee024","line":1187,"in_reply_to":"00efddd3_86a112be","updated":"2024-09-14 08:36:55.000000000","message":"Done","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"a3784a1e04bdb66255cd70f010c5fa4354f14ede","unresolved":true,"context_lines":[{"line_number":1198,"context_line":"\t\t/* DSPCTL is the last element of register store */"},{"line_number":1199,"context_line":"\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_RDDSP(8, 0x3F));"},{"line_number":1200,"context_line":"\t\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT + offset_dsp + (6 * 4),"},{"line_number":1201,"context_line":"\t\t\t\t  MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_dsp + (6 * 4), 1));"},{"line_number":1202,"context_line":""},{"line_number":1203,"context_line":"\t\tmips32_pracc_store_regs_restore(\u0026ctx);"},{"line_number":1204,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ea25ea92_f0cfd5c5","line":1201,"updated":"2024-09-13 10:31:06.000000000","message":"Please, replace hardcoded offsets like (6 * 4) with calculated offsets. I assume 4 is sizeof(uint32_t).","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"348780e3bdad09ee48b289cfc12ad4d8d4ef613a","unresolved":false,"context_lines":[{"line_number":1198,"context_line":"\t\t/* DSPCTL is the last element of register store */"},{"line_number":1199,"context_line":"\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_RDDSP(8, 0x3F));"},{"line_number":1200,"context_line":"\t\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT + offset_dsp + (6 * 4),"},{"line_number":1201,"context_line":"\t\t\t\t  MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_dsp + (6 * 4), 1));"},{"line_number":1202,"context_line":""},{"line_number":1203,"context_line":"\t\tmips32_pracc_store_regs_restore(\u0026ctx);"},{"line_number":1204,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"86ae0e7c_541adbf7","line":1201,"in_reply_to":"ea25ea92_f0cfd5c5","updated":"2024-09-14 08:36:55.000000000","message":"Yes, 6 is the index of last element of core_regs.dsp and 4 is sizeof(uint32_t).","commit_id":"264fd805d6c73730e8b3aec523629cb76f600c02"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"0d27a3f1866f0f68361e94c5ffcde1737181e002","unresolved":true,"context_lines":[{"line_number":955,"context_line":"\t\t\tpracc_add_li32(\u0026ctx, 3, dspr[(ac * 2) + 1], 0);"},{"line_number":956,"context_line":""},{"line_number":957,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MTHI(2, ac + 1));"},{"line_number":958,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MTLO(3, ac + 1));"},{"line_number":959,"context_line":"\t\t}"},{"line_number":960,"context_line":""},{"line_number":961,"context_line":"\t\t/* DSPCTL is the last element of register store */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"754c7854_a28e131e","line":958,"updated":"2024-09-17 08:17:34.000000000","message":"I still can\u0027t wrap my brain around, why in first part of this scope we have:\n[ac * 2]\n[(ac * 2) + 1]\npattern, and in the second part we have:\nac + 1\nac + 1\n\nIt looks suspicious without diving deeper in code (which i can\u0027t do right now.\nPlease, add more comments. Explain the arithmetic you are doing.","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"d5bf3bfe988be8144b1f13e807d434a3cd309cd0","unresolved":true,"context_lines":[{"line_number":955,"context_line":"\t\t\tpracc_add_li32(\u0026ctx, 3, dspr[(ac * 2) + 1], 0);"},{"line_number":956,"context_line":""},{"line_number":957,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MTHI(2, ac + 1));"},{"line_number":958,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MTLO(3, ac + 1));"},{"line_number":959,"context_line":"\t\t}"},{"line_number":960,"context_line":""},{"line_number":961,"context_line":"\t\t/* DSPCTL is the last element of register store */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"97efcdd9_c69a9eaa","line":958,"in_reply_to":"754c7854_a28e131e","updated":"2024-09-18 08:51:39.000000000","message":"I have added more explaining in comments and changed wording of variable names, lets see if this makes more sense.\n\nIf you find using an array of r/w instructions is more self explanatory, I can change it to that form, or write the execution order in a comment.","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"4a83b82eade4aedb0b283acde5ddecc20ef3327f","unresolved":false,"context_lines":[{"line_number":955,"context_line":"\t\t\tpracc_add_li32(\u0026ctx, 3, dspr[(ac * 2) + 1], 0);"},{"line_number":956,"context_line":""},{"line_number":957,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MTHI(2, ac + 1));"},{"line_number":958,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MTLO(3, ac + 1));"},{"line_number":959,"context_line":"\t\t}"},{"line_number":960,"context_line":""},{"line_number":961,"context_line":"\t\t/* DSPCTL is the last element of register store */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"3639cdb1_caa562a9","line":958,"in_reply_to":"97efcdd9_c69a9eaa","updated":"2024-09-23 08:24:51.000000000","message":"Done","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"},{"author":{"_account_id":1000410,"name":"Oleksij Rempel","email":"linux@rempel-privat.de","username":"olerem"},"change_message_id":"0d27a3f1866f0f68361e94c5ffcde1737181e002","unresolved":true,"context_lines":[{"line_number":1195,"context_line":"\t\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_hi, 1));"},{"line_number":1196,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MFLO(8, ac + 1));"},{"line_number":1197,"context_line":"\t\t\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT + offset_lo,"},{"line_number":1198,"context_line":"\t\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_lo, 1));"},{"line_number":1199,"context_line":"\t\t}"},{"line_number":1200,"context_line":""},{"line_number":1201,"context_line":"\t\t/* DSPCTL is the last element of register store */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"6246321c_e4b73b3f","line":1198,"updated":"2024-09-17 08:17:34.000000000","message":"Same here, we have two accumulators ac + 0, and ac + 1 on the top, and used ac + 1 and ac + 1 on the button. Why? From your perspective it may be a stupid question, but from reader perspective i just miss complete understanding process you already had :)","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"d5bf3bfe988be8144b1f13e807d434a3cd309cd0","unresolved":true,"context_lines":[{"line_number":1195,"context_line":"\t\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_hi, 1));"},{"line_number":1196,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MFLO(8, ac + 1));"},{"line_number":1197,"context_line":"\t\t\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT + offset_lo,"},{"line_number":1198,"context_line":"\t\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_lo, 1));"},{"line_number":1199,"context_line":"\t\t}"},{"line_number":1200,"context_line":""},{"line_number":1201,"context_line":"\t\t/* DSPCTL is the last element of register store */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"9f6b8993_35991665","line":1198,"in_reply_to":"6246321c_e4b73b3f","updated":"2024-09-18 08:51:39.000000000","message":"Same above.","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"},{"author":{"_account_id":1002186,"name":"Walter J.","display_name":"Walter Ji","email":"walter.ji@oss.cipunited.com","username":"709924470","status":"Currently working at CIP United Co., Ltd."},"change_message_id":"4a83b82eade4aedb0b283acde5ddecc20ef3327f","unresolved":false,"context_lines":[{"line_number":1195,"context_line":"\t\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_hi, 1));"},{"line_number":1196,"context_line":"\t\t\tpracc_add(\u0026ctx, 0, MIPS32_DSP_MFLO(8, ac + 1));"},{"line_number":1197,"context_line":"\t\t\tpracc_add(\u0026ctx, MIPS32_PRACC_PARAM_OUT + offset_lo,"},{"line_number":1198,"context_line":"\t\t\t\t\tMIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + offset_lo, 1));"},{"line_number":1199,"context_line":"\t\t}"},{"line_number":1200,"context_line":""},{"line_number":1201,"context_line":"\t\t/* DSPCTL is the last element of register store */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"6629541c_02a5403b","line":1198,"in_reply_to":"9f6b8993_35991665","updated":"2024-09-23 08:24:51.000000000","message":"Done","commit_id":"5f978c36cabc47f5e501fe546f1c4565195e1a1e"}]}