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\u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/59/8559/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/59/8559/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/59/8559/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/59/8559/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"8d7bf3ce9e07a3f1c931a843380da93b1605e51f","subject":"target: riscv: enable jtag comms via tunnelling to a soft processor"}],"author":{"name":"Conor Paxton","email":"conor.paxton@microchip.com","date":"2024-06-18 21:09:12.000000000","tz":60},"committer":{"name":"Conor Paxton","email":"conor.paxton@microchip.com","date":"2024-11-05 01:40:52.000000000","tz":0},"subject":"target: riscv: resume all thread group members when run algorithm","message":"target: riscv: resume all thread group members when run algorithm\n\nWhen there are multiple harts in the same thread group, all harts should\nbe resumed, not just the hart that runs the algorithm code.\n\nThis may be different for multi processor configurations.\n\nChange-Id: I46e85d58c2b04d8ea53d2e8f7e41fc03ab1f9815\nSigned-off-by: Tommy Murphy \u003ctommy_murphy@hotmail.com\u003e\nSigned-off-by: Anton Krug \u003canton.krug@gmail.com\u003e\nSigned-off-by: Daire McNamara \u003cdaire.mcnamara@microchip.com\u003e\nSigned-off-by: Matteo Bonicolini \u003cmatteo.bonicolini@microchip.com\u003e\nSigned-off-by: Conor Paxton \u003cconor.paxton@microchip.com\u003e\n"}}},"requirements":[],"submit_records":[],"submit_requirements":[]}