)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"5cd0056dc3bca997aa4bedd130a61037a9daf853","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"5ae53616_eb6c3b83","updated":"2024-11-12 12:27:20.000000000","message":"I\u0027ve just tested this patch using stlink v2 and stlink v3, using dapdirect mode and hla mode and also using swd and jtag interfaces. I\u0027ve checked different speeds and verified clk frequencies with logic analyzer. Nrf51822 works now fine in dapdirect mode.\nThanks Antonio for patch!\nI think that this patch can be merged.","commit_id":"04cc91a1585b8506aae2e2cea486e4073cd76e0a"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"1b9c9619ef96a107348961079927285d9526d18e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"68ecd8bd_29fef8ef","updated":"2024-11-12 10:19:24.000000000","message":"Testing dapdirect mode with stlink v2 and nrf51822 I noticed that openocd fails to connect to this microcontroller. HLA mode worked fine.I spent some time to diagnose the problem. Using a logic analyzer, I noticed that the initialization sequence when debugger is connecting to the microcontroller\u0027s SWD line (reset line, switching jtag to swd, reset line, read IDCODE etc.) takes place at a CLK frequency of 5 kHz, regardless of the frequency set in the configuration. For HLA mode frequency was ok.\nI added some logs to source code and I found that variable initial_interface_speed in param struct has value 0 at init sequence (for dapdirect). SWD frequency is set to required value after init function.\n(Un)Fortunatelly nrf51822 has requirement for SWDCLK frequency that it has to be above 125kHz (SWDIO line is common with RESET). This helped to observe this issue.\nI tested stlinks v2 and v3 without connected any microcontrollers and I observed waveforms on stlink output lines using logic analyzer. For dapdirect mode CLK frequency was always at the lowest possible value for v2 and v3 stlinks, both in swd and jtag mode.","commit_id":"04cc91a1585b8506aae2e2cea486e4073cd76e0a"}]}