)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"71a1156512e7d5eb727c3a06429e3c2f4a792f2c","unresolved":true,"context_lines":[{"line_number":11,"context_line":""},{"line_number":12,"context_line":"The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory"},{"line_number":13,"context_line":"which can be programmed directly. Since it does not fit in the current"},{"line_number":14,"context_line":"flash memory infrastructure of OpenOCD there is no NVM support so far."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0"},{"line_number":17,"context_line":"Signed-off-by: Marc Schink \u003cdev@zapb.de\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"37b9ccce_f1762947","line":14,"updated":"2024-12-01 22:29:19.000000000","message":"It would be nice to have a flash emulation based on target\u0027s SRAM. It should work for RRAM too, apart side protections or mass erase, if they exist.\nSuch driver will be reported by OpenOCD to GDB in the target memory map, preventing GDB to use SW breakpoints in the RRAM area.\n\nThere is already a dummy flash driver named \u0027faux\u0027. It allocates an area on host to emulate a flash.\nIt should not be difficult to replace the host with target memory using some target_read_buffer() and target_write_buffer().","commit_id":"606f8efbb8eee2094421ee00941ac38a9a507a47"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"5daf9b4a5e8fe7b576cfb88186bda50cc2288cc4","unresolved":true,"context_lines":[{"line_number":11,"context_line":""},{"line_number":12,"context_line":"The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory"},{"line_number":13,"context_line":"which can be programmed directly. Since it does not fit in the current"},{"line_number":14,"context_line":"flash memory infrastructure of OpenOCD there is no NVM support so far."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0"},{"line_number":17,"context_line":"Signed-off-by: Marc Schink \u003cdev@zapb.de\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"5faafe68_d0d4cb45","line":14,"in_reply_to":"37b9ccce_f1762947","updated":"2024-12-02 14:54:44.000000000","message":"We could write a \"NOR flash\" driver for it, with a single sector of the entire RRAM and the write performance would also probably benefit from a \"loader\" script. But I\u0027m not sure if that\u0027s the best way we should proceed or if we start to add a more general \"nvm\" subsystem instead of abusing the \"NOR flash\" one. What do you think?\n\nIn any case this should be done in an additional patch.","commit_id":"606f8efbb8eee2094421ee00941ac38a9a507a47"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b1938f72ff55129e40c0fdf50fabf60102f08fab","unresolved":true,"context_lines":[{"line_number":11,"context_line":""},{"line_number":12,"context_line":"The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory"},{"line_number":13,"context_line":"which can be programmed directly. Since it does not fit in the current"},{"line_number":14,"context_line":"flash memory infrastructure of OpenOCD there is no NVM support so far."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0"},{"line_number":17,"context_line":"Signed-off-by: Marc Schink \u003cdev@zapb.de\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"070da6db_951013c4","line":14,"in_reply_to":"4b09a940_907233aa","updated":"2025-01-25 17:50:17.000000000","message":"No I didn\u0027t. For the moment I\u0027m happy with the hack:\n```\nproc rram_wr { enable } {\n        set RRAMC_CONFIG 0x5004b500\n        set RRAMC_TASKS_COMMITWRITEBUF 0x5004b008\n        if { $enable } {\n                mww $RRAMC_CONFIG 0x101\n        } else {\n                mww $RRAMC_TASKS_COMMITWRITEBUF 1\n                mww $RRAMC_CONFIG 0\n        }\n}\n```\nand using `load_image`. I admit we need \"flash\" driver to pass memory map to gdb and enable gdb `load`, however I have no time to write it. Feel free to work on it.","commit_id":"606f8efbb8eee2094421ee00941ac38a9a507a47"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"2d60c6c8ef440b73a98c28c34ba19809058337d6","unresolved":true,"context_lines":[{"line_number":11,"context_line":""},{"line_number":12,"context_line":"The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory"},{"line_number":13,"context_line":"which can be programmed directly. Since it does not fit in the current"},{"line_number":14,"context_line":"flash memory infrastructure of OpenOCD there is no NVM support so far."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0"},{"line_number":17,"context_line":"Signed-off-by: Marc Schink \u003cdev@zapb.de\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"7b60fc3b_0919d6f5","line":14,"in_reply_to":"5faafe68_d0d4cb45","updated":"2025-01-15 17:02:53.000000000","message":"Hi Marc,\nI just get the dev kit so I played with it a little bit.\n\nActually OpenOCD supports external SPI FRAM chips which are very similar from the view of programming. Of course they are only emulated as a flash of one sector with no-op erase. I\u0027m not convinced that a new subsystem would be worth to implement. FRAMs and RRAMs are functionally subset of what is implemented in flash subsystem: they have no sectors, no sector erase and also erase check is almost useless. Future will show if these non-volatile RAMs spread wider or stay as a rare curiosity.\n\nBTW: After enabling buffered RRAM write (buffer size 1x 128-bit word)\n`mww 0x5004b500 0x101`\nand increasing\n`nrf54l.dap memaccess 12` to prevent WAITs treated as error\ncommand `load_image` works just fine:\n```\n65536 bytes written at address 0x00130000\ndownloaded 65536 bytes in 1.382572s (46.291 KiB/s)\n```\nOne RRAM read or triggering TASKS_COMMITWRITEBUF is necessary to commit not aligned end of image.","commit_id":"606f8efbb8eee2094421ee00941ac38a9a507a47"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"c941c02c9bf1544a06e348ad10c73569b50fe1bc","unresolved":true,"context_lines":[{"line_number":11,"context_line":""},{"line_number":12,"context_line":"The nRFL54L series uses resistive RAM (RRAM) as non-volatile memory"},{"line_number":13,"context_line":"which can be programmed directly. Since it does not fit in the current"},{"line_number":14,"context_line":"flash memory infrastructure of OpenOCD there is no NVM support so far."},{"line_number":15,"context_line":""},{"line_number":16,"context_line":"Change-Id: I9934af4fd3bb8b7272954fc4b17638c7dabbbee0"},{"line_number":17,"context_line":"Signed-off-by: Marc Schink \u003cdev@zapb.de\u003e"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"4b09a940_907233aa","line":14,"in_reply_to":"7b60fc3b_0919d6f5","updated":"2025-01-25 15:54:42.000000000","message":"\u003e Actually OpenOCD supports external SPI FRAM chips which are very similar from the view of programming. Of course they are only emulated as a flash of one sector with no-op erase. I\u0027m not convinced that a new subsystem would be worth to implement. FRAMs and RRAMs are functionally subset of what is implemented in flash subsystem: they have no sectors, no sector erase and also erase check is almost useless. Future will show if these non-volatile RAMs spread wider or stay as a rare curiosity.\n\nYes, a new subsystem is probably not the correct term for what I meant. I think a modification of the current \u0027flash\u0027 subsystem in terms of available commands, wording etc. would be sufficient. So that other NVM technologies can be represented well and the term \u0027flash\u0027 does not lead to confusion.\n\nDid you implement a simple flash driver for your test? Are you going to push a patch for it?","commit_id":"606f8efbb8eee2094421ee00941ac38a9a507a47"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"71a1156512e7d5eb727c3a06429e3c2f4a792f2c","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"84132317_b2b24d75","updated":"2024-12-01 22:29:19.000000000","message":"Thanks","commit_id":"606f8efbb8eee2094421ee00941ac38a9a507a47"}],"tcl/target/nordic/nrf54l.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"2d60c6c8ef440b73a98c28c34ba19809058337d6","unresolved":true,"context_lines":[{"line_number":30,"context_line":"transport select swd"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID"},{"line_number":33,"context_line":"dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":36,"context_line":"target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"431f6e62_f75af204","line":33,"updated":"2025-01-15 17:02:53.000000000","message":"The swd multidrop support is probably same as nrf53 has. Could be copied from tcl/target/nrf53.cfg except the comment where is TINSTANCE sourced from: although RM references UICR.TINSTANCE, it doesn\u0027t exist. Perhaps TAD.TINSTANCE is used - but it does not work either. I\u0027ll ask Nordic Semi support and eventually submit a patch.","commit_id":"4d1b3cbafc7a1bf44ca695103cf4701d8e8ef8e9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4ad0a2a5533bccfe4f8386c434bf1757714dc2ff","unresolved":false,"context_lines":[{"line_number":30,"context_line":"transport select swd"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID"},{"line_number":33,"context_line":"dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":36,"context_line":"target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"80d7a7af_1f58916d","line":33,"in_reply_to":"31523bac_81f63b6f","updated":"2025-02-16 11:54:35.000000000","message":"See\n8752: tcl/target/nordic/nrf54l: minor corrections | https://review.openocd.org/c/openocd/+/8752","commit_id":"4d1b3cbafc7a1bf44ca695103cf4701d8e8ef8e9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b1938f72ff55129e40c0fdf50fabf60102f08fab","unresolved":true,"context_lines":[{"line_number":30,"context_line":"transport select swd"},{"line_number":31,"context_line":""},{"line_number":32,"context_line":"swd newdap $_CHIPNAME cpu -expected-id $_CPUTAPID"},{"line_number":33,"context_line":"dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu"},{"line_number":34,"context_line":""},{"line_number":35,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":36,"context_line":"target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap -ap-num 0"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"31523bac_81f63b6f","line":33,"in_reply_to":"431f6e62_f75af204","updated":"2025-01-25 17:50:17.000000000","message":"https://devzone.nordicsemi.com/f/nordic-q-a/118254/how-to-set-nrf54l-device-swd-multidrop-instance-id","commit_id":"4d1b3cbafc7a1bf44ca695103cf4701d8e8ef8e9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"2d60c6c8ef440b73a98c28c34ba19809058337d6","unresolved":true,"context_lines":[{"line_number":37,"context_line":""},{"line_number":38,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"# Create target for the control access port (CTRL-AP)."},{"line_number":41,"context_line":"target create $_CHIPNAME.ctrl mem_ap -dap $_CHIPNAME.dap -ap-num 1"},{"line_number":42,"context_line":""},{"line_number":43,"context_line":"adapter speed 1000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"5437d778_644d00ca","line":40,"range":{"start_line":40,"start_character":2,"end_line":40,"end_character":53},"updated":"2025-01-15 17:02:53.000000000","message":"Actually CTRL-AP is -ap-num 2 and AFAIK it\u0027s not a mem-ap.\n`_nrf_ctrl_ap_recover` from `tcl/target/nrf_common.cfg` could be usable after small modification of IDR version check.\n\nap-num 1 is described in\nhttps://docs.nordicsemi.com/bundle/ps_nrf54L15/page/debug.html\nas AUX access port. TBH I have no idea what is the AP connected to.\nI made a Tcl loop to check all addresses from 0 with incr 0x10000,\nthen also from 0x44, 0x444 (expected RISC-V DMSTATUS) and 0xfffc (a possible ROM table). No one readable word was found.\n\nMaybe the AP #1 is prepared for nRF54H and has no function in nRF54L? I\u0027ll ask at Nordic Semi.","commit_id":"4d1b3cbafc7a1bf44ca695103cf4701d8e8ef8e9"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"c941c02c9bf1544a06e348ad10c73569b50fe1bc","unresolved":true,"context_lines":[{"line_number":37,"context_line":""},{"line_number":38,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"# Create target for the control access port (CTRL-AP)."},{"line_number":41,"context_line":"target create $_CHIPNAME.ctrl mem_ap -dap $_CHIPNAME.dap -ap-num 1"},{"line_number":42,"context_line":""},{"line_number":43,"context_line":"adapter speed 1000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"ac07d16a_fb10877d","line":40,"range":{"start_line":40,"start_character":2,"end_line":40,"end_character":53},"in_reply_to":"5437d778_644d00ca","updated":"2025-01-25 15:54:42.000000000","message":"Oh, I confused both APs then. Yes, it should be connected to the RISC-V core (VPR), according to the datasheet. However, I was also not able to find a readable address. Let me know if you have feedback from Nordic.","commit_id":"4d1b3cbafc7a1bf44ca695103cf4701d8e8ef8e9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b1938f72ff55129e40c0fdf50fabf60102f08fab","unresolved":true,"context_lines":[{"line_number":37,"context_line":""},{"line_number":38,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"# Create target for the control access port (CTRL-AP)."},{"line_number":41,"context_line":"target create $_CHIPNAME.ctrl mem_ap -dap $_CHIPNAME.dap -ap-num 1"},{"line_number":42,"context_line":""},{"line_number":43,"context_line":"adapter speed 1000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"f103cfe1_b530eff6","line":40,"range":{"start_line":40,"start_character":2,"end_line":40,"end_character":53},"in_reply_to":"ac07d16a_fb10877d","updated":"2025-01-25 17:50:17.000000000","message":"So far they sent me just a confirmation that `An engineer has been assigned to`\n\nhttps://devzone.nordicsemi.com/f/nordic-q-a/118258/nrf54l-aux-ap-access-port-description-and-usage\n\nBTW The RISC-V debug DM over MEM-AP code I wrote for RP2350 needs just a trivial patch to connect RISC-V core in nRF54L - it communicates over the registers exposed @ 0x4004C000 / 0x5004C000 of APP-AP (AP ID 0).\nThe code lives here:\nhttps://github.com/tom-van/openocd-rp2350-riscv\nUnfortunately not easy to merge to the upstream as it depends on newer RISC-V code from RISC-V colab fork.","commit_id":"4d1b3cbafc7a1bf44ca695103cf4701d8e8ef8e9"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4ad0a2a5533bccfe4f8386c434bf1757714dc2ff","unresolved":false,"context_lines":[{"line_number":37,"context_line":""},{"line_number":38,"context_line":"$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0"},{"line_number":39,"context_line":""},{"line_number":40,"context_line":"# Create target for the control access port (CTRL-AP)."},{"line_number":41,"context_line":"target create $_CHIPNAME.ctrl mem_ap -dap $_CHIPNAME.dap -ap-num 1"},{"line_number":42,"context_line":""},{"line_number":43,"context_line":"adapter speed 1000"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"eab09223_347b5e20","line":40,"range":{"start_line":40,"start_character":2,"end_line":40,"end_character":53},"in_reply_to":"f103cfe1_b530eff6","updated":"2025-02-16 11:54:35.000000000","message":"Continues here\n8752: tcl/target/nordic/nrf54l: minor corrections | https://review.openocd.org/c/openocd/+/8752","commit_id":"4d1b3cbafc7a1bf44ca695103cf4701d8e8ef8e9"}]}