)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1002340,"name":"Nicolas Derumigny","display_name":"Nicolas Derumigny","email":"nicolas.derumigny@inria.fr","username":"NicolasDerumigny","status":"Post Doc - Inria"},"change_message_id":"e36b6124096a33853c207301b8720a6a1f4b2d9b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"0ac0ffc9_28fd3e40","updated":"2024-12-12 09:25:40.000000000","message":"Hi,\nThanks a lot to have added me as a reviewer! Sadly, I do not have a PCIe board to test this patch and I do not master JTAG signaling, so I pass my turn here. I can however test this on my AXI branch, can you provide a sequence of commands that is fixed by this patch?","commit_id":"d652a017ca38ade1ee1c61c79d1ddf4c82806956"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a8ec4c1f964d48fd836ab9ffb64e3eae6dfc1e84","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"08c12239_ea5677fd","updated":"2025-06-21 09:36:45.000000000","message":"This would create a conflict with\nhttps://review.openocd.org/c/openocd/+/8595\nbut it has to be rebased on current master, so not a big deal","commit_id":"d652a017ca38ade1ee1c61c79d1ddf4c82806956"},{"author":{"_account_id":1002346,"name":"Henrik Brix Andersen","email":"henrik@brixandersen.dk","username":"henrikbrixandersen"},"change_message_id":"a603739175b14720828ec69b0c663d81be6d8623","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"6ba82c1c_4091a50f","in_reply_to":"0ac0ffc9_28fd3e40","updated":"2024-12-12 09:55:59.000000000","message":"Hi,\n\nI do not have a PCIe card with a Xilinx Debug Bridge on it either, but I was in the process of resurrecting the original xlnx-axi-xvc changeset and encountered this bug.\n\nI have just tested with your AXI branch (and this fix), works fine for JTAG connections towards both external Xilinx Artix-7 FPGAs and Altera MAX-V CPLDs.\n\nWithout this patch, a simple `pathmove RESET RUN/IDLE` will show a wrong state transition (wrong TMS polarity) using your AXI branch.","commit_id":"d652a017ca38ade1ee1c61c79d1ddf4c82806956"},{"author":{"_account_id":1002346,"name":"Henrik Brix Andersen","email":"henrik@brixandersen.dk","username":"henrikbrixandersen"},"change_message_id":"76a04a2183f216b99d9da323010cc80ff2224b22","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"db8db092_76fd1353","in_reply_to":"497bdc3c_a27efd26","updated":"2024-12-16 15:51:48.000000000","message":"Done","commit_id":"d652a017ca38ade1ee1c61c79d1ddf4c82806956"},{"author":{"_account_id":1002346,"name":"Henrik Brix Andersen","email":"henrik@brixandersen.dk","username":"henrikbrixandersen"},"change_message_id":"f4231d3b48e4556325035fedbfc941e1c4c1cd24","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"74396cad_a12df6c7","in_reply_to":"6ba82c1c_4091a50f","updated":"2024-12-16 11:45:50.000000000","message":"Hi,\n\nI see you have incorporated this change in your AXI branch, thanks. Could you please review it here as well in order to get the bug fix merged?","commit_id":"d652a017ca38ade1ee1c61c79d1ddf4c82806956"},{"author":{"_account_id":1002340,"name":"Nicolas Derumigny","display_name":"Nicolas Derumigny","email":"nicolas.derumigny@inria.fr","username":"NicolasDerumigny","status":"Post Doc - Inria"},"change_message_id":"707ad39bc66e0dbdc04d77eac28fbe828490e4ad","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"497bdc3c_a27efd26","in_reply_to":"74396cad_a12df6c7","updated":"2024-12-16 15:03:34.000000000","message":"Hi!\nI do not have a lot of knowledge about the low-level JTAG commands, but I have successfully compile and tested on a ZCU104 board and a softcore on the FPGA that I encounter no regression. As far as I can tell, this is ready to be merged.","commit_id":"d652a017ca38ade1ee1c61c79d1ddf4c82806956"}]}