)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"869782ccbaf578da492c9f9d9f021eeaf4ef387f","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"5ef2fe89_b6d9f547","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"updated":"2025-01-27 07:57:47.000000000","message":"What some MCU?\n\nDo they conform to RISC-V debug spec or is it a quirk?","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"9b3b92f85f752858369ea5242aaefc854c418e81","unresolved":false,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"ba11a261_0ab0740b","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"in_reply_to":"5ef2fe89_b6d9f547","updated":"2025-01-27 10:11:46.000000000","message":"It\u0027s not a quirk, but a correct procedure I believe. Because when reset_haltreq is set, when exiting this function, device is expected to be halted. And a halted state needs to be confirmed explicitly by checking DM_DMCONTROL_ALLHALTED. For now, HPMicro MCUs are facing such issue, but I believe it might be a general problem.","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"f681909e95c47c1698291af691ba867862d4c2ef","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"794bb812_900eb06b","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"in_reply_to":"69ed93dc_d044deac","updated":"2025-01-27 11:31:14.000000000","message":"But according to the funciton\u0027s intension, it needs target to be halted on exit when reset_haltreq is set, right? But halt state can only be guaranteeded when ALLHALTED is set. So I believe this change can make sure the function does what is expected when reset_haltreq is set.","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"64bf8087b5bb9c0cb55cd5c3082e72dea96b3261","unresolved":false,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"56a09987_fa8dab1f","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"in_reply_to":"7768d128_351aa7e9","updated":"2025-01-27 13:28:19.000000000","message":"But it does change target status to TARGET_HALTED. please refer to line 2444","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"3cac4960103ad92c1f0f930d41988329806787f2","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"a3fb4ce2_0b7ec72b","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"in_reply_to":"794bb812_900eb06b","updated":"2025-01-27 12:28:13.000000000","message":"IMHO, this is a quirk.\nPlease see [3.2. Reset Control] (RISC-V Debug Spec. Version 1.0.0-rc4, Revised 2024-12-05):\n\u003e When a hart comes out of reset and `haltreq` or `hasresethaltreq` are set, the hart will immediately enter Debug Mode (halted state).\n\nHowever, this exact change is classifyed as a bugfix in the spec (listed under [1.2.1.1. Bugfixes from 0.13 to 1.0]).\n\nThough looking at the comments this is more of a clarification:\nhttps://github.com/riscv/riscv-debug-spec/pull/419#issuecomment-452856148","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1a8f947d4a703ef713c9f9bc41cec47e51a9eb42","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"7768d128_351aa7e9","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"in_reply_to":"a3fb4ce2_0b7ec72b","updated":"2025-01-27 13:26:00.000000000","message":"Thanks for valuable info, Evgeniy!!\n\n@Qian, Evgeniy:\n\n\u003e But according to the funciton\u0027s intension, it needs target to be halted on exit \n\u003e when reset_haltreq is set, right?\n\nThe function `reset_deassert()` does NOT guarantee the target is halted on its exit. As the name suggests, it handles reset deassert, nothing more.\nActual waiting for halted state after `reset halt` is handled in Tcl, see:\nhttps://review.openocd.org/c/openocd/+/8725/4/src/target/startup.tcl#140\n\nNote that a pluggable event `reset-deassert-post` is called between `reset_deassert()` and `arp_waitstate halted 1000`\n\nSo to keep other RISC-V targets intact and not to diverge from other targets we should leave HALTREQ set on `reset_deassert()` exit and clear HALTREQ later: perhaps when poll detects halt. Would it be possible?","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"45af051d4d6339459accde3c2077c38209b7f28a","unresolved":false,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"76385629_901c216c","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"in_reply_to":"a3fb4ce2_0b7ec72b","updated":"2025-01-27 13:13:02.000000000","message":"This change is for 0.13, as it does requires HW halts immediately out of reset.","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"8cf218140e6cff8d7fa35d24b33dc49164bb7e45","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"target/riscv: make sure target is halted when reset_halt is set"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"- some MCU will need certain period of time to be halted after ndmreset"},{"line_number":10,"context_line":"  is issued, so in deassert_reset, it needs to make sure MCU is halted"},{"line_number":11,"context_line":"  before clearing DM_DMCONTROL_HALTREQ."},{"line_number":12,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":2,"id":"69ed93dc_d044deac","line":9,"range":{"start_line":9,"start_character":2,"end_line":9,"end_character":10},"in_reply_to":"ba11a261_0ab0740b","updated":"2025-01-27 10:54:32.000000000","message":"Don\u0027t think so. With the exception of GD32VF103 with broken nmdreset, all RISC-V devices I tested stopped on `reset halt` without problem.","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"f93f97d6443726c3950c32d54d8649f19f440a2d","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"e72b67d8_b645b1cc","updated":"2025-01-27 04:13:25.000000000","message":"similar changes I have created another PR in the riscv fork (https://github.com/riscv-collab/riscv-openocd/pull/1214) since that fork has been diverged from this repo. If this change should come from that fork, please let me know, I\u0027ll discard the change here.\nThanks.","commit_id":"fee5bad0d72b07122bfcabd15f2780fd3dc5d91d"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"9b3b92f85f752858369ea5242aaefc854c418e81","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"8b7c4d26_b3125db3","in_reply_to":"85f419d8_69547c5b","updated":"2025-01-27 10:11:46.000000000","message":"This is the PR for riscv-colab. https://github.com/riscv-collab/riscv-openocd/pull/1214","commit_id":"fee5bad0d72b07122bfcabd15f2780fd3dc5d91d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"8cf218140e6cff8d7fa35d24b33dc49164bb7e45","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"be19f256_205b1c72","in_reply_to":"8b7c4d26_b3125db3","updated":"2025-01-27 10:54:32.000000000","message":"I meant that you should add URL https://review.openocd.org/c/openocd/+/8725\nto your PR https://github.com/riscv-collab/riscv-openocd/pull/1214\nto allow RISC-V guys to look here","commit_id":"fee5bad0d72b07122bfcabd15f2780fd3dc5d91d"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"fbf6e31da43237411b8226d8156c55aeba8a1f04","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"8b3eeeca_023b918f","in_reply_to":"93f86ad6_eabf607d","updated":"2025-01-27 14:50:32.000000000","message":"Done","commit_id":"fee5bad0d72b07122bfcabd15f2780fd3dc5d91d"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"f681909e95c47c1698291af691ba867862d4c2ef","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"93f86ad6_eabf607d","in_reply_to":"be19f256_205b1c72","updated":"2025-01-27 11:31:14.000000000","message":"consider it done! thanks","commit_id":"fee5bad0d72b07122bfcabd15f2780fd3dc5d91d"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"869782ccbaf578da492c9f9d9f021eeaf4ef387f","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"85f419d8_69547c5b","in_reply_to":"e72b67d8_b645b1cc","updated":"2025-01-27 07:57:47.000000000","message":"The way through riscv-colab would be preferred but you could wait quite long. The upstream RISC-V code haven\u0027t been updated for 2 or 3 years. Let\u0027s work on both.\nPlease add a pointer from riscv-colab PR to here.","commit_id":"fee5bad0d72b07122bfcabd15f2780fd3dc5d91d"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"3cac4960103ad92c1f0f930d41988329806787f2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"e4eac05f_86bf4efe","updated":"2025-01-27 12:28:13.000000000","message":"Thanks for reporting the issue!\nAlthough I would like to avoid merging this patch as it is.\nI have a couple concerns:\n\n1. I believe this is a workaround and it should be clearly stated.\n2. I would suggest first reviewing the patch to RISC-V fork -- IMHO, the reset procedure is much simpler there. Link: https://github.com/riscv-collab/riscv-openocd/pull/1214","commit_id":"a304f668cd193681730953ce78bdabb62250e2bc"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"4f8164c0fe1d8604d4f34e66f026155f938386cd","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"3602c2ae_633932a4","in_reply_to":"e4eac05f_86bf4efe","updated":"2025-02-05 01:10:45.000000000","message":"Okay, I\u0027ll exclude this commit from my patches. Thanks.","commit_id":"a304f668cd193681730953ce78bdabb62250e2bc"}],"src/target/riscv/riscv-013.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"869782ccbaf578da492c9f9d9f021eeaf4ef387f","unresolved":true,"context_lines":[{"line_number":2410,"context_line":"\t\t\tdmi_write(target, DM_DMCONTROL,"},{"line_number":2411,"context_line":"\t\t\t\t\tset_hartsel(control_haltreq, index));"},{"line_number":2412,"context_line":"\t\t} else {"},{"line_number":2413,"context_line":"\t\t\tindex \u003d r-\u003ecurrent_hartid;"},{"line_number":2414,"context_line":"\t\t}"},{"line_number":2415,"context_line":""},{"line_number":2416,"context_line":"\t\tLOG_DEBUG(\"Waiting for hart %d to come out of reset.\", index);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"877916dd_c0e76260","line":2413,"updated":"2025-01-27 07:57:47.000000000","message":"This part of original code looks pretty strange.\nIf the hart is not configured as SMP hwthread, then work just with current hart (and repeat the loop body sever time for the same hart)","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"3cac4960103ad92c1f0f930d41988329806787f2","unresolved":false,"context_lines":[{"line_number":2410,"context_line":"\t\t\tdmi_write(target, DM_DMCONTROL,"},{"line_number":2411,"context_line":"\t\t\t\t\tset_hartsel(control_haltreq, index));"},{"line_number":2412,"context_line":"\t\t} else {"},{"line_number":2413,"context_line":"\t\t\tindex \u003d r-\u003ecurrent_hartid;"},{"line_number":2414,"context_line":"\t\t}"},{"line_number":2415,"context_line":""},{"line_number":2416,"context_line":"\t\tLOG_DEBUG(\"Waiting for hart %d to come out of reset.\", index);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"98f977a7_ae944717","line":2413,"in_reply_to":"7c8b7c8e_c0310ac6","updated":"2025-01-27 12:28:13.000000000","message":"There is a commit in RISC-V fork that addresses this issue.\nhttps://github.com/riscv-collab/riscv-openocd/commit/1c168242e9f5993aec7024998529e2b2ed53098a\n(please note, the commit description mistakenly mentions `-rtos hwthread` instead of `-rtos riscv`).","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"97c656188cf9e63d4150b8105a2cbb4fad233a2b","unresolved":true,"context_lines":[{"line_number":2410,"context_line":"\t\t\tdmi_write(target, DM_DMCONTROL,"},{"line_number":2411,"context_line":"\t\t\t\t\tset_hartsel(control_haltreq, index));"},{"line_number":2412,"context_line":"\t\t} else {"},{"line_number":2413,"context_line":"\t\t\tindex \u003d r-\u003ecurrent_hartid;"},{"line_number":2414,"context_line":"\t\t}"},{"line_number":2415,"context_line":""},{"line_number":2416,"context_line":"\t\tLOG_DEBUG(\"Waiting for hart %d to come out of reset.\", index);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"fe250155_f669ba95","line":2413,"in_reply_to":"877916dd_c0e76260","updated":"2025-01-27 08:11:38.000000000","message":"\u003e (and repeat the loop body sever time for the same hart)\n\nOh no, in that case the loop is forced to end @ 2468","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"45af051d4d6339459accde3c2077c38209b7f28a","unresolved":false,"context_lines":[{"line_number":2410,"context_line":"\t\t\tdmi_write(target, DM_DMCONTROL,"},{"line_number":2411,"context_line":"\t\t\t\t\tset_hartsel(control_haltreq, index));"},{"line_number":2412,"context_line":"\t\t} else {"},{"line_number":2413,"context_line":"\t\t\tindex \u003d r-\u003ecurrent_hartid;"},{"line_number":2414,"context_line":"\t\t}"},{"line_number":2415,"context_line":""},{"line_number":2416,"context_line":"\t\tLOG_DEBUG(\"Waiting for hart %d to come out of reset.\", index);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"30c8beba_56611ab3","line":2413,"in_reply_to":"98f977a7_ae944717","updated":"2025-01-27 13:13:02.000000000","message":"Do you want me to bring that fix here too?","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"9b3b92f85f752858369ea5242aaefc854c418e81","unresolved":false,"context_lines":[{"line_number":2410,"context_line":"\t\t\tdmi_write(target, DM_DMCONTROL,"},{"line_number":2411,"context_line":"\t\t\t\t\tset_hartsel(control_haltreq, index));"},{"line_number":2412,"context_line":"\t\t} else {"},{"line_number":2413,"context_line":"\t\t\tindex \u003d r-\u003ecurrent_hartid;"},{"line_number":2414,"context_line":"\t\t}"},{"line_number":2415,"context_line":""},{"line_number":2416,"context_line":"\t\tLOG_DEBUG(\"Waiting for hart %d to come out of reset.\", index);"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"7c8b7c8e_c0310ac6","line":2413,"in_reply_to":"fe250155_f669ba95","updated":"2025-01-27 10:11:46.000000000","message":"should I do something about this?","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"869782ccbaf578da492c9f9d9f021eeaf4ef387f","unresolved":true,"context_lines":[{"line_number":2453,"context_line":""},{"line_number":2454,"context_line":"\t\tif (target-\u003ereset_halt) {"},{"line_number":2455,"context_line":"\t\t\t/* Wait for all harts to halt */"},{"line_number":2456,"context_line":"\t\t\twhile (1) {"},{"line_number":2457,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2458,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"},{"line_number":2459,"context_line":"\t\t\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHALTED))"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"4703ce9a_94d82595","line":2456,"updated":"2025-01-27 07:57:47.000000000","message":"Certainly not wait loop without any timeout!","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"9b3b92f85f752858369ea5242aaefc854c418e81","unresolved":false,"context_lines":[{"line_number":2453,"context_line":""},{"line_number":2454,"context_line":"\t\tif (target-\u003ereset_halt) {"},{"line_number":2455,"context_line":"\t\t\t/* Wait for all harts to halt */"},{"line_number":2456,"context_line":"\t\t\twhile (1) {"},{"line_number":2457,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2458,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"},{"line_number":2459,"context_line":"\t\t\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHALTED))"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"5b18c6cf_37ca2b35","line":2456,"in_reply_to":"4703ce9a_94d82595","updated":"2025-01-27 10:11:46.000000000","message":"sure, I\u0027ll revise it.","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"869782ccbaf578da492c9f9d9f021eeaf4ef387f","unresolved":true,"context_lines":[{"line_number":2456,"context_line":"\t\t\twhile (1) {"},{"line_number":2457,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2458,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"},{"line_number":2459,"context_line":"\t\t\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHALTED))"},{"line_number":2460,"context_line":"\t\t\t\t\tbreak;"},{"line_number":2461,"context_line":"\t\t\t}"},{"line_number":2462,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"fa28cd50_b0ca2061","line":2459,"updated":"2025-01-27 07:57:47.000000000","message":"Could we rely on ALLHALTED? E.g. in the case of hart not configured as SMP hwthread?","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"9b3b92f85f752858369ea5242aaefc854c418e81","unresolved":false,"context_lines":[{"line_number":2456,"context_line":"\t\t\twhile (1) {"},{"line_number":2457,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2458,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"},{"line_number":2459,"context_line":"\t\t\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHALTED))"},{"line_number":2460,"context_line":"\t\t\t\t\tbreak;"},{"line_number":2461,"context_line":"\t\t\t}"},{"line_number":2462,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"2692df67_485b759a","line":2459,"in_reply_to":"04bd8ffe_5364bacb","updated":"2025-01-27 10:11:46.000000000","message":"according to the spec, ALLHALTED covers the harts selected in DM.","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"8cf218140e6cff8d7fa35d24b33dc49164bb7e45","unresolved":false,"context_lines":[{"line_number":2456,"context_line":"\t\t\twhile (1) {"},{"line_number":2457,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2458,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"},{"line_number":2459,"context_line":"\t\t\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHALTED))"},{"line_number":2460,"context_line":"\t\t\t\t\tbreak;"},{"line_number":2461,"context_line":"\t\t\t}"},{"line_number":2462,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"94f92fd1_7786113e","line":2459,"in_reply_to":"2692df67_485b759a","updated":"2025-01-27 10:54:32.000000000","message":"Oh yes, I forgot that ALL is very misleading and just one hart is selected here.","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"97c656188cf9e63d4150b8105a2cbb4fad233a2b","unresolved":true,"context_lines":[{"line_number":2456,"context_line":"\t\t\twhile (1) {"},{"line_number":2457,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2458,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"},{"line_number":2459,"context_line":"\t\t\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHALTED))"},{"line_number":2460,"context_line":"\t\t\t\t\tbreak;"},{"line_number":2461,"context_line":"\t\t\t}"},{"line_number":2462,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"04bd8ffe_5364bacb","line":2459,"in_reply_to":"fa28cd50_b0ca2061","updated":"2025-01-27 08:11:38.000000000","message":"And for SMP target we are just in the process of setting HALTREQ - other harts may indicate different state than HALTED","commit_id":"ef806864a7030b2107cd7b0745e6ea5302bca4bf"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"8cf218140e6cff8d7fa35d24b33dc49164bb7e45","unresolved":true,"context_lines":[{"line_number":2453,"context_line":""},{"line_number":2454,"context_line":"\t\tif (target-\u003ereset_halt) {"},{"line_number":2455,"context_line":"\t\t\t/* Wait for all selected harts to halt */"},{"line_number":2456,"context_line":"\t\t\tstart \u003d time(NULL);"},{"line_number":2457,"context_line":"\t\t\tdo {"},{"line_number":2458,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2459,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"5b902aa0_b79bae65","line":2456,"range":{"start_line":2456,"start_character":3,"end_line":2456,"end_character":22},"updated":"2025-01-27 10:54:32.000000000","message":"No! This would break timeout in the outer loop.\nIt\u0027s OK to use the same `start` in the following test but do not set it again!","commit_id":"961c241f6dbd35f840302238eb16dcc25000540e"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"f681909e95c47c1698291af691ba867862d4c2ef","unresolved":true,"context_lines":[{"line_number":2453,"context_line":""},{"line_number":2454,"context_line":"\t\tif (target-\u003ereset_halt) {"},{"line_number":2455,"context_line":"\t\t\t/* Wait for all selected harts to halt */"},{"line_number":2456,"context_line":"\t\t\tstart \u003d time(NULL);"},{"line_number":2457,"context_line":"\t\t\tdo {"},{"line_number":2458,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2459,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"a7f0dd5c_22ddc878","line":2456,"range":{"start_line":2456,"start_character":3,"end_line":2456,"end_character":22},"in_reply_to":"5b902aa0_b79bae65","updated":"2025-01-27 11:31:14.000000000","message":"you\u0027re right, my bad. I\u0027ll fix it. thanks","commit_id":"961c241f6dbd35f840302238eb16dcc25000540e"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"fbf6e31da43237411b8226d8156c55aeba8a1f04","unresolved":false,"context_lines":[{"line_number":2453,"context_line":""},{"line_number":2454,"context_line":"\t\tif (target-\u003ereset_halt) {"},{"line_number":2455,"context_line":"\t\t\t/* Wait for all selected harts to halt */"},{"line_number":2456,"context_line":"\t\t\tstart \u003d time(NULL);"},{"line_number":2457,"context_line":"\t\t\tdo {"},{"line_number":2458,"context_line":"\t\t\t\tif (dmi_read(target, \u0026dmstatus, DM_DMSTATUS) !\u003d ERROR_OK)"},{"line_number":2459,"context_line":"\t\t\t\t\treturn ERROR_FAIL;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"b74cbdc9_ea788e15","line":2456,"range":{"start_line":2456,"start_character":3,"end_line":2456,"end_character":22},"in_reply_to":"a7f0dd5c_22ddc878","updated":"2025-01-27 14:50:32.000000000","message":"Done","commit_id":"961c241f6dbd35f840302238eb16dcc25000540e"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c777e18e157927ebc88e835ac5d878a66992b8bf","unresolved":true,"context_lines":[{"line_number":2441,"context_line":"\t\t\t\treturn ERROR_FAIL;"},{"line_number":2442,"context_line":"\t\t\t}"},{"line_number":2443,"context_line":"\t\t}"},{"line_number":2444,"context_line":"\t\ttarget-\u003estate \u003d TARGET_HALTED;"},{"line_number":2445,"context_line":""},{"line_number":2446,"context_line":"\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) {"},{"line_number":2447,"context_line":"\t\t\t/* Ack reset with DM_DMCONTROL_HALTREQ for those MCU whose dm needs"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"e0a58279_71993c4b","line":2444,"updated":"2025-01-27 13:43:16.000000000","message":"Yes, it looks like a bug in the original code. TARGET_HALTED is set regardless of `reset run` or `reset halt` is issued, regardless of hart state. risc-v colab has fixed it.\n\nOk, I will follow the conversation on risc-v colab and then we can backport the fix.","commit_id":"a304f668cd193681730953ce78bdabb62250e2bc"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"fbf6e31da43237411b8226d8156c55aeba8a1f04","unresolved":false,"context_lines":[{"line_number":2441,"context_line":"\t\t\t\treturn ERROR_FAIL;"},{"line_number":2442,"context_line":"\t\t\t}"},{"line_number":2443,"context_line":"\t\t}"},{"line_number":2444,"context_line":"\t\ttarget-\u003estate \u003d TARGET_HALTED;"},{"line_number":2445,"context_line":""},{"line_number":2446,"context_line":"\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) {"},{"line_number":2447,"context_line":"\t\t\t/* Ack reset with DM_DMCONTROL_HALTREQ for those MCU whose dm needs"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"aac1fe23_34b15eac","line":2444,"in_reply_to":"746abd11_fd9601d6","updated":"2025-01-27 14:50:32.000000000","message":"Done","commit_id":"a304f668cd193681730953ce78bdabb62250e2bc"},{"author":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"change_message_id":"0185ccbef08d4e091ec77a482c8eeef041aa58ac","unresolved":true,"context_lines":[{"line_number":2441,"context_line":"\t\t\t\treturn ERROR_FAIL;"},{"line_number":2442,"context_line":"\t\t\t}"},{"line_number":2443,"context_line":"\t\t}"},{"line_number":2444,"context_line":"\t\ttarget-\u003estate \u003d TARGET_HALTED;"},{"line_number":2445,"context_line":""},{"line_number":2446,"context_line":"\t\tif (get_field(dmstatus, DM_DMSTATUS_ALLHAVERESET)) {"},{"line_number":2447,"context_line":"\t\t\t/* Ack reset with DM_DMCONTROL_HALTREQ for those MCU whose dm needs"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"746abd11_fd9601d6","line":2444,"in_reply_to":"e0a58279_71993c4b","updated":"2025-01-27 13:50:21.000000000","message":"Great! Thank you, Tomas. I can update my patches once the issue\u0027s been fixed.","commit_id":"a304f668cd193681730953ce78bdabb62250e2bc"}]}