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\u003cjianghao.qian@hpmicro.com\u003e\n"}},"a304f668cd193681730953ce78bdabb62250e2bc":{"kind":"REWORK","_number":4,"created":"2025-01-27 11:33:52.000000000","uploader":{"_account_id":1001991,"name":"Ryan QIAN","email":"jianghao.qian@outlook.com","username":"jhqian"},"ref":"refs/changes/25/8725/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/8725/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/8725/4 \u0026\u0026 git checkout -b change-8725 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/8725/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/8725/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/8725/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/8725/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/8725/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"a510d51a78f14fbb8416037a587ce1bfc6016d24","subject":"bootstrap: Do not set up Git submodules by default"}],"author":{"name":"Ryan QIAN","email":"jianghao.qian@hpmicro.com","date":"2025-01-27 03:47:42.000000000","tz":480},"committer":{"name":"Ryan QIAN","email":"jianghao.qian@hpmicro.com","date":"2025-01-27 11:33:34.000000000","tz":480},"subject":"target/riscv: make sure target is halted when reset_halt is set","message":"target/riscv: make sure target is halted when reset_halt is set\n\n- some MCU will need certain period of time to be halted after ndmreset\n  is issued, so in deassert_reset, it needs to make sure MCU is halted\n  before clearing DM_DMCONTROL_HALTREQ.\n\nChange-Id: Id5171a46cc5d93b83f1915408c725cb9f4c28a4d\nSigned-off-by: Ryan QIAN \u003cjianghao.qian@hpmicro.com\u003e\n"}}},"requirements":[],"submit_records":[],"submit_requirements":[]}