)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"07dc207013b50ba5dd51dd20fee4cd0c56348b48","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"7dee73a7_73551837","updated":"2025-02-09 08:02:20.000000000","message":"CH347F v 4.41 SWD with STM32H7 target, no resistor in SWDIO circuit\n\n```\nWarn : If you get parity errors with CH347 vesion 4.41 insert a resistor to SWDIO connection\nInfo : clock speed 1000 kHz\nInfo : SWD DPIDR 0xff4c001b\nError: SWD Read data parity mismatch\n```\n\nNote all tests with whole patch series applied.","commit_id":"1f089fb9ca924b0ed3925d29349b31490faea0cc"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c1e804881d73e14167a3a192122596a95606dd71","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"1dbbf304_72e7961a","updated":"2025-02-09 07:50:07.000000000","message":"Measured transfer rates and stepping time with `load_image` of 64 KiB ramdisk file, `dump_image` of 64 KiB to /dev/null and `step` at RPi5 host.\n\nCH347T v 2.41 JTAG, target Kinetis K22, adapter speed 1875 kHz\n(note that the adapter despite requested speed drives some clocks pulses at freq  4.6 MHz and the shortest TCLK positive pulse is as short as 24 ns instead of 266 ns corresponding to the clock speed)\n```\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.850688s (75.233 KiB/s)\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.846626s (75.594 KiB/s)\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.847719s (75.497 KiB/s)\ncpufreq 2400000\ndumped 65536 bytes in 0.835417s (76.608 KiB/s)\ncpufreq 1600000\ndumped 65536 bytes in 0.851213s (75.187 KiB/s)\ncpufreq 1600000\ndumped 65536 bytes in 0.850905s (75.214 KiB/s)\ncpufreq 1600000\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x61000000 pc: 0x00002392 psp: 0x1fff0830\n13285 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x61000000 pc: 0x0000233c psp: 0x1fff0830\n12682 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x61000000 pc: 0x0000233e psp: 0x1fff0828\n12699 microseconds per iteration\ncpufreq 1600000\n```\n\nCH347T v 4.41 JTAG, target Kinetis K22, adapter speed 1875 kHz\n```\ncpufreq 1500000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.793566s (80.649 KiB/s)\ncpufreq 1500000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.787498s (81.270 KiB/s)\ncpufreq 1500000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.786558s (81.367 KiB/s)\ncpufreq 1500000\ndumped 65536 bytes in 0.781515s (81.892 KiB/s)\ncpufreq 1600000\ndumped 65536 bytes in 0.780878s (81.959 KiB/s)\ncpufreq 1600000\ndumped 65536 bytes in 0.780765s (81.971 KiB/s)\ncpufreq 1600000\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004e2 msp: 0x20010000\n12753 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004e4 msp: 0x20010000\n12001 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004e6 msp: 0x20010000\n11998 microseconds per iteration\ncpufreq 1600000\n```\ncompare with FT232H at the same requested speed\n```\ndownloaded 65536 bytes in 0.493123s (129.785 KiB/s)\ndumped 65536 bytes in 0.494058s (129.539 KiB/s)\n8829 microseconds per iteration\n```\n\nCH347T v 2.41 JTAG, target Kinetis K22, adapter speed 60000 kHz\n(the target wouldn\u0027t work if the speed were true 60 MHz)\n```\ncpufreq 1500000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.682376s (93.790 KiB/s)\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.666978s (95.955 KiB/s)\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.664251s (96.349 KiB/s)\ncpufreq 2400000\ndumped 65536 bytes in 0.660887s (96.840 KiB/s)\ncpufreq 2400000\ndumped 65536 bytes in 0.660206s (96.939 KiB/s)\ncpufreq 2400000\ndumped 65536 bytes in 0.660005s (96.969 KiB/s)\ncpufreq 2400000\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x61000000 pc: 0x00002378 psp: 0x1fff0828\n9995 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x61000000 pc: 0x0000237a psp: 0x1fff0828\n10072 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x61000000 pc: 0x0000237c psp: 0x1fff0828\n10078 microseconds per iteration\ncpufreq 2400000\n```\n\nCH347T v 4.41 JTAG, target Kinetis K22, adapter speed 30000 kHz\n(not surprisingly 60 MHz does not work with the target device)\n```\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.515594s (124.129 KiB/s)\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.519550s (123.184 KiB/s)\ncpufreq 1500000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.525967s (121.681 KiB/s)\ncpufreq 1500000\ndumped 65536 bytes in 0.518571s (123.416 KiB/s)\ncpufreq 1600000\ndumped 65536 bytes in 0.518204s (123.503 KiB/s)\ncpufreq 1600000\ndumped 65536 bytes in 0.518606s (123.408 KiB/s)\ncpufreq 1600000\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004e8 msp: 0x20010000\n8647 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004ea msp: 0x20010000\n8752 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004ee msp: 0x20010000\n8636 microseconds per iteration\ncpufreq 1600000\n```\ncompare with FT232H at the same requested speed\n```\ndownloaded 65536 bytes in 0.070775s (904.274 KiB/s)\ndumped 65536 bytes in 0.070441s (908.562 KiB/s)\n2579 microseconds per iteration\n```\nCH347T v 2.41 is almost **10 times slower**, v 4.41 is 7 times slower !!!\n\nCH347T v 4.41 SWD, target Kinetis K22, adapter speed 1000 kHz (maximum)\n```\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.965775s (66.268 KiB/s)\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.965727s (66.271 KiB/s)\ncpufreq 2400000\n65536 bytes written at address 0x20000000\ndownloaded 65536 bytes in 0.965730s (66.271 KiB/s)\ncpufreq 2400000\ndumped 65536 bytes in 0.957920s (66.811 KiB/s)\ncpufreq 1500000\ndumped 65536 bytes in 0.961098s (66.590 KiB/s)\ncpufreq 1500000\ndumped 65536 bytes in 0.961071s (66.592 KiB/s)\ncpufreq 1500000\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004e2 msp: 0x20010000\n14965 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004e4 msp: 0x20010000\n14515 microseconds per iteration\n[kx.cpu] halted due to single-step, current mode: Thread\nxPSR: 0x01000000 pc: 0x000004e6 msp: 0x20010000\n14592 microseconds per iteration\ncpufreq 1500000\n```\n\nFT232H in SWD mode is just slightly faster\n```\ndownloaded 65536 bytes in 0.923855s (69.275 KiB/s)\ndumped 65536 bytes in 0.920353s (69.539 KiB/s)\n13890 microseconds per iteration\n```\nUnlike CH347F much higher adapter speed can be selected with most of other adapters.","commit_id":"1f089fb9ca924b0ed3925d29349b31490faea0cc"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"622ef0a7086bb38022ef8672f1fced004298de5e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"02b507b1_35041304","in_reply_to":"067e6d94_ac34fcc1","updated":"2025-02-10 06:23:50.000000000","message":"Be aware that I measured just the **2.41** and **4.41** versions working in bitwise mode, not the old **2.21** which must be awful piece of crap.","commit_id":"1f089fb9ca924b0ed3925d29349b31490faea0cc"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"d1421ea449071e3ecb6b645c2e70582a4c90fbdc","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"067e6d94_ac34fcc1","in_reply_to":"1dbbf304_72e7961a","updated":"2025-02-10 05:17:50.000000000","message":"The reason why the speed is much slower compared to FT is that the speeds of CH347_CMD_JTAG_SIT_oP (D1) and CH347_CMD_JTAG_SIT_oP_RD (D2) are slower, actually around 1MHz, and this speed does not change with the speed setting.\n\nFor the version of CH347T: The old 2.21 version has a flaw and can only support the `use_bitwise_mode` mode, while other new versions can set `ch347.use_bitwise_mode \u003d true;`\nIn this way, CH347_CMD_JTAG_DATA_SHIFT(D3)/CH347_CMD_JTAG_DATA_SHIFT_RD(D4) will be able to be used, and the adapter speed setting will become effective,the speed will be faster.\n\nAll versions of CH347F can be set `ch347.use_bitwise_mode \u003d false;`","commit_id":"1f089fb9ca924b0ed3925d29349b31490faea0cc"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"2fd48b3a0d1e7db0e6ebe62171c998fabd2f3e9f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"b4b4cb6a_32301d83","in_reply_to":"7dee73a7_73551837","updated":"2025-02-09 11:27:48.000000000","message":"Damn, the parity error was copy\u0026pasta message logged in the case of a bad ack from SWD write.\n\nWith fixed log messages\n8747: drivers/ch347: fix SWD log messages | https://review.openocd.org/c/openocd/+/8747\nit looks like\n```\nWarn : If CH347 vesion 4.41 cannot connect or SWD fails often, insert a resistor to SWDIO circuit\nInfo : clock speed 1000 kHz\nError: Error connecting DP: cannot read IDR\n```\nand with -d3\n```\nDebug: 114 11 ch347.c:2327 ch347_swd_switch_seq(): JTAG-to-SWD\nInfo : 115 11 adi_v5_swd.c:385 swd_connect_single(): SWD DPIDR 0xff4c001b\nDebug: 116 11 ch347.c:2201 ch347_swd_run_queue_inner(): JUNK DP write reg 0 \u003d 0000001e\nDebug: 117 11 command.c:528 exec_command(): Command \u0027dap init\u0027 failed with error code -400\n```","commit_id":"1f089fb9ca924b0ed3925d29349b31490faea0cc"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"d1421ea449071e3ecb6b645c2e70582a4c90fbdc","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"dd73c32c_50324640","in_reply_to":"b4b4cb6a_32301d83","updated":"2025-02-10 05:17:50.000000000","message":"Usually this error caused by poor signal quality, can be minimized by shortening the connection line length and ensuring consistent voltage levels (3.3V).","commit_id":"1f089fb9ca924b0ed3925d29349b31490faea0cc"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"622ef0a7086bb38022ef8672f1fced004298de5e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"e5b6d94a_760ef0c7","in_reply_to":"dd73c32c_50324640","updated":"2025-02-10 06:23:50.000000000","message":"\u003e Usually this error caused by poor signal quality,\n\nPlease be aware that I regularly work with many types of SWD and some JTAG adapters so I know what wiring I need for what adapter speed. I very often use SWD at 10 or 20 MHz with better adapters than CH347. SWD at 1 MHz usually does not require anything special and almost any wiring up to 30 cm is sufficient. But not in CH347 case.\n\nThis problem is undoubtedly caused by an error in CH437T 4.41 SWD implementation. I discovered it looking at signals by 900 Msps logic analyzer and first described it here\nhttps://review.openocd.org/c/openocd/+/7937/comments/03e2b2d5_f5dbc6bc\n\nI extend the original description:\n\u003e When reading AP reg CH347 **erroneously drives SWDIO to H** for 392 ns after the last ACK bit and just before sampling of the first data bit.\n\nARM ADI v 5.2 spec defines this time slot as **turnaround** so the adapter have to switch the SWDIO output to Hi-Z ASAP and not to continue driving it to H!\nDuring this time the device under debug starts driving SWDIO in accordance to ADI specs and if drives to L (the first bit of read data), a **harmful current pulse (glitch) is generated** as two outputs (one driving H and the second driving L) are connected together.\nSome targets (almost all STM32 or some Kinetis Kx) get so upset by this glitch  that SWD protocol communication fails. Of course the behaviour is highly wiring dependent. A resistor inserted between the CH347 SWDIO pin and the device under debug SWDIO pin limits the current glitch and reliably mitigates the problem. \nSo maybe worse wiring (longer) could be better in this particular case.","commit_id":"1f089fb9ca924b0ed3925d29349b31490faea0cc"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"00949f19972dc35164d15fce81c10f7ce583d1b0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"05e66287_db24d149","updated":"2025-08-06 02:04:56.000000000","message":"look good","commit_id":"2dd1388eaf7a85f64a2c174d609e9775de705ae7"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"894a44c1aa5b1ebde2c218d2f67fbb6b1f9ce29a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"6dde202d_07e73129","updated":"2025-08-06 02:04:33.000000000","message":"look good","commit_id":"2dd1388eaf7a85f64a2c174d609e9775de705ae7"}],"src/jtag/drivers/ch347.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5556533d010aea0f467072d6b7913ea925c24bdb","unresolved":true,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"8ed85f50_99d2632b","line":1412,"updated":"2025-02-09 08:42:20.000000000","message":"ZhiYuanNJ,\ncould you please test CH347F versions, if these warnings are relevant as well or they should be limited to `chip_variant \u003d\u003d CH347T`\nThanks","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"fa53ad4a5be61812dccea01a67abdee91418b817","unresolved":false,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"d962d912_e9138d7d","line":1412,"in_reply_to":"11a42630_d99bbfee","updated":"2025-05-26 08:33:31.000000000","message":"Hi,Tomas\nAfter testing, found that CH347T older than 4.41 not support SWD, but CH347F, All versions support SWD mode. So the code can be written like this:\n\n```\n  if (swd_mode) {\n\t\tif (ch347.chip_variant \u003d\u003d CH347T \u0026\u0026 ch347_device_descriptor.bcdDevice \u003c 0x441)\n\t\t\tLOG_WARNING(\"CH347T version older than 4.41 probably does not support SWD transport\");\n\n\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)\n\t\t\tLOG_WARNING(\"If CH347 version 4.41 cannot connect or SWD fails often, insert a resistor to SWDIO circuit\");\n\n\t} else if (ch347.chip_variant \u003d\u003d CH347T \u0026\u0026 ch347_device_descriptor.bcdDevice \u003d\u003d 0x241) {\n\t\tLOG_WARNING(\"CH347 version 2.41 has very weird clock timing, may not work with a slower JTAG device\");\n\t}\n```","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"ef182432afb740f9fa7094e91fbafcf321de5dcc","unresolved":true,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"419f6718_6a0515a4","line":1412,"in_reply_to":"2839350e_b5fcf4ac","updated":"2025-08-05 02:33:01.000000000","message":"Warning message to add:\n\nLOG_WARNING(\"CH347T versions older than 5.44 or CH347F versions older than 1.1 do not support SWD clock settings - fixed at 1000 kHz!\");\n\nFor CH347T version 5.44 and above, and CH347F version 1.1 and above, there are three available clock settings: 5M, 1M, and 500K.\n```\n// clock_divisor: 0 --\u003e 5M\n// clock_divisor: 1 --\u003e 1M\n// clock_divisor: 2 --\u003e 500K\nuint8_t cmd_data[] \u003d {0x40, 0x42, 0x0f, 0x00, clock_divisor, 0x00, 0x00, 0x00 };\n```","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"622ef0a7086bb38022ef8672f1fced004298de5e","unresolved":false,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"c68aac92_a52a0db7","line":1412,"in_reply_to":"2edbaf12_6cbf2f7a","updated":"2025-02-10 06:23:50.000000000","message":"Please give details what versions CH347**F** chips report. Whether version numbering continues from CH347**T** or CH347**T** series starts from low version numbers.\nI also wonder if there is a version between 2.41 and 4.41 and if it implements SWD","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c335c972069c4767a2293df2ec6ad16f1fa507e4","unresolved":false,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"a557620a_919b1379","line":1412,"in_reply_to":"419f6718_6a0515a4","updated":"2025-08-06 05:16:56.000000000","message":"Actually 4.41 supports not only 1M SWD clock, also any integer divisor of 1M - low freq is limited by USB disconnect issue. Addressed in 8743: drivers/ch347: add SWD speed settings | https://review.openocd.org/c/openocd/+/8743","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"d1421ea449071e3ecb6b645c2e70582a4c90fbdc","unresolved":false,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"2edbaf12_6cbf2f7a","line":1412,"in_reply_to":"8ed85f50_99d2632b","updated":"2025-02-10 05:17:50.000000000","message":"I will test CH347F ASAP.","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"db4d49252a8796b6d20216b0752ee8aa033fedda","unresolved":false,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"11a42630_d99bbfee","line":1412,"in_reply_to":"c68aac92_a52a0db7","updated":"2025-02-10 13:31:54.000000000","message":"I\u0027ve heard there\u0027s a 3.41 version out there, but I\u0027ve never come across it.","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6f84af06b3e45dd475ffa0023200ea3f29037bb5","unresolved":false,"context_lines":[{"line_number":1409,"context_line":"\t}"},{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"2839350e_b5fcf4ac","line":1412,"in_reply_to":"d962d912_e9138d7d","updated":"2025-08-01 07:39:46.000000000","message":"Thanks ZhiYuanNJ. I put the part of your proposed change to this patch.\nI leave the warning about weird timing of version 2.41 valid for both variants until somebody shows the log analyser traces of CH347F v 2.41.","commit_id":"8bd4794e8b1ac41d1f6c77b271db9fabc3bb84be"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"91f131ac658788c40e29d41b83642438591acfd0","unresolved":true,"context_lines":[{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"},{"line_number":1416,"context_line":"\t\t\tLOG_WARNING(\"If CH347 vesion 4.41 cannot connect or SWD fails often, insert a resistor to SWDIO circuit\");"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"2916061c_47bf7c16","line":1413,"updated":"2025-03-16 22:26:30.000000000","message":"typo s/vesion/version/\nalso in next two LOG_WARNING()","commit_id":"44fcef05e385aa4e901efd8c9169d8b1f8390163"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"898ecfa013fdfa39521e67844e2b49cdc2f07c06","unresolved":false,"context_lines":[{"line_number":1410,"context_line":""},{"line_number":1411,"context_line":"\tif (swd_mode) {"},{"line_number":1412,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x441)"},{"line_number":1413,"context_line":"\t\t\tLOG_WARNING(\"CH347 vesion older than 4.41 probably does not support SWD transport\");"},{"line_number":1414,"context_line":""},{"line_number":1415,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003d\u003d 0x441)"},{"line_number":1416,"context_line":"\t\t\tLOG_WARNING(\"If CH347 vesion 4.41 cannot connect or SWD fails often, insert a resistor to SWDIO circuit\");"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"186ea4f8_eb0efc1e","line":1413,"in_reply_to":"2916061c_47bf7c16","updated":"2025-03-17 07:42:33.000000000","message":"Thanks","commit_id":"44fcef05e385aa4e901efd8c9169d8b1f8390163"},{"author":{"_account_id":1002199,"name":"ZhiYuanNJ","display_name":" ZhiYuanNJ","email":"871238103@qq.com","username":"ZhiYuanNJ"},"change_message_id":"e71544e6ac316aa7ab0f947cd7adb8dcb56e5cfa","unresolved":true,"context_lines":[{"line_number":1426,"context_line":"\t\t\tLOG_INFO(\"Please upgrade CH347T firmware to a production version \u003e\u003d 5.44\");"},{"line_number":1427,"context_line":""},{"line_number":1428,"context_line":"\t} else if (ch347.chip_variant \u003d\u003d CH347F) {"},{"line_number":1429,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x110)"},{"line_number":1430,"context_line":"\t\t\tLOG_INFO(\"Please upgrade CH347F firmware to a production version \u003e\u003d 1.1\");"},{"line_number":1431,"context_line":"\t}"},{"line_number":1432,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"5f50d08e_c4a9eea2","line":1429,"range":{"start_line":1429,"start_character":42,"end_line":1429,"end_character":47},"updated":"2025-08-06 03:44:53.000000000","message":"should be 0x101","commit_id":"2dd1388eaf7a85f64a2c174d609e9775de705ae7"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c335c972069c4767a2293df2ec6ad16f1fa507e4","unresolved":false,"context_lines":[{"line_number":1426,"context_line":"\t\t\tLOG_INFO(\"Please upgrade CH347T firmware to a production version \u003e\u003d 5.44\");"},{"line_number":1427,"context_line":""},{"line_number":1428,"context_line":"\t} else if (ch347.chip_variant \u003d\u003d CH347F) {"},{"line_number":1429,"context_line":"\t\tif (ch347_device_descriptor.bcdDevice \u003c 0x110)"},{"line_number":1430,"context_line":"\t\t\tLOG_INFO(\"Please upgrade CH347F firmware to a production version \u003e\u003d 1.1\");"},{"line_number":1431,"context_line":"\t}"},{"line_number":1432,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"62d00caa_e90adc65","line":1429,"range":{"start_line":1429,"start_character":42,"end_line":1429,"end_character":47},"in_reply_to":"5f50d08e_c4a9eea2","updated":"2025-08-06 05:16:56.000000000","message":"Done","commit_id":"2dd1388eaf7a85f64a2c174d609e9775de705ae7"}]}