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The trial and error\nmethod on SWD init USB packet discovered a byte parameter used\nas a divisor from 1 MHz maximal clock.\n\nPrevent setting too low clocks as it may trigger USB disconnects.\n\nCH347T/F versions 5.44/1.1 add 5 MHz SWD speed at divisor/index 0.\n\nCH347F related parts co-authored by ZhiYuanNJ \u003c871238103@qq.com\u003e\n\nSigned-off-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\nChange-Id: I5a990a43dcd7a6d73c71b795283a9fbdff489bf4\nReviewed-on: https://review.openocd.org/c/openocd/+/8743\nReviewed-by: ZhiYuanNJ \u003c871238103@qq.com\u003e\nTested-by: jenkins\n"}},"0d173f2b1e824e50fb3a7581a764b815c87be35a":{"kind":"REWORK","_number":4,"created":"2025-08-06 05:14:00.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/43/8743/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/43/8743/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/4 \u0026\u0026 git checkout -b change-8743 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/43/8743/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"af9e19189caedda3c4bd4a0a44be4ae04fbb78a5","subject":"drivers/ch347: detailed packet logging"}],"author":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2023-11-05 05:49:18.000000000","tz":60},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2025-08-06 05:12:07.000000000","tz":120},"subject":"drivers/ch347: add SWD speed settings","message":"drivers/ch347: add SWD speed settings\n\nSWD has completely different speed setting than JTAG.\nThere is no official chip documentation. The trial and error\nmethod on SWD init USB packet discovered a byte parameter used\nas a divisor from 1 MHz maximal clock.\n\nCH347T/F versions 5.44/1.1 add 5 MHz SWD speed at divisor/index 0.\n\nCH347F related parts co-authored by ZhiYuanNJ \u003c871238103@qq.com\u003e\n\nSigned-off-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\nChange-Id: I5a990a43dcd7a6d73c71b795283a9fbdff489bf4\n"}},"a827306c56ac0d7db1e0f981399b1093376c4f03":{"kind":"REWORK","_number":5,"created":"2025-08-06 09:22:58.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/43/8743/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/43/8743/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/5 \u0026\u0026 git checkout -b change-8743 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/43/8743/5","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/43/8743/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"af9e19189caedda3c4bd4a0a44be4ae04fbb78a5","subject":"drivers/ch347: detailed packet logging"}],"author":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2023-11-05 05:49:18.000000000","tz":60},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2025-08-06 09:17:30.000000000","tz":120},"subject":"drivers/ch347: add SWD speed settings","message":"drivers/ch347: add SWD speed settings\n\nSWD has completely different speed setting than JTAG.\nThere is no official chip documentation. The trial and error\nmethod on SWD init USB packet discovered a byte parameter used\nas a divisor from 1 MHz maximal clock.\n\nPrevent setting too low clocks as it may trigger USB disconnects.\n\nCH347T/F versions 5.44/1.1 add 5 MHz SWD speed at divisor/index 0.\n\nCH347F related parts co-authored by ZhiYuanNJ \u003c871238103@qq.com\u003e\n\nSigned-off-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\nChange-Id: I5a990a43dcd7a6d73c71b795283a9fbdff489bf4\n"}}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"CLOSED","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"OK","applied_by":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"}}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[]}},{"name":"Code-Review","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"],"failing_atoms":[]}}]}