)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"edc6f9aa22052a4559310863480d446bac3052c0","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":5,"id":"931621f6_803175a4","updated":"2025-06-21 08:25:25.000000000","message":"Please use a board configuration filename according to the style guide [1]. In this case the filename should be `pic64gx-curiosity-kit.cfg`\n\n[1] https://openocd.org/doc/doxygen/html/config_files.html","commit_id":"a65ca900cf21378e18bb5082d565ec272743fa53"},{"author":{"_account_id":1002366,"name":"Liam Fletcher","display_name":"Li-Fletch","email":"liam.fletcher@microchip.com","username":"Li-Fletch","status":"Microchip"},"change_message_id":"3965907ac6022e73ec7b3f0f3e85a43536f52c72","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"01eb2bf0_c428b6ae","in_reply_to":"931621f6_803175a4","updated":"2025-07-04 11:53:46.000000000","message":"Corrected","commit_id":"a65ca900cf21378e18bb5082d565ec272743fa53"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"0a3c5c23129e85e690cd717b02301685507701b1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"84cf5d0c_46478f55","updated":"2025-07-06 04:41:57.000000000","message":"Looks good, just one minor question.","commit_id":"66d32502bd87b76fc457acbcf010c3027a3e683d"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0e9ae059a7f7f6500287673777b23eeb7bf34cee","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"e89d0a70_12ef05d0","updated":"2025-07-05 21:04:19.000000000","message":"Thanks!\n\nQuestion for Liam: is there any microchip Risc-V device that uses a cJTAG (compact-JTAG) interface for debug?","commit_id":"66d32502bd87b76fc457acbcf010c3027a3e683d"},{"author":{"_account_id":1002366,"name":"Liam Fletcher","display_name":"Li-Fletch","email":"liam.fletcher@microchip.com","username":"Li-Fletch","status":"Microchip"},"change_message_id":"41422d34ebe4db82b43127f4e9bbf0d12baae50b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"1af0a845_6a39e9ed","in_reply_to":"e89d0a70_12ef05d0","updated":"2025-07-07 12:14:51.000000000","message":"No there is not.","commit_id":"66d32502bd87b76fc457acbcf010c3027a3e683d"}],"tcl/interface/pic64gx.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"9f13de8f0c231545f8a79d54ab9d2b097de7a29c","unresolved":true,"context_lines":[{"line_number":4,"context_line":"# MCHP Debug - PIC64GX"},{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"adapter speed 6000"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"adapter driver ftdi"},{"line_number":10,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"aa905ff3_260e310b","line":7,"updated":"2025-06-04 15:32:02.000000000","message":"The speed should not be part of the interface, but of the board or the target.","commit_id":"6b3a0c717bf3f39946a724675fa3b9f862baccf9"},{"author":{"_account_id":1002366,"name":"Liam Fletcher","display_name":"Li-Fletch","email":"liam.fletcher@microchip.com","username":"Li-Fletch","status":"Microchip"},"change_message_id":"3965907ac6022e73ec7b3f0f3e85a43536f52c72","unresolved":false,"context_lines":[{"line_number":4,"context_line":"# MCHP Debug - PIC64GX"},{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"adapter speed 6000"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"adapter driver ftdi"},{"line_number":10,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"253ae1e7_ef47cd5e","line":7,"in_reply_to":"aa905ff3_260e310b","updated":"2025-07-04 11:53:46.000000000","message":"Moved","commit_id":"6b3a0c717bf3f39946a724675fa3b9f862baccf9"}],"tcl/target/microchip/pic64gx.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"0a3c5c23129e85e690cd717b02301685507701b1","unresolved":true,"context_lines":[{"line_number":1,"context_line":"# SPDX-License-Identifier: GPL-2.0-or-later"},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Target: MPFS PolarFire SoC-series processors by Microchip Technologies"},{"line_number":4,"context_line":"#"},{"line_number":5,"context_line":"# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx"},{"line_number":6,"context_line":"#"}],"source_content_type":"text/x-ttcn-cfg","patch_set":7,"id":"de1b4b15_4fa43a17","line":3,"range":{"start_line":3,"start_character":10,"end_line":3,"end_character":46},"updated":"2025-07-06 04:41:57.000000000","message":"Is `PolarFire` name correct for a SoC without FPGA?\nThis comment looks like a copy pasta from `mpfs.cfg`","commit_id":"66d32502bd87b76fc457acbcf010c3027a3e683d"},{"author":{"_account_id":1002366,"name":"Liam Fletcher","display_name":"Li-Fletch","email":"liam.fletcher@microchip.com","username":"Li-Fletch","status":"Microchip"},"change_message_id":"41422d34ebe4db82b43127f4e9bbf0d12baae50b","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# SPDX-License-Identifier: GPL-2.0-or-later"},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Target: MPFS PolarFire SoC-series processors by Microchip Technologies"},{"line_number":4,"context_line":"#"},{"line_number":5,"context_line":"# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx"},{"line_number":6,"context_line":"#"}],"source_content_type":"text/x-ttcn-cfg","patch_set":7,"id":"cd21b5ab_871be169","line":3,"range":{"start_line":3,"start_character":10,"end_line":3,"end_character":46},"in_reply_to":"de1b4b15_4fa43a17","updated":"2025-07-07 12:14:51.000000000","message":"Well spotted thank you, changed.","commit_id":"66d32502bd87b76fc457acbcf010c3027a3e683d"}],"tcl/target/pic64gx.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"9f13de8f0c231545f8a79d54ab9d2b097de7a29c","unresolved":true,"context_lines":[{"line_number":1,"context_line":"# SPDX-License-Identifier: GPL-2.0-or-later"},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Target: MPFS PolarFire SoC-series processors by Microchip Technologies"},{"line_number":4,"context_line":"#"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"1012cee8_6c5b42c0","line":1,"updated":"2025-06-04 15:32:02.000000000","message":"I think this file can be merged within\nhttps://review.openocd.org/c/openocd/+/8877\nThe only difference is the table of expected ID, but from debug point of view the SoC\u0027s are similar.\nI don\u0027t see reason for having two files.\nAnd the file should be named `tcl/target/microchip/polarfire.tcl` or anything else you think better matches the list of supported SoC\u0027s\n\nIf you really want to have different file names for different SoC, then create a \u0027common\u0027 file and an extra file for each SoC that includes the \u0027common\u0027 one. See `esp_common.cfg` or `stm32x5x_common.cfg`.","commit_id":"6b3a0c717bf3f39946a724675fa3b9f862baccf9"},{"author":{"_account_id":1002366,"name":"Liam Fletcher","display_name":"Li-Fletch","email":"liam.fletcher@microchip.com","username":"Li-Fletch","status":"Microchip"},"change_message_id":"3965907ac6022e73ec7b3f0f3e85a43536f52c72","unresolved":true,"context_lines":[{"line_number":1,"context_line":"# SPDX-License-Identifier: GPL-2.0-or-later"},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Target: MPFS PolarFire SoC-series processors by Microchip Technologies"},{"line_number":4,"context_line":"#"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"89337284_1b359dd2","line":1,"in_reply_to":"1012cee8_6c5b42c0","updated":"2025-07-04 11:53:46.000000000","message":"Thank you, does the following resolve the issue: https://review.openocd.org/c/openocd/+/8877/comments/8ae1e561_77a8e853","commit_id":"6b3a0c717bf3f39946a724675fa3b9f862baccf9"},{"author":{"_account_id":1002366,"name":"Liam Fletcher","display_name":"Li-Fletch","email":"liam.fletcher@microchip.com","username":"Li-Fletch","status":"Microchip"},"change_message_id":"e8af4985e06ddd510a2b14eeb70cf48db0e9eea8","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# SPDX-License-Identifier: GPL-2.0-or-later"},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Target: MPFS PolarFire SoC-series processors by Microchip Technologies"},{"line_number":4,"context_line":"#"}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"8578e122_19ea1829","line":1,"in_reply_to":"89337284_1b359dd2","updated":"2025-07-21 08:29:08.000000000","message":"Ack","commit_id":"6b3a0c717bf3f39946a724675fa3b9f862baccf9"}]}