)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"da84d645741cd1adf0b87180a56766d321547eeb","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"armv8m: Add support for msplim/psplim for targets with no secext"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"When armv8m does not have security extension, it still has"},{"line_number":10,"context_line":"msplim/psplim regs implemented, which is described in Cortex-M33"},{"line_number":11,"context_line":"Devices Generic User Guide."},{"line_number":12,"context_line":"Document ID: 100235_0100_06_en, or at the link:"},{"line_number":13,"context_line":"https://developer.arm.com/documentation/100235/latest/"},{"line_number":14,"context_line":"Tested on cyw20829 along with gdb v14.2.1"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"38eb87ed_13210850","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":27},"updated":"2025-06-27 12:23:09.000000000","message":"Not completely true.\nARMv8-M Architecture Reference Manual says:\n```\nB3.21 Stack limit checks\n\nRPCRT A PE that does not implement the Main Extension, and does not implement the Security Extension does not\nimplement stack limit checking.\n```\n\nThe question is how to check the main extension presence (and whether such baseline ARMv8-M CPU is implemented at all)","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b9b2ff8cac7629a96500bc87babc0cdf68ad6faf","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"armv8m: Add support for msplim/psplim for targets with no secext"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"When armv8m does not have security extension, it still has"},{"line_number":10,"context_line":"msplim/psplim regs implemented, which is described in Cortex-M33"},{"line_number":11,"context_line":"Devices Generic User Guide."},{"line_number":12,"context_line":"Document ID: 100235_0100_06_en, or at the link:"},{"line_number":13,"context_line":"https://developer.arm.com/documentation/100235/latest/"},{"line_number":14,"context_line":"Tested on cyw20829 along with gdb v14.2.1"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"3bb49484_d06df586","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":27},"in_reply_to":"38eb87ed_13210850","updated":"2025-06-27 21:06:12.000000000","message":"`Main Extension` is detected from register\u0027s field `CPUID.Architecture`, chapter D1.2.16 \"CPUID, CPUID Base Register\":\n\u003e Architecture, bits [19:16]\n\u003e Architecture version. Defines the Architecture implemented by the PE.\n\u003e The possible values of this field are:\n\u003e 0b1100: Armv8-M architecture without Main Extension.\n\u003e 0b1111: Armv8-M architecture with Main Extension.\n\u003e All other values are reserved.\n\n`Security Extension` is detected from register\u0027s field `ID_PFR1.Security`, chapter D1.2.141 \"ID_PFR1, Processor Feature Register 1\":\n\u003e Security, bits [7:4]\n\u003e Security. Identifies whether the Security Extension is implemented.\n\u003e The possible values of this field are:\n\u003e 0b0000: Security Extension not implemented.\n\u003e 0b0001: Security Extension implemented.\n\u003e 0b0011: Security Extension implemented with state handling instructions\n\u003e  (VSCCLRM, CLRM, FPCXT access instructions and disabling SG Thread mode\n\u003e  re-entrancy).\n\u003e All other values are reserved.","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6cc293fbbb3021de9c23a737d06fdf8ce66696f0","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"armv8m: Add support for msplim/psplim for targets with no secext"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"When armv8m does not have security extension, it still has"},{"line_number":10,"context_line":"msplim/psplim regs implemented, which is described in Cortex-M33"},{"line_number":11,"context_line":"Devices Generic User Guide."},{"line_number":12,"context_line":"Document ID: 100235_0100_06_en, or at the link:"},{"line_number":13,"context_line":"https://developer.arm.com/documentation/100235/latest/"},{"line_number":14,"context_line":"Tested on cyw20829 along with gdb v14.2.1"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"7d4973f5_c6e3eba8","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":27},"in_reply_to":"3bb49484_d06df586","updated":"2025-06-28 05:21:32.000000000","message":"Antonio, thanks for pointing this (I hadn\u0027t enough time to dig in ARM ref).\n\nBTW: In 7402: cortex_m: handle armv8m cores without security extension | https://review.openocd.org/c/openocd/+/7402\nyour code of `cortex_m_has_tz()` reads `DAUTHSTATUS.SID` reg instead of `ID_PFR1.Security`. Any reason to prefer this way?","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ee77f83abe98024ae98da28ad385a0c647c1c251","unresolved":false,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"armv8m: Add support for msplim/psplim for targets with no secext"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"When armv8m does not have security extension, it still has"},{"line_number":10,"context_line":"msplim/psplim regs implemented, which is described in Cortex-M33"},{"line_number":11,"context_line":"Devices Generic User Guide."},{"line_number":12,"context_line":"Document ID: 100235_0100_06_en, or at the link:"},{"line_number":13,"context_line":"https://developer.arm.com/documentation/100235/latest/"},{"line_number":14,"context_line":"Tested on cyw20829 along with gdb v14.2.1"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"893c5017_3fa855aa","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":27},"in_reply_to":"6950224d_cbc83db4","updated":"2025-08-24 16:55:20.000000000","message":"Replying myself:\n`ID_PFR1` is present only if the Main Extension is implemented - so for baseline it\u0027s RES0. This explains why `cortex_m_has_tz()` tests `DAUTHSTATUS.SID` instead.","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"662fa926d44c249f230bdab73a7e3e809302f7c0","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"armv8m: Add support for msplim/psplim for targets with no secext"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"When armv8m does not have security extension, it still has"},{"line_number":10,"context_line":"msplim/psplim regs implemented, which is described in Cortex-M33"},{"line_number":11,"context_line":"Devices Generic User Guide."},{"line_number":12,"context_line":"Document ID: 100235_0100_06_en, or at the link:"},{"line_number":13,"context_line":"https://developer.arm.com/documentation/100235/latest/"},{"line_number":14,"context_line":"Tested on cyw20829 along with gdb v14.2.1"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"6950224d_cbc83db4","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":27},"in_reply_to":"7d4973f5_c6e3eba8","updated":"2025-07-27 09:51:55.000000000","message":"I completely forgot about that patch. Thanks for point to it.\nThere are two levels here:\n- Security extension is implemented in CPU by HW. This is to be detected through `ID_PFR1.Security`. Can be read only once at examine, as this cannot change.\n- Debugger is allowed to debug the CPU when CPU is in secure mode, e.g. R/W secure registers. This is detected through `DAUTHSTATUS.SID`. It should be read again at each halt, as the secure firmware is allowed to changed it through some SoC specific register.\n\nThe list of registers is sent to GDB only once, at GDB connection.\nSo here we have an issue in our OpenOCD model for the registers. We have the flag resister \"exist\" but we don\u0027t have a flag debugger can currently \"access\" it.\nI don\u0027t expect `DAUTHSTATUS.SID` to change often during a debug session, so we can stick at it to set \"exist\".\nNevertheless, we should improve OpenOCD to handle secure vs non-secure debug.","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"da84d645741cd1adf0b87180a56766d321547eeb","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"485e2363_5651a7c0","updated":"2025-06-27 12:23:09.000000000","message":"Thanks for the patch.\n\nAlthough the new code probably works, renaming of registers (defined in armv7m.h/armv7m.c) in cortex_m.c goes much different way than the existing code uses for register switching.\n\nWouldn\u0027t be better to define new ARMv8M specific `ARMV8M_MSPLIM` and `ARMV8M_PSPLIM` in armv7m.h, add their descriptions to `armv7m_regs` table\nand add appropriate mappings to `armv7m_map_id_to_regsel()`\n\nThen we should just mark as non-existent either `ARMV8M_MSPLIM`, `ARMV8M_PSPLIM` in the case of ARMv8M with secure ext, or the range from `ARMV8M_MSP_NS` to `ARMV8M_CONTROL_NS` in the case of ARMv8M with main ext/no sec ext and all of them in the case of ARMv7-M/ARMv6-M/(ARMv8-M baseline if detected) ?","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1002258,"name":"Ivan Kryvosheia","display_name":"kryvosheia","email":"kryvosheia.ivan@gmail.com","username":"kryvosheia","status":"SE at Infineon"},"change_message_id":"3ec68a1bb53c988fde02e5d39b66b2398a2823d4","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"c33a1685_c78f41d7","in_reply_to":"057be4e1_06a44aa8","updated":"2025-09-24 17:16:48.000000000","message":"I get CM5164LE00 (CM23, no security extension due to vendor docs) as a part of PIC32CM Lx Curiosity PRO board. As a result - the same as you have.\nopenOCD reads that the target has SecExt. And yes, seems that has to be in errata (I checked - that is missed there). So, seems that is an Atmel/Microchip problem based on our 2 boards.","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"eacf638e94a1710d4a5889d47bf8c4ca6469fb65","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"a5b3de4a_a97c05ad","in_reply_to":"297eab6c_7a513a03","updated":"2025-09-25 08:59:31.000000000","message":"Tomas, I have at least one CM-23 without security extension and CM-33 with security extension. Does this help you? I probably have some more but have to check - let me know if only CM-23 is suitable or all ARMv8-M based cores.","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1002410,"name":"Ivan","display_name":"kryvosheia","email":"Ivan.Kryvosheia@infineon.com","username":"kryvosheiaivan","status":"employer"},"change_message_id":"294304a1ed82be1c594bb4a9a5f5738a9ce8f55d","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"5d0b16ff_7f1c2980","in_reply_to":"485e2363_5651a7c0","updated":"2025-07-17 08:52:33.000000000","message":"Thanks for comment.\nFirst of all I toke into account all comments from you and Antonio and explored documentation on armv8m baseline+main extension with and without TZ.\nAs a result:\n- baseline, no tz \u003d\u003e no stack limit checks\n- baseline, tz \u003d\u003e2 stack limit registers in Secure state only (msplim_s,psplim_s)\n- main-ext, tz \u003d\u003e 4 stack limits\n- main-ext, no tz \u003d\u003e 2 stack limits\nand also I develop code accordingly.\n\nAs for tests:\n- I checked cm33,no tz case and make sure msplim real operation (checked that limit violation causes hard_fault)\n- also checked slightly that cm33,tz shows the same set of registers as before\n\nunfortunately, I does not have cm23 (baseline) to test it","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ee77f83abe98024ae98da28ad385a0c647c1c251","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"057be4e1_06a44aa8","in_reply_to":"5d0b16ff_7f1c2980","updated":"2025-08-24 16:55:20.000000000","message":"I dug an Atmel SAM L10 chip from my drawer. It\u0027s a Cortex-M23 and according to the data sheet it has **no security ext**. Unfortunately OpenOCD false detects it has TZ!\n\nSAM L10:\n```\nCPUID\n0xe000ed00: 411cd200\nID_PFR1\n0xe000ed44: 00000000\nDAUTHSTATUS\n0xe000efb8: 000000ff\n```\nNote ID_PFR1 is present only if the Main Extension is implemented - so for baseline it\u0027s RES0.\n\n`DAUTHSTATUS` value is most probably a silicon erratum, `SID` (and also `SNID`) bits should not read as \"Security Extension implemented and Secure (non)invasive debug allowed.\" when Security Extension is **not** implemented.\n\nTo make things even more complicated the core has accessible all four stack pointers `msp_ns`, `psp_ns`, `msp_s` and `psp_s` and two stack limits `msplim_s` and `psplim_s` (tested without this patch) so it looks like sec ext is implemented?! Atmel/Microchip produces also SAM L11 with TrustZone, so who knows how they select between the TZ and non TZ version.\n\nDoes anybody have a better Cortex-M23 device to test?\n\nFor comparison I checked two Cortex-M33 devices: STM32U5 with disabled TZ\n```\n\u003e flash info 0\ndevice idcode \u003d 0x20016482 (STM32U57/U58xx - Rev X : 0x2001)\nTZEN \u003d 0 : TrustZone disabled by option bytes\n...\nCPUID\n0xe000ed00: 410fd214\nID_PFR1\n0xe000ed44: 00000200\nDAUTHSTATUS\n0xe000efb8: 0000000f\n```\n\nand STM32L5 with enabled TZ\n```\n\u003e flash info 0\ndevice idcode \u003d 0x20016472 (STM32L55/L56xx - Rev Z : 0x2001)\nTZEN \u003d 1 : TrustZone enabled by option bytes\nRDP level 0 (0xAA)\n...\nCPUID\n0xe000ed00: 410fd212\nID_PFR1\n0xe000ed44: 00000210\nDAUTHSTATUS\n0xe000efb8: 000000ff\n```\n\nand the same device again with secure code debugging disabled:\n```\n\u003e flash info 0\ndevice idcode \u003d 0x20016472 (STM32L55/L56xx - Rev Z : 0x2001)\nTZEN \u003d 1 : TrustZone enabled by option bytes\nRDP level 0.5 (0x55)\n...\nCPUID\n0xe000ed00: 410fd212\nID_PFR1\n0xe000ed44: 00000210\nDAUTHSTATUS\n0xe000efb8: 000000af\n```\n\nEverything as expected.\nAlso note `ID_PFR1.Security` bits can change following TZEN setting, in case of STM32L5/U5 only during `option_load` (triggering reset), so Antonio\u0027s comment\n\u003e Security extension is implemented in CPU by HW. This is to be detected through `ID_PFR1.Security`. Can be read only once at examine, as this cannot change\n\nis not perfectly true.\n\nIvan,\nI think we should first get more ARMv8M baseline devices for testing.","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"430ed1effe5da7c86884f995e64f260f6b7507ce","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"7d58d572_fa04c89b","in_reply_to":"7672342e_a35cef5d","updated":"2025-09-26 07:06:51.000000000","message":"Done","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"199c783d7008cb99ce80ebbb8d3d8beea70f5c25","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"7672342e_a35cef5d","in_reply_to":"a5b3de4a_a97c05ad","updated":"2025-09-25 09:32:16.000000000","message":"\u003e Tomas, I have at least one CM-23 without security extension\n\nGreat, it is exactly what we need (hopefully it\u0027s not an Atmel SAM L10 or Microchip PIC32CM5164 we already tested and looks strange).\n\nCould you please read memory mapped word registers:\n```\nCPUID @ 0xe000ed00\nID_PFR1 @ 0xe000ed44\nDAUTHSTATUS @ 0xe000efb8\n```\nIf DAUTHSTATUS \u0026 0x30 is non zero, then OpenOCD will detect the security ext.\nThen please test the real existence of core stacks regs `msp_ns, psp_ns, msp_s, psp_s` and stack limit regs `msplim_s, psplim_s, msplim_ns, psplim_ns` simply\nby setting them to some different reasonable non-zero values (regs align to word address, the 2 lowest bits are always zero), issue `step` and check them if they keep the value.\n\nIf DAUTHSTATUS \u0026 0x30 is zero, then we would need the same test, but with slightly patched `src/target/cortex_m.c`: force `cortex_m_has_tz()` function to return always true.\n\nThanks a lot!","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"404dc3795c8fe5488d7574b375c1bb45294b476b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":3,"id":"297eab6c_7a513a03","in_reply_to":"c33a1685_c78f41d7","updated":"2025-09-24 18:13:37.000000000","message":"Hmm, this could be a successor silicon version of SAM L10/11 as Microchip acquired Atmel and continues in some products with changed naming. So the silicon bug could be easily the same.\n\nMarc, Andrzej, don\u0027t you have a Cortex-M23 device? E.g. GD32E230?\nCould you please make some tests for us?","commit_id":"2a6971f1e251a5d1aa1364a3713e072dffec0776"},{"author":{"_account_id":1002410,"name":"Ivan","display_name":"kryvosheia","email":"Ivan.Kryvosheia@infineon.com","username":"kryvosheiaivan","status":"employer"},"change_message_id":"294304a1ed82be1c594bb4a9a5f5738a9ce8f55d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"c2dc7322_46db4fdc","updated":"2025-07-17 08:52:33.000000000","message":"Thanks for comment.\nFirst of all I toke into account all comments from you and Antonio and explored documentation on armv8m baseline+main extension with and without TZ.\nAs a result:\n\n- baseline, no tz \u003d\u003e no stack limit checks\n- baseline, tz \u003d\u003e2 stack limit registers in Secure state only (msplim_s,psplim_s)\n- main-ext, tz \u003d\u003e 4 stack limits\n- main-ext, no tz \u003d\u003e 2 stack limits\nand also I develop code accordingly.\n\nAs for tests:\n- I checked cm33,no tz case and make sure msplim real operation (checked that limit violation causes hard_fault)\n- checked slightly that cm33,tz shows the same set of registers as before\n\nunfortunately, I does not have cm23 (baseline) to test it","commit_id":"fc8057a089b8d79594b40af7439efa09ca55dfe3"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"e35595b86c78d1a673d8c209db1f1c445241280d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"36b88108_d6576785","updated":"2025-09-25 10:30:12.000000000","message":"At debubg level 3 I see also:\n\ndevice id \u003d 0x19090410                                                                                                  flash size \u003d 64 KiB        \n\nThis microcontroller is probably ARMv8-M (Baseline).","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"db09103ae4e814e996556d03c4c6f9091677ac1f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"56dbdc14_dbae28c9","updated":"2025-09-25 21:45:13.000000000","message":"GD32E230C8T6 (cortex M23)\n\nTest with forced trustzone detection\n\n```\n\u003e flash info 0\ndevice id \u003d 0x19090410\nflash size \u003d 64 KiB\n\nCPUID\n\u003e mdw 0xe000ed00\n0xe000ed00: 411cd200\nID_PFR1\n\u003e mdw 0xe000ed44\n0xe000ed44: 00000000\nDAUTHSTATUS\n\u003e mdw 0xe000efb8\n0xe000efb8: 0000000f\n\n\u003e reg pc 0xeffffffe\npc (/32): 0xeffffffe\n\n\u003e reg msp_ns 0x20000050\nmsp_ns (/32): 0x20000050\n\u003e reg psp_ns 0x20000060\npsp_ns (/32): 0x20000060\n\u003e reg msp_s 0x20000070\nmsp_s (/32): 0x20000070\n\u003e reg psp_s 0x20000080\npsp_s (/32): 0x20000080\n\u003e reg msplim_s 0x20000010\nmsplim_s (/32): 0x20000010\n\u003e reg psplim_s 0x20000020\npsplim_s (/32): 0x20000020\n\u003e reg msplim_ns 0x20000030\nregister msplim_ns not found in current target\n\u003e reg psplim_ns 0x20000040\nregister psplim_ns not found in current target\n\n\u003e step\n[gd32e23x.cpu] halted due to single-step, current mode: Handler HardFault\nxPSR: 0x01000003 pc: 0xeffffffe msp: 0xffffffd8\nhalted: PC: 0xeffffffe\n\n\u003e reg\n\u003d\u003d\u003d\u003d\u003d arm v7m registers\n(23) control (/3): 0x00\n(26) msp_ns (/32): 0x00000000\n(27) psp_ns (/32): 0x00000000\n(28) msp_s (/32): 0x00000000\n(29) psp_s (/32): 0x00000000\n(30) msplim_s (/32): 0x00000000\n(31) psplim_s (/32): 0x00000000\n(35) primask_s (/1): 0x00\n```","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"188e97d6e97c81923a0ca7cb4b2db87d0698e02d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"d602b940_b132bc76","updated":"2025-09-25 10:09:32.000000000","message":"I have GD32E230C8T6 (cortex M23).\nPlease give me detailed telnet commands because I\u0027m getting only this:\n\n \u003e flash info 0\n#0 : stm32f1x at 0x08000000, size 0x00010000, buswidth 0, chipwidth 0\n#0: 0x00000000 (0x1000 4kB) not protected\n#1: 0x00001000 (0x1000 4kB) not protected\n...\n#15: 0x0000f000 (0x1000 4kB) not protected\nGD32E23x - Rev: unknown (0x1909)","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"430ed1effe5da7c86884f995e64f260f6b7507ce","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":7,"id":"a67846de_9089717a","updated":"2025-09-26 07:06:51.000000000","message":"Marc, Andrzej, thank you both!\nThe devices you tested behaves as we expect according to documentation for ARMv8M baseline without sec ext. I ask you for final testing of this patch as soon as it\u0027s ready.\n\nIvan,\nthe register logic now looks good with one exception - I spotted another difference baseline versus main ext:\n\u003e ARMv8-M architecture reference manual, B3.32\n\u003e A PE without the Main Extension implements PRIMASK, but does not implement FAULTMASK and BASEPRI\n\nAlthough not explicitly described, it\u0027s probably relevant also for _S and _NS banked versions on baseline with sec ext. FAULTMASK and BASEPRI does not keep non zero value on my SAM L10.\n\nThis is kind of out of topic, so we can address it in a separate patch. However you should address Marc\u0027s comment anyway - so if you don\u0027t mind please take a look on it.","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1001874,"name":"Andrzej Sierżęga","email":"asier70@gmail.com","username":"asier70"},"change_message_id":"c1ec19629895f9334a9f2689eeabe2681c17b469","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"d1ab1996_54d961a1","updated":"2025-09-25 13:09:27.000000000","message":"Sorry for partially sent information.\n\n0xe000ed00: 411cd200\n0xe000ed44: 00000000\n0xe000ee88: 00000000","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"5e924c953671bb451fee83b0fb2952867c86241d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"5a31d661_ca09d39c","in_reply_to":"2495963a_4eaf8105","updated":"2025-09-25 17:17:01.000000000","message":"Hi Tomas,\n\nI hope this helps you. The target is an Renesas RA0E1 (Cortex-M23) without security extension.\n\nRegister dump:\n\n```\n0xe000ed00: 411cd200 \n0xe000ed44: 00000000 \n0xe000ee88: 00000000 \n```\n\nWith `cortex_m_has_tz()` fixed to `true`:\n\n```\n\u003e reg msp_ns 0x20000050     \nmsp_ns (/32): 0x20000050  \n\u003e reg psp_ns 0x20000060     \npsp_ns (/32): 0x20000060\n\u003e reg msp_s 0x20000070\nmsp_s (/32): 0x20000070\n\u003e reg psp_s 0x20000080\npsp_s (/32): 0x20000080  \n\u003e reg msplim_s 0x20000010\nmsplim_s (/32): 0x20000010\n\u003e reg psplim_s 0x20000020\npsplim_s (/32): 0x20000020\n\u003e reg msplim_ns 0x20000030\nregister msplim_ns not found in current target\n\u003e reg psplim_ns 0x20000040\nregister psplim_ns not found in current target\n```\n\n```\n(23) control (/3): 0x00 \n(26) msp_ns (/32): 0x20000050 (dirty)\n(27) psp_ns (/32): 0x20000060 (dirty)\n(28) msp_s (/32): 0x20000070 (dirty)\n(29) psp_s (/32): 0x20000080 (dirty)\n(30) msplim_s (/32): 0x20000010 (dirty)\n(31) psplim_s (/32): 0x20000020 (dirty)\n(35) primask_s (/1): 0x00\n(36) basepri_s (/8): 0x00\n```\n\nAfter the step (executing `nop`):\n\n```\n(23) control (/3): 0x00\n(26) msp_ns (/32): 0x00000000\n(27) psp_ns (/32): 0x00000000\n(28) msp_s (/32): 0x00000000\n(29) psp_s (/32): 0x00000000\n(30) msplim_s (/32): 0x00000000\n(31) psplim_s (/32): 0x00000000\n(35) primask_s (/1): 0x00\n(36) basepri_s (/8): 0x00\n```","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1002410,"name":"Ivan","display_name":"kryvosheia","email":"Ivan.Kryvosheia@infineon.com","username":"kryvosheiaivan","status":"employer"},"change_message_id":"24c91dadf7a9456f5e6d369e3f23258a322d5703","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"11703710_be7d73d7","in_reply_to":"a67846de_9089717a","updated":"2025-10-20 11:59:31.000000000","message":"Tomas, Marc\u0027s comment resolved\nand yes, topic on FAULTMASK and BASEPRI should be covered in a separate patch,\nI believe","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"3ae9914567289d0a0e52f1db2ae29edd39ee2f45","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"2495963a_4eaf8105","in_reply_to":"d1ab1996_54d961a1","updated":"2025-09-25 15:37:09.000000000","message":"Perfect. Finally we have a device which has undoubtedly no trustzone.\n\nCould you please recompile OpenOCD with the following patch\n9148: target/cortex_m: force trustzone detection | https://review.openocd.org/c/openocd/+/9148\n\nand test presence of stack and stack limit registers. OpenOCD will show all security extension registers, however the not implemented ones will ignore writes and return zero value.\n\nOpen telnet interface and issue commands:\nKeep the core in lockout state to prevent processing instructions\n```\nreg pc 0xeffffffe\n```\nSet some values to stacks and stack limits\n```\nreg msp_ns 0x20000050\nreg psp_ns 0x20000060\nreg msp_s 0x20000070\nreg psp_s 0x20000080\nreg msplim_s 0x20000010\nreg psplim_s 0x20000020\nreg msplim_ns 0x20000030\nreg psplim_ns 0x20000040\n```\n\nDo a step. OpenOCD complains about lockup - it\u0027s no problem for this test as we want only re-read registers\n```\n\u003e step\nError: [saml1x.cpu] clearing lockup after double fault\n```\n\nRead back all registers\n```\nreg\n```\nand paste the result here.\nOn Atmel SAML10 the result reads:\n```\n...\n(23) control (/3): 0x00\n(24) msp_ns (/32): 0x20000050\n(25) psp_ns (/32): 0x20000060\n(26) msp_s (/32): 0x20000070\n(27) psp_s (/32): 0x20000080\n(28) msplim_s (/32): 0x20000010\n(29) psplim_s (/32): 0x20000020\n(30) msplim_ns (/32): 0x00000000\n(31) psplim_ns (/32): 0x00000000\n(33) primask_s (/1): 0x00\n...\n```\nAll but msplim_ns, psplim_ns are implemented. GD32E230 is expected to have two stack limits only.","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6d8fedab12ddd4a4928b2b25fecf74aa94220e08","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"d7f7456e_eee011c1","updated":"2025-10-20 13:20:45.000000000","message":"Thanks!","commit_id":"00ab6b606a030d9722ae449e024026c5d528968f"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"c8fc849fc35b6bacfe9542f2190bca86a3994ff8","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"3612d9f3_27dad2aa","in_reply_to":"8bc06579_a7d5724e","updated":"2025-11-02 13:46:21.000000000","message":"No written schedule.\nWe are going to merge riscv code, then we would enter in code freeze","commit_id":"00ab6b606a030d9722ae449e024026c5d528968f"},{"author":{"_account_id":1002410,"name":"Ivan","display_name":"kryvosheia","email":"Ivan.Kryvosheia@infineon.com","username":"kryvosheiaivan","status":"employer"},"change_message_id":"71c8a7222ca6098b318e7d57a12d91cab946dac0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"8bc06579_a7d5724e","in_reply_to":"d7f7456e_eee011c1","updated":"2025-10-27 11:19:01.000000000","message":"out of topic but when is openOCD release  is planned overall?\nmaybe this info is written somewhere?","commit_id":"00ab6b606a030d9722ae449e024026c5d528968f"}],"src/target/armv7m.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"662fa926d44c249f230bdab73a7e3e809302f7c0","unresolved":true,"context_lines":[{"line_number":148,"context_line":"\t{ ARMV8M_PSPLIM_S, \"psplim_s\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":149,"context_line":"\t{ ARMV8M_MSPLIM_NS, \"msplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":150,"context_line":"\t{ ARMV8M_PSPLIM_NS, \"psplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":151,"context_line":"\t{ ARMV8M_MSPLIM, \"msplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":152,"context_line":"\t{ ARMV8M_PSPLIM, \"psplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":153,"context_line":""},{"line_number":154,"context_line":"\t{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, \"pmsk_bpri_fltmsk_ctrl_s\", 32, REG_TYPE_INT, NULL, NULL, NULL, },"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"9fb66882_72732e5a","line":151,"updated":"2025-07-27 09:51:55.000000000","message":"The string you added \"arm-v8m.main-ext.no.secext\" is used for the target \"feature\", as described in\nhttps://sourceware.org/gdb/current/onlinedocs/gdb.html/Standard-Target-Features.html\nCurrent GDB does not handle natively \"msplim\" and \"psplim\", nor it handles the \"_s\" and \"_ns\" variants.\n\nI think we are already abusing of the feature \"org.gnu.gdb.arm.secext\" that GPB considers having only \"msp_ns\", \"psp_ns\", \"msp_s\", \"psp_s\". Anyway, I don\u0027t expect it\u0027s a big issue.\n\nBut \"arm-v8m.main-ext.no.secext\" is not following the naming convention.\n\nIn:\nsrc/target/armv8.c:1620\nsrc/target/armv4_5.c:543\nsrc/target/armv4_5.c:733\nwe used \"net.sourceforge.openocd.XXXX\"\nWe now have the domain \"openocd.org\", so we could probably change those to \"org.openocd.XXX\".\n\nIn mean time, if you cannot find a standard GDB feature for these registers, use something like \"net.sourceforge.openocd.arm-v8m.main-ext.no-secext\". I don\u0027t know if GDB has a max size for this field; please give it a try.\n\nTomas,\nyou have been working at restructuring the register description of OpenOCD. Any hint?","commit_id":"fc8057a089b8d79594b40af7439efa09ca55dfe3"},{"author":{"_account_id":1002410,"name":"Ivan","display_name":"kryvosheia","email":"Ivan.Kryvosheia@infineon.com","username":"kryvosheiaivan","status":"employer"},"change_message_id":"64d1ca6543a7bf512c8b134cc469ccb81e17111c","unresolved":false,"context_lines":[{"line_number":148,"context_line":"\t{ ARMV8M_PSPLIM_S, \"psplim_s\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":149,"context_line":"\t{ ARMV8M_MSPLIM_NS, \"msplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":150,"context_line":"\t{ ARMV8M_PSPLIM_NS, \"psplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":151,"context_line":"\t{ ARMV8M_MSPLIM, \"msplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":152,"context_line":"\t{ ARMV8M_PSPLIM, \"psplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":153,"context_line":""},{"line_number":154,"context_line":"\t{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, \"pmsk_bpri_fltmsk_ctrl_s\", 32, REG_TYPE_INT, NULL, NULL, NULL, },"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"4b52b3f9_9938ee91","line":151,"in_reply_to":"413e052f_a775d3b1","updated":"2025-08-18 12:26:27.000000000","message":"I moved msplim and psplim to \u0027org.gnu.gdb.arm.m-system\" as was proposed.","commit_id":"fc8057a089b8d79594b40af7439efa09ca55dfe3"},{"author":{"_account_id":1002410,"name":"Ivan","display_name":"kryvosheia","email":"Ivan.Kryvosheia@infineon.com","username":"kryvosheiaivan","status":"employer"},"change_message_id":"71c8a7222ca6098b318e7d57a12d91cab946dac0","unresolved":false,"context_lines":[{"line_number":148,"context_line":"\t{ ARMV8M_PSPLIM_S, \"psplim_s\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":149,"context_line":"\t{ ARMV8M_MSPLIM_NS, \"msplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":150,"context_line":"\t{ ARMV8M_PSPLIM_NS, \"psplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":151,"context_line":"\t{ ARMV8M_MSPLIM, \"msplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":152,"context_line":"\t{ ARMV8M_PSPLIM, \"psplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":153,"context_line":""},{"line_number":154,"context_line":"\t{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, \"pmsk_bpri_fltmsk_ctrl_s\", 32, REG_TYPE_INT, NULL, NULL, NULL, },"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"47765c24_5ce343e1","line":151,"in_reply_to":"4b52b3f9_9938ee91","updated":"2025-10-27 11:19:01.000000000","message":"Antonio, Can you also look at this patch?","commit_id":"fc8057a089b8d79594b40af7439efa09ca55dfe3"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a1134ef0fc2f451dc490dbfca1acb7926e3d7f4f","unresolved":true,"context_lines":[{"line_number":148,"context_line":"\t{ ARMV8M_PSPLIM_S, \"psplim_s\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":149,"context_line":"\t{ ARMV8M_MSPLIM_NS, \"msplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":150,"context_line":"\t{ ARMV8M_PSPLIM_NS, \"psplim_ns\", 32, REG_TYPE_DATA_PTR, \"stack\", \"org.gnu.gdb.arm.secext\", NULL, },"},{"line_number":151,"context_line":"\t{ ARMV8M_MSPLIM, \"msplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":152,"context_line":"\t{ ARMV8M_PSPLIM, \"psplim\", 32, REG_TYPE_DATA_PTR, \"stack\", \"arm-v8m.main-ext.no.secext\", NULL, },"},{"line_number":153,"context_line":""},{"line_number":154,"context_line":"\t{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, \"pmsk_bpri_fltmsk_ctrl_s\", 32, REG_TYPE_INT, NULL, NULL, NULL, },"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"413e052f_a775d3b1","line":151,"in_reply_to":"9fb66882_72732e5a","updated":"2025-07-30 19:20:48.000000000","message":"\u003e I think we are already abusing of the feature \"org.gnu.gdb.arm.secext\" that GPB considers having only \"msp_ns\", \"psp_ns\", \"msp_s\", \"psp_s\". Anyway, I don\u0027t expect it\u0027s a big issue.\n\nThe sourceware document also reads:\n\"Extra registers are allowed in this feature, but they will not affect GDB.\"\n\nSo it\u0027s IMO correct to use that feature for `msplim_s/ns` and `psplim_s/ns`\n\nSimilarly \"extra registers\" are allowed in `org.gnu.gdb.arm.m-system` feature.\nIs not this feature suitable also for `msplim` and `psplim`? I would vote for the simplest solution...","commit_id":"fc8057a089b8d79594b40af7439efa09ca55dfe3"}],"src/target/armv7m.h":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ee77f83abe98024ae98da28ad385a0c647c1c251","unresolved":true,"context_lines":[{"line_number":210,"context_line":"\tARMV7M_CORE_LAST_REG \u003d ARMV7M_XPSR,"},{"line_number":211,"context_line":"\tARMV7M_FPU_FIRST_REG \u003d ARMV7M_D0,"},{"line_number":212,"context_line":"\tARMV7M_FPU_LAST_REG \u003d ARMV8M_VPR,"},{"line_number":213,"context_line":"\tARMV8M_TZ_FIRST_REG \u003d ARMV8M_MSP_NS,"},{"line_number":214,"context_line":"\tARMV8M_TZ_LAST_REG \u003d ARMV8M_CONTROL_NS,"},{"line_number":215,"context_line":"};"},{"line_number":216,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"9e5f0fac_40fc822c","line":213,"range":{"start_line":213,"start_character":1,"end_line":213,"end_character":20},"updated":"2025-08-24 16:55:20.000000000","message":"`TZ` in the range name is quite misleading as the range now includes also MSPLIM and PSPLIM.\nWhat if we move them before ARMV8M_MSP_NS and exclude them from ARMV8M_TZ range? It would make the exist/not exist setting in examine more readable.","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1002258,"name":"Ivan Kryvosheia","display_name":"kryvosheia","email":"kryvosheia.ivan@gmail.com","username":"kryvosheia","status":"SE at Infineon"},"change_message_id":"3ec68a1bb53c988fde02e5d39b66b2398a2823d4","unresolved":false,"context_lines":[{"line_number":210,"context_line":"\tARMV7M_CORE_LAST_REG \u003d ARMV7M_XPSR,"},{"line_number":211,"context_line":"\tARMV7M_FPU_FIRST_REG \u003d ARMV7M_D0,"},{"line_number":212,"context_line":"\tARMV7M_FPU_LAST_REG \u003d ARMV8M_VPR,"},{"line_number":213,"context_line":"\tARMV8M_TZ_FIRST_REG \u003d ARMV8M_MSP_NS,"},{"line_number":214,"context_line":"\tARMV8M_TZ_LAST_REG \u003d ARMV8M_CONTROL_NS,"},{"line_number":215,"context_line":"};"},{"line_number":216,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"08e69ebc_e736b924","line":213,"range":{"start_line":213,"start_character":1,"end_line":213,"end_character":20},"in_reply_to":"9e5f0fac_40fc822c","updated":"2025-09-24 17:16:48.000000000","message":"it is Moved now","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"}],"src/target/cortex_m.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ee77f83abe98024ae98da28ad385a0c647c1c251","unresolved":true,"context_lines":[{"line_number":2568,"context_line":"\tuint32_t cpuid;"},{"line_number":2569,"context_line":""},{"line_number":2570,"context_line":"\t/* Read from Device Identification Registers */"},{"line_number":2571,"context_line":"\tint retval \u003d target_read_u32(target, CPUID, \u0026cpuid);"},{"line_number":2572,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":2573,"context_line":"\t\treturn retval;"},{"line_number":2574,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"3002fd2e_9073b7bc","line":2571,"range":{"start_line":2571,"start_character":14,"end_line":2571,"end_character":29},"updated":"2025-08-24 16:55:20.000000000","message":"CPUID register is read at the beginning of examine, don\u0027t waste time reading it again.","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1002258,"name":"Ivan Kryvosheia","display_name":"kryvosheia","email":"kryvosheia.ivan@gmail.com","username":"kryvosheia","status":"SE at Infineon"},"change_message_id":"3ec68a1bb53c988fde02e5d39b66b2398a2823d4","unresolved":false,"context_lines":[{"line_number":2568,"context_line":"\tuint32_t cpuid;"},{"line_number":2569,"context_line":""},{"line_number":2570,"context_line":"\t/* Read from Device Identification Registers */"},{"line_number":2571,"context_line":"\tint retval \u003d target_read_u32(target, CPUID, \u0026cpuid);"},{"line_number":2572,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":2573,"context_line":"\t\treturn retval;"},{"line_number":2574,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":6,"id":"d4253ea9_40796b94","line":2571,"range":{"start_line":2571,"start_character":14,"end_line":2571,"end_character":29},"in_reply_to":"3002fd2e_9073b7bc","updated":"2025-09-24 17:16:48.000000000","message":"done","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ee77f83abe98024ae98da28ad385a0c647c1c251","unresolved":true,"context_lines":[{"line_number":2853,"context_line":"\t\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2854,"context_line":"\t\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2855,"context_line":""},{"line_number":2856,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d true;"},{"line_number":2857,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM].exist \u003d true;"},{"line_number":2858,"context_line":"\t\t\t} else if (cm_has_tz \u0026\u0026 main_ext) {"},{"line_number":2859,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d false;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"6a1c79e2_ef07c19a","line":2856,"updated":"2025-08-24 16:55:20.000000000","message":"Very unreadable code - MSPLIM and PSPLIM are first marked as non existent and then set back existent.","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"430ed1effe5da7c86884f995e64f260f6b7507ce","unresolved":false,"context_lines":[{"line_number":2853,"context_line":"\t\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2854,"context_line":"\t\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2855,"context_line":""},{"line_number":2856,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d true;"},{"line_number":2857,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM].exist \u003d true;"},{"line_number":2858,"context_line":"\t\t\t} else if (cm_has_tz \u0026\u0026 main_ext) {"},{"line_number":2859,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d false;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"e13312ef_aecb3b3d","line":2856,"in_reply_to":"20e35764_ab011ec4","updated":"2025-09-26 07:06:51.000000000","message":"Done","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1002258,"name":"Ivan Kryvosheia","display_name":"kryvosheia","email":"kryvosheia.ivan@gmail.com","username":"kryvosheia","status":"SE at Infineon"},"change_message_id":"3ec68a1bb53c988fde02e5d39b66b2398a2823d4","unresolved":true,"context_lines":[{"line_number":2853,"context_line":"\t\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2854,"context_line":"\t\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2855,"context_line":""},{"line_number":2856,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d true;"},{"line_number":2857,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM].exist \u003d true;"},{"line_number":2858,"context_line":"\t\t\t} else if (cm_has_tz \u0026\u0026 main_ext) {"},{"line_number":2859,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d false;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"20e35764_ab011ec4","line":2856,"in_reply_to":"6a1c79e2_ef07c19a","updated":"2025-09-24 17:16:48.000000000","message":"branches was refactored","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ee77f83abe98024ae98da28ad385a0c647c1c251","unresolved":true,"context_lines":[{"line_number":2859,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d false;"},{"line_number":2860,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM].exist \u003d false;"},{"line_number":2861,"context_line":"\t\t\t} else if (cm_has_tz \u0026\u0026 baseline) {"},{"line_number":2862,"context_line":"\t\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2863,"context_line":"\t\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2864,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM_S].exist \u003d true;"},{"line_number":2865,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM_S].exist \u003d true;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"bee2faf9_dc231a2f","line":2862,"updated":"2025-08-24 16:55:20.000000000","message":"Has TZ and doesn\u0027t have TZ registers? Very strange!","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1002258,"name":"Ivan Kryvosheia","display_name":"kryvosheia","email":"kryvosheia.ivan@gmail.com","username":"kryvosheia","status":"SE at Infineon"},"change_message_id":"3ec68a1bb53c988fde02e5d39b66b2398a2823d4","unresolved":false,"context_lines":[{"line_number":2859,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM].exist \u003d false;"},{"line_number":2860,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM].exist \u003d false;"},{"line_number":2861,"context_line":"\t\t\t} else if (cm_has_tz \u0026\u0026 baseline) {"},{"line_number":2862,"context_line":"\t\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2863,"context_line":"\t\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2864,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_MSPLIM_S].exist \u003d true;"},{"line_number":2865,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM_S].exist \u003d true;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"13a34958_f8a81218","line":2862,"in_reply_to":"bee2faf9_dc231a2f","updated":"2025-09-24 17:16:48.000000000","message":"Ack","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"ee77f83abe98024ae98da28ad385a0c647c1c251","unresolved":true,"context_lines":[{"line_number":2865,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM_S].exist \u003d true;"},{"line_number":2866,"context_line":"\t\t\t}"},{"line_number":2867,"context_line":"\t\t} else {"},{"line_number":2868,"context_line":"\t\t\t/* ARCH_V7M or ARCH_V8M baseline without security extension */"},{"line_number":2869,"context_line":"\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2870,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2871,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"c369a311_01761cd6","line":2868,"range":{"start_line":2868,"start_character":18,"end_line":2868,"end_character":62},"updated":"2025-08-24 16:55:20.000000000","message":"ARCH_V8M does not go to this branch!","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"430ed1effe5da7c86884f995e64f260f6b7507ce","unresolved":false,"context_lines":[{"line_number":2865,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM_S].exist \u003d true;"},{"line_number":2866,"context_line":"\t\t\t}"},{"line_number":2867,"context_line":"\t\t} else {"},{"line_number":2868,"context_line":"\t\t\t/* ARCH_V7M or ARCH_V8M baseline without security extension */"},{"line_number":2869,"context_line":"\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2870,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2871,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"4867c4be_d3bc58b6","line":2868,"range":{"start_line":2868,"start_character":18,"end_line":2868,"end_character":62},"in_reply_to":"3337901b_597d08be","updated":"2025-09-26 07:06:51.000000000","message":"Done","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1002258,"name":"Ivan Kryvosheia","display_name":"kryvosheia","email":"kryvosheia.ivan@gmail.com","username":"kryvosheia","status":"SE at Infineon"},"change_message_id":"3ec68a1bb53c988fde02e5d39b66b2398a2823d4","unresolved":true,"context_lines":[{"line_number":2865,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[ARMV8M_PSPLIM_S].exist \u003d true;"},{"line_number":2866,"context_line":"\t\t\t}"},{"line_number":2867,"context_line":"\t\t} else {"},{"line_number":2868,"context_line":"\t\t\t/* ARCH_V7M or ARCH_V8M baseline without security extension */"},{"line_number":2869,"context_line":"\t\t\tfor (size_t idx \u003d ARMV8M_TZ_FIRST_REG; idx \u003c\u003d ARMV8M_TZ_LAST_REG; idx++)"},{"line_number":2870,"context_line":"\t\t\t\tarmv7m-\u003earm.core_cache-\u003ereg_list[idx].exist \u003d false;"},{"line_number":2871,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"3337901b_597d08be","line":2868,"range":{"start_line":2868,"start_character":18,"end_line":2868,"end_character":62},"in_reply_to":"c369a311_01761cd6","updated":"2025-09-24 17:16:48.000000000","message":"comment was changed","commit_id":"3965443e49a4965589c4857b3b8d4de3adefa137"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"eacf638e94a1710d4a5889d47bf8c4ca6469fb65","unresolved":true,"context_lines":[{"line_number":2573,"context_line":"\telse if (extension \u003d\u003d ARM_CPUID_NO_MAIN_EXTENSION)"},{"line_number":2574,"context_line":"\t\treturn false;"},{"line_number":2575,"context_line":""},{"line_number":2576,"context_line":"\tLOG_WARNING(\"Fail to detect target extension\");"},{"line_number":2577,"context_line":""},{"line_number":2578,"context_line":"\treturn false;"},{"line_number":2579,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"98cc74e0_f24544ef","line":2576,"updated":"2025-09-25 08:59:31.000000000","message":"Please do not introduce log output without target context -\u003e `LOG_TARGET_WARNING()`.","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"},{"author":{"_account_id":1002410,"name":"Ivan","display_name":"kryvosheia","email":"Ivan.Kryvosheia@infineon.com","username":"kryvosheiaivan","status":"employer"},"change_message_id":"24c91dadf7a9456f5e6d369e3f23258a322d5703","unresolved":false,"context_lines":[{"line_number":2573,"context_line":"\telse if (extension \u003d\u003d ARM_CPUID_NO_MAIN_EXTENSION)"},{"line_number":2574,"context_line":"\t\treturn false;"},{"line_number":2575,"context_line":""},{"line_number":2576,"context_line":"\tLOG_WARNING(\"Fail to detect target extension\");"},{"line_number":2577,"context_line":""},{"line_number":2578,"context_line":"\treturn false;"},{"line_number":2579,"context_line":"}"}],"source_content_type":"text/x-csrc","patch_set":7,"id":"5a248709_1f5cad3c","line":2576,"in_reply_to":"98cc74e0_f24544ef","updated":"2025-10-20 11:59:31.000000000","message":"done","commit_id":"77bf3810224194c268ceeb6847cd95532e8f6631"}]}