)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"06b7c3ee7d088c2845f3ee3642029bd348ab6910","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"9492b125_a5560bf1","updated":"2025-09-01 14:44:14.000000000","message":"I think this patch replaces https://review.openocd.org/c/openocd/+/8086\nShould the old one be abandoned with a message pointing to this new version?","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"19689d33fcd3e81913c95e1548f1c546ca176f9b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"b9da56c7_83872883","updated":"2025-10-08 15:44:43.000000000","message":"Looks good, just one potential issue common to both stm32h7x.cfg and stm32h7rsx.cfg.","commit_id":"c4c52b124333b75a63387391617d74fad188d583"}],"src/flash/nor/stm32h7x.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6fdbe0f42a1229401c1d3f9623e9fbf09ad089ed","unresolved":true,"context_lines":[{"line_number":382,"context_line":"\t\talive_sleep(1);"},{"line_number":383,"context_line":"\t}"},{"line_number":384,"context_line":""},{"line_number":385,"context_line":"\tif (device_id \u003d\u003d DEVID_STM32H7R_H7SXX) {"},{"line_number":386,"context_line":"\t\tflash_error \u003d FLASH_ERROR_H7RS;"},{"line_number":387,"context_line":"\t\tflash_clear_status_index \u003d STM32_FLASH_ICR_INDEX;"},{"line_number":388,"context_line":"\t} else {"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"b4b08510_23b02bad","line":385,"range":{"start_line":385,"start_character":5,"end_line":385,"end_character":39},"updated":"2025-08-30 16:02:26.000000000","message":"I\u0027m not fan of combining `stm32h7_parts` table with scattered `device_id` tests. Could you consider adding `flash_error` to `stm32h7_parts` table and use special CCR/ICR index - similarly as I recommended in\nhttps://review.openocd.org/c/openocd/+/8888/comment/a4783ed4_8f9fc590/","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"7b1b53f02da3f8e038007c7a216bb478a2d331b7","unresolved":false,"context_lines":[{"line_number":382,"context_line":"\t\talive_sleep(1);"},{"line_number":383,"context_line":"\t}"},{"line_number":384,"context_line":""},{"line_number":385,"context_line":"\tif (device_id \u003d\u003d DEVID_STM32H7R_H7SXX) {"},{"line_number":386,"context_line":"\t\tflash_error \u003d FLASH_ERROR_H7RS;"},{"line_number":387,"context_line":"\t\tflash_clear_status_index \u003d STM32_FLASH_ICR_INDEX;"},{"line_number":388,"context_line":"\t} else {"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"8ecf8a1e_487947b3","line":385,"range":{"start_line":385,"start_character":5,"end_line":385,"end_character":39},"in_reply_to":"b4b08510_23b02bad","updated":"2025-09-05 08:26:05.000000000","message":"Done","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6fdbe0f42a1229401c1d3f9623e9fbf09ad089ed","unresolved":true,"context_lines":[{"line_number":690,"context_line":"\t};"},{"line_number":691,"context_line":""},{"line_number":692,"context_line":"\tif (device_id \u003d\u003d DEVID_STM32H7R_H7SXX) {"},{"line_number":693,"context_line":"\t\tif (target_alloc_working_area(target, sizeof(stm32h7rs_flash_write_code),"},{"line_number":694,"context_line":"\t\t\t\u0026write_algorithm) !\u003d ERROR_OK) {"},{"line_number":695,"context_line":"\t\t\tLOG_WARNING(\"no working area available, can\u0027t do block memory writes\");"},{"line_number":696,"context_line":"\t\t\treturn ERROR_TARGET_RESOURCE_NOT_AVAILABLE;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"02acccee_6e238595","line":693,"range":{"start_line":693,"start_character":47,"end_line":693,"end_character":73},"updated":"2025-08-30 16:02:26.000000000","message":"Consider adding `write_code` and `write_code_size` to `stm32h7_parts` table","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"7b1b53f02da3f8e038007c7a216bb478a2d331b7","unresolved":false,"context_lines":[{"line_number":690,"context_line":"\t};"},{"line_number":691,"context_line":""},{"line_number":692,"context_line":"\tif (device_id \u003d\u003d DEVID_STM32H7R_H7SXX) {"},{"line_number":693,"context_line":"\t\tif (target_alloc_working_area(target, sizeof(stm32h7rs_flash_write_code),"},{"line_number":694,"context_line":"\t\t\t\u0026write_algorithm) !\u003d ERROR_OK) {"},{"line_number":695,"context_line":"\t\t\tLOG_WARNING(\"no working area available, can\u0027t do block memory writes\");"},{"line_number":696,"context_line":"\t\t\treturn ERROR_TARGET_RESOURCE_NOT_AVAILABLE;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"ec124ba5_42420185","line":693,"range":{"start_line":693,"start_character":47,"end_line":693,"end_character":73},"in_reply_to":"02acccee_6e238595","updated":"2025-09-05 08:26:05.000000000","message":"Done","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"}],"tcl/target/stm32h7rsx.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"d6a1fef832b7cdf55ad9c400d780f6a7bd14403c","unresolved":true,"context_lines":[{"line_number":71,"context_line":"# unavailable while SRST is asserted, and that is used to access the DBGMCU"},{"line_number":72,"context_line":"# component at 0x5C001000 in the examine-end event handler."},{"line_number":73,"context_line":"#"},{"line_number":74,"context_line":"reset_config srst_nogate"},{"line_number":75,"context_line":""},{"line_number":76,"context_line":"if {![using_hla]} {"},{"line_number":77,"context_line":"   # if srst is not fitted use SYSRESETREQ to"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"dd0ce9df_9c39d433","line":74,"range":{"start_line":74,"start_character":13,"end_line":74,"end_character":24},"updated":"2025-09-08 09:56:26.000000000","message":"If the previous comment is valid then `srst_nogate` mode should not be configured or `examine-end` event handler fails (as it runs under reset in this mode)!","commit_id":"18e3364f6d6712c57f3efe58ac783302e229eee6"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"980e476acd156b696f24d40014143724483743bb","unresolved":false,"context_lines":[{"line_number":71,"context_line":"# unavailable while SRST is asserted, and that is used to access the DBGMCU"},{"line_number":72,"context_line":"# component at 0x5C001000 in the examine-end event handler."},{"line_number":73,"context_line":"#"},{"line_number":74,"context_line":"reset_config srst_nogate"},{"line_number":75,"context_line":""},{"line_number":76,"context_line":"if {![using_hla]} {"},{"line_number":77,"context_line":"   # if srst is not fitted use SYSRESETREQ to"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"5a02924c_cf44f3c8","line":74,"range":{"start_line":74,"start_character":13,"end_line":74,"end_character":24},"in_reply_to":"dd0ce9df_9c39d433","updated":"2025-10-02 08:34:28.000000000","message":"Done","commit_id":"18e3364f6d6712c57f3efe58ac783302e229eee6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"d6a1fef832b7cdf55ad9c400d780f6a7bd14403c","unresolved":true,"context_lines":[{"line_number":130,"context_line":"\tset used_target [target current]"},{"line_number":131,"context_line":"\tset reg_addr [expr {0x5C001000 + $reg_offset}]"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"\tstm32h7x_mmw $used_target $reg_addr $setbits $clearbits"},{"line_number":134,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"0abf5b12_91426ec2","line":133,"range":{"start_line":133,"start_character":1,"end_line":133,"end_character":26},"updated":"2025-09-08 09:56:26.000000000","message":"`stm32h7x_dbgmcu_mmw` is now simple `mmw` on DBGMCU address and proc definitions `stm32h7x_get_chipname`, `stm32h7x_mrw` and `stm32h7x_mww` are useless.\nI would prefer direct use of\n```\nmmw 0x5C001004 ...\n```\nin `examine-end`.\nAlthough a stripped `stm32h7x_dbgmcu_mmw` is also acceptable.","commit_id":"18e3364f6d6712c57f3efe58ac783302e229eee6"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"980e476acd156b696f24d40014143724483743bb","unresolved":false,"context_lines":[{"line_number":130,"context_line":"\tset used_target [target current]"},{"line_number":131,"context_line":"\tset reg_addr [expr {0x5C001000 + $reg_offset}]"},{"line_number":132,"context_line":""},{"line_number":133,"context_line":"\tstm32h7x_mmw $used_target $reg_addr $setbits $clearbits"},{"line_number":134,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":5,"id":"b9532ea3_9e74a055","line":133,"range":{"start_line":133,"start_character":1,"end_line":133,"end_character":26},"in_reply_to":"0abf5b12_91426ec2","updated":"2025-10-02 08:34:28.000000000","message":"Done","commit_id":"18e3364f6d6712c57f3efe58ac783302e229eee6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"19689d33fcd3e81913c95e1548f1c546ca176f9b","unresolved":true,"context_lines":[{"line_number":97,"context_line":"\tmmw 0x5C001004 0x00100000 0"},{"line_number":98,"context_line":"}"},{"line_number":99,"context_line":""},{"line_number":100,"context_line":"$_CHIPNAME.cpu0 configure -event reset-init {"},{"line_number":101,"context_line":"\t# Clock after reset is HSI at 64 MHz, no need of PLL"},{"line_number":102,"context_line":"\tadapter speed 4000"},{"line_number":103,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"d355f8ee_d03757c8","line":103,"range":{"start_line":100,"start_character":0,"end_line":103,"end_character":1},"updated":"2025-10-08 15:44:43.000000000","message":"This config pattern is common to both stm32h7x.cfg and stm32h7rsx.cfg\n\nThe speed is set to 1800 kHz at OpenOCD initialisation - so the debugging normally uses this speed.\nBefore flash programming the speed rises to 4000 kHz and never returns back.\nSo any debugging after flash programming uses the higher speed.\n\nHonestly I see no reason why not set speed to 4000 kHz at OpenOCD init and drop `reset-init` event. Is there anything I missed?\n\nMoreover the speed setting in an event has some drawbacks:\n- if an adapter without speed setting support is used, the event fails\n- if user sets desired speed from command line, the event might be an unwanted surprise for him.\n\nSee also 9128: tcl/target/stm32g4x: drop useless reset-start event | https://review.openocd.org/c/openocd/+/9128\n\nCould you consider dropping `reset-init` event and eventually changing the default speed in both configs?","commit_id":"c4c52b124333b75a63387391617d74fad188d583"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"30b63f51e31e556947d7ff50a8ad37906600e285","unresolved":false,"context_lines":[{"line_number":97,"context_line":"\tmmw 0x5C001004 0x00100000 0"},{"line_number":98,"context_line":"}"},{"line_number":99,"context_line":""},{"line_number":100,"context_line":"$_CHIPNAME.cpu0 configure -event reset-init {"},{"line_number":101,"context_line":"\t# Clock after reset is HSI at 64 MHz, no need of PLL"},{"line_number":102,"context_line":"\tadapter speed 4000"},{"line_number":103,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":6,"id":"16152a6d_1a55c472","line":103,"range":{"start_line":100,"start_character":0,"end_line":103,"end_character":1},"in_reply_to":"d355f8ee_d03757c8","updated":"2025-10-30 09:57:34.000000000","message":"Done","commit_id":"c4c52b124333b75a63387391617d74fad188d583"}],"tcl/target/stm32h7rx.cfg":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6fdbe0f42a1229401c1d3f9623e9fbf09ad089ed","unresolved":true,"context_lines":[{"line_number":14,"context_line":"   set _CHIPNAME stm32h7x"},{"line_number":15,"context_line":"}"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# Issue a warning when hla is used, and fallback to single core configuration"},{"line_number":18,"context_line":"if { [using_hla] } {"},{"line_number":19,"context_line":"\techo \"Error : hla does not support multicore debugging\""},{"line_number":20,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"71f471ad_8b201af9","line":17,"range":{"start_line":17,"start_character":34,"end_line":17,"end_character":77},"updated":"2025-08-30 16:02:26.000000000","message":"copypasta","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"7b1b53f02da3f8e038007c7a216bb478a2d331b7","unresolved":false,"context_lines":[{"line_number":14,"context_line":"   set _CHIPNAME stm32h7x"},{"line_number":15,"context_line":"}"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"# Issue a warning when hla is used, and fallback to single core configuration"},{"line_number":18,"context_line":"if { [using_hla] } {"},{"line_number":19,"context_line":"\techo \"Error : hla does not support multicore debugging\""},{"line_number":20,"context_line":"}"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"27998449_bdf8673a","line":17,"range":{"start_line":17,"start_character":34,"end_line":17,"end_character":77},"in_reply_to":"71f471ad_8b201af9","updated":"2025-09-05 08:26:05.000000000","message":"Done","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6fdbe0f42a1229401c1d3f9623e9fbf09ad089ed","unresolved":true,"context_lines":[{"line_number":130,"context_line":"}"},{"line_number":131,"context_line":""},{"line_number":132,"context_line":"# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base"},{"line_number":133,"context_line":"# this procedure will use the mem_ap on AP2 whenever possible"},{"line_number":134,"context_line":"proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {"},{"line_number":135,"context_line":"\tset _CHIPNAME [stm32h7x_get_chipname]"},{"line_number":136,"context_line":"\tset used_target [target current]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"49a86e1e_153492c7","line":133,"range":{"start_line":133,"start_character":2,"end_line":133,"end_character":61},"updated":"2025-08-30 16:02:26.000000000","message":"??? Seems it will never use AP2 and there is no point in defining `stm32h7x_dbgmcu_mmw`\nBTW, why was access though AP2 removed?","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"21a3d6ab4f8817118879852f56c0d80a258f81a5","unresolved":false,"context_lines":[{"line_number":130,"context_line":"}"},{"line_number":131,"context_line":""},{"line_number":132,"context_line":"# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base"},{"line_number":133,"context_line":"# this procedure will use the mem_ap on AP2 whenever possible"},{"line_number":134,"context_line":"proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {"},{"line_number":135,"context_line":"\tset _CHIPNAME [stm32h7x_get_chipname]"},{"line_number":136,"context_line":"\tset used_target [target current]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"35e98454_fe732383","line":133,"range":{"start_line":133,"start_character":2,"end_line":133,"end_character":61},"in_reply_to":"2e2c2dd1_a1a50420","updated":"2025-10-08 15:48:54.000000000","message":"Done","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"7b1b53f02da3f8e038007c7a216bb478a2d331b7","unresolved":true,"context_lines":[{"line_number":130,"context_line":"}"},{"line_number":131,"context_line":""},{"line_number":132,"context_line":"# mmw for dbgmcu component registers, it accepts the register offset from dbgmcu base"},{"line_number":133,"context_line":"# this procedure will use the mem_ap on AP2 whenever possible"},{"line_number":134,"context_line":"proc stm32h7x_dbgmcu_mmw {reg_offset setbits clearbits} {"},{"line_number":135,"context_line":"\tset _CHIPNAME [stm32h7x_get_chipname]"},{"line_number":136,"context_line":"\tset used_target [target current]"}],"source_content_type":"text/x-ttcn-cfg","patch_set":4,"id":"2e2c2dd1_a1a50420","line":133,"range":{"start_line":133,"start_character":2,"end_line":133,"end_character":61},"in_reply_to":"49a86e1e_153492c7","updated":"2025-09-05 08:26:05.000000000","message":"H7RS does not have AP2 like H7","commit_id":"cbcd311ff5f2d66d17d3c8861eb11d0f05484976"}]}