)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"7acab959_767d2156","updated":"2025-05-04 20:34:48.000000000","message":"Thanks for this patch, really welcome for upstreaming the riscv fork.\n\nThe ACI complains that this patch does not passes the test with checkpatch.\n\nTo avoid further divergence, it would be better to have all the checkpatch issues at first fixed in the riscv fork, then re-generate the upstream request. \n\nI have also analyzed the base64 helpers, where origin and license were not clear plus other minor issues with checkpatch.\nFor these two file plus the Makefile.am associated, I would prefer getting them in a separate patch.\n\nThen, please great attention to my comment to `src/target/riscv/debug_defines.h`, valid for `debug_defines.c` too","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"aeabf98c2c4aa6e744ebb523bb0481bd10448de9","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"3577a71f_1e11fcf5","in_reply_to":"18cf8937_7f2e40d4","updated":"2025-05-05 01:22:09.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"b4e1ec60f1399f30a81e50206a11eb70d50918b7","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"18cf8937_7f2e40d4","in_reply_to":"7acab959_767d2156","updated":"2025-05-04 22:06:48.000000000","message":"I\u0027ve fixed the checkpatch complaints in revision 2 (minus a few that don\u0027t go well with the particular code in question -- can\u0027t really use do-while around a macro that does \"case name: ....\"\nWill add Checkpatch-ignore: for those in the next revision.","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"b4e1ec60f1399f30a81e50206a11eb70d50918b7","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"9096ea55_ff97b73a","updated":"2025-05-04 22:06:48.000000000","message":"Hi,\nalready fixed most checkpatch complaints in rev. 2, will address the remaining bits now.","commit_id":"f0bb61cf5f2a54ccc7920b8078ee359907bbed25"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"d19662c29e6688249a2ed66c377bc0e6be60ae7d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"2d653e7e_b3fd7378","updated":"2025-05-05 00:26:59.000000000","message":"The build failure jenkins complains about is caused by a false warning from an old version of gcc -- both current clang and current gcc  no longer warn about this.\n\n                if (opcode \u003d\u003d MATCH_SB || opcode \u003d\u003d (MATCH_FSH \u0026 ~INSN_FIELD_FUNCT3)) {\n                        offset \u003d get_field32(instruction, INSN_FIELD_IMM12LO) |\n                                  (get_field32(instruction, INSN_FIELD_IMM12HI) \u003c\u003c 5);\n                } else if (opcode \u003d\u003d MATCH_LB ||\n                                   opcode \u003d\u003d (MATCH_FLH \u0026 ~INSN_FIELD_FUNCT3)) {\n                        offset \u003d get_field32(instruction, INSN_FIELD_IMM12);\n                } else {\n                        assert(false);\n                }\n                /* sign extend 12-bit imm to 16-bits */\n                if (offset \u0026 (1 \u003c\u003c 11))\n                        offset |\u003d 0xf000;\n\nThe old compiler thinks \"offset |\u003d 0xf000\" could be an uninitialized use because it doesn\u0027t realize what assert(false) is.\nBut other than wasting a little space, explicitly initializing the variable at declaration time won\u0027t hurt, and it\u0027ll fix this","commit_id":"e0126171a7599ce891ed1e847f05b5624493a09c"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"f8cb084c745548308d66cce5a4f9e1874a600f49","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"538fe9c9_624db61f","updated":"2025-05-07 13:49:57.000000000","message":"Thank you for taking the time to clean up the mess that is the discrepencies between RISC-V OpenOCD fork and the mainline!\n\nHowever, I\u0027m a bit concerned with the approach you have selected.\n\nThere are significant changes in the RISC-V OpenOCD fork outside of `target/riscv`.\nNamely (from `diff` between current master and merge from master to `riscv-openocd/riscv`[1]):\n* `server/gdb_server.c` -- handling of unavailable targets\n* `target/breakpoints.c` in `breakpoint_add/remove()` etc.\n* `target/target.c` in `target_examine()`\n* `src/rtos`  -- there are many changes. The majority is related to FreeRTOS, however there is also changes to `rtos/rtos.c` itself.\nYou can see a discussion of these differences in the relevant issue [2]. It\u0027s outdated, but still helpful IMHO.\n\nConsidering that this version of `target/riscv` has never been tested with the version of the code outside of `target/riscv` from the mainline, I\u0027d suggest an alternative approach:\n\n1. Distinguish changes to the \"core\" code (e.g. `target_examine()`) from additional RISC-V independent features (e.g. the change to FreeRTOS support).\n2. Create a branch in RISC-V fork that drops these features -- this will allow us to establish the expectation on the passrate after alignment between the fork and mainline.\n3. Align the code outside `target/riscv`. AFAIU this would be a diff of about a 1000 lines that can be split into multiple well-formed commits to either fork or mainline.\n4. Update the code inside `target/riscv`.\n\nThe current commit is too large to grasp (even excluding auto-generated stuff). Considering the limited testing available, one hardly can be certain that the resulting code would work properly with the current approach.\n\n[1] https://github.com/riscv-collab/riscv-openocd/pull/1247\n[2] https://github.com/riscv-collab/riscv-openocd/issues/979","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"aeabf98c2c4aa6e744ebb523bb0481bd10448de9","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"0357bdef_b7113e78","updated":"2025-05-05 01:22:09.000000000","message":"The current patchset should address everything -- will try to get the changes it needed to make checkpatch happy merged into the fork as well to unify codebases.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"ae624ff6cd120e154bec5a001bb0fde0c71b4473","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"149b1192_377b4c66","in_reply_to":"0a08fb13_7ed40fbe","updated":"2025-08-06 07:47:24.000000000","message":"Took a look, besides the things already mentioned by Evgeniy there are some things I noticed:\n\n- `nvp_target_state` is missing the `unavailable` option - can be added to this sync\n- Few logging changes in `target.c` - this can be done later\n- tcl scripts for RISC-V boards/targers are missing - this could be adder to this sync\n\nOur internal test suite passes, trough we don\u0027t test SMP targets. For comparison, the version without this sync fails on some breakpoint tests. This is thanks to mcontrol6 trigger support.\n\nCurrently, I am trying to run the testsuite from from https://github.com/riscv-software-src/riscv-tests So far there is trouble with tests entering infinite loops hanging the entire test suite. I will post an update later.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002161,"name":"Anatoly P","email":"kupokupokupopo@gmail.com","username":"ecco_the_dolphin"},"change_message_id":"2ce037d46c512450bf91db631e552cd40c60863b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"b0dc6854_820cebb4","in_reply_to":"0d9ffbc1_9c327a95","updated":"2025-10-21 17:14:05.000000000","message":"Hi Tomas and Antonio!\n\nToday I\u0027ve managed to find the time to do some additional testing. As far as riscv-openocd goes (from riscv-collab) I used https://github.com/riscv-collab/riscv-openocd/commit/6f84e90d5cc0e98f895ea0fa31212326b50ab769 as a baseline to compare results.\n\n---\n\nAs for OpenOCD source code I used the following:\n\ntook current TOT (which was 88b9bd3 : target: cortex-m: fix support for armv8m caches ). Then I applied the following patches on top of it:\n- https://review.openocd.org/c/openocd/+/8893 (this one)\n- https://review.openocd.org/c/openocd/+/8921 (target/breakpoints: better wording for error reason)\n- https://review.openocd.org/c/openocd/+/8914 (server/gdb_server: Handle events if first target is unavailable)\n- https://review.openocd.org/c/openocd/+/8915 (server/gdb_server: Fake resuming unavailable targets.)\n- https://review.openocd.org/c/openocd/+/9138 (gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not implemented)\n- https://review.openocd.org/c/openocd/+/9127 (target, flash: utility for riscv repeat_read command)\n- https://review.openocd.org/c/openocd/+/8913 (server/gdb_server: Step unavailable targets)\n- https://review.openocd.org/c/openocd/+/9123 (rtos: Dynamically allocate memory for RTOS registers)\n\n---\n\nTesting environment:\n\n1. In Syntacore we have an internal testsuite that runs on spike and RTL. I\u0027ve managed to run it on spike only (for now) - all our internal tests pass (modulo those that depend on new fixes committed since this PR was created).\n\n2. riscv-tests/debug, I used this version: https://github.com/riscv-software-src/riscv-tests/commit/51de00886cd28a3cf9b85ee306fb2b5ee5ab550e .For the last couple of years we used these tests in our internal CI. We use the following platforms:\n  - spike32\n  - spike32-2\n  - spike32-2-hwthread\n  - spike64\n  - spike64-2\n  - spike64-2-hwthread\n\nThere are some quirks with this testsuite and it\u0027s execution environment, however on the baseline we are able to obtain consistent results when running it.\n\n---\n\n\nCurrently I observe the following failures:\n\n- FreeRtosTest fails on platforms that have this test (that\u0027s understandable, since the respected patches are not part of the change chain I used).\n- ProgramSwWatchpoint **hangs** on **spike32-2-hwthread** and **spike64-2-hwthread**.\n\nAs far as ProgramSwWatchpoint test goes, I\u0027ve done an initial analysis - this looks like a serious issue on OpenOCD side. In the test gdb attempts to continue till the SW watchpoint condition is satisfied. However, due to fake single-step it goes into an infinite lopp. It looks as follows:\n\n```\ngdb_server.c:426 gdb_log_incoming_packet(): [riscv.cpu0] {1} received packet: vCont;s:1;c\ngdb_server.c:3178 gdb_handle_vcont_packet(): fake step thread 1\n```\n\n```\nhead -n 10000000 | spike32_2-ProgramSwWatchpoint.log | grep -e \u0027fake step thread 1\\|vCont;s:1;c\u0027  | wc -l\n```\n\ngives me 1299573 matches.\n\nWhile looking at the issue I asked Evgeniy for help with this and he pointed out that likely this is related to this change: https://github.com/riscv-collab/riscv-openocd/commit/efce094b409179acbaa7726c112a10fcf8343503 which AFAIK is missing from the change chain currently (he was going to publish the fixes for review soon)","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"ec5dcee7decdbbf9ec1f31fb64fd72a826ba376b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"273d0dc8_240dfc77","in_reply_to":"0e891e3e_21ffbeaf","updated":"2025-06-19 13:04:40.000000000","message":"\u003e I agree with Benhard: let\u0027s focus first to the easier parts of sync and bring something usable to upstream. The more complicated and not absolutely necessary parts can wait. Could we manage it ready for 1.0 release?\n\nAn alternative approach would be to run all the available testing on this version and at least try to understand what is broken by the diff outside `src/target/riscv`.\nAt least we can run the tests from https://github.com/riscv-software-src/riscv-tests/tree/master/debug on as many RISC-V targets as we can and track the difference between this version and the RISC-V fork.\nMoreover, we at Syntacore have an internal test suite we could run on this version too and report the issues we find. AFAIU, the guys from Codasip also run some internal testing.\nI\u0027m a bit afraid of the need to support two different versions -- let\u0027s at least make it a bit easier by figuring out how they differ.\n\nTo reiterate -- this is not the solution I would prefer. But we could agree to do this and we can try to finish it in time for the release.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a3698efcfa8a82a4b5a4c22be5beb84e1522c61a","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"aee9b780_548d97ff","in_reply_to":"10b05547_1ebfb162","updated":"2025-09-14 14:41:57.000000000","message":"Evgeniy,\nI run the tests on x86-64 PC (Ubuntu 24.04.3 LTS) to be able use the precompiled Syntacore package sc-dt-2025.06.tar.gz\nUnfortunately, there is a problem with `riscv64-unknown-elf-gdb`:\n```\nGNU gdb (sc.sc-dt.2025.06-experimental-8dc903a9) 16.2\n...\n(gdb) set remotetimeout 9\n/home/ci_user/.conan2/conan_homes/2.0.9/conan_0/p/b/riscv0aad492f0cbc1/b/gdb/gmp-utils.c:1\n68: internal-error: export_bits: Assertion `word_countp \u003d\u003d 1\u0027 failed.\nA problem internal to GDB has been detected,\n```\nThis problem prevents running debug tests from the suite, because `testlib.py` sets `remotetimeout` on each gdb run. With commented out python line emitting `set remotetimeout` command only 23 of 73 tests pass. Surprisingly `IcountTest` which didn\u0027t pass before now passed.\n\nI switched to `gdb-multiarch` (GNU gdb (Ubuntu 15.0.50.20240403-0ubuntu1) 15.0.50.20240403-git) and the tests resulted exactly same as they did on aarch64 where I also used `gdb-multiarch` (GNU gdb (Debian 13.1-3) 13.1).\n\nIMO the debug part of riscv-test is so heavily dependent to the used gdb version that we cannot take the results too seriously. The only relevant results we can get from comparison of tests with two different OpenOCD versions - and they were equal.\n\nI would recommend to investigate further the causes of failed UnavailableHaltedTest\nas it may be problem in OpenOCD - but it is not blocker of this patch.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"81281ca41c6c6e551a0a9af171ae6a2fbc907ae3","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"76252da2_e84b6d5e","in_reply_to":"11514ec8_d424208d","updated":"2025-05-25 21:22:27.000000000","message":"Obviously this patch is only a start -- there are more things in the riscv-collab tree well worth having in openocd. But a number of them are more problematic to get into a shape that is acceptable, and of course the most important (and most severely missed in upstream openocd) part is risc-v target bits. It would be great to have at least that part in 1.0.0.\n\nI\u0027ve tested the combination quite extensively - there\u0027s probably a few code paths in target/riscv that can\u0027t be reached in upstream openocd, but the parts that are used work well (and should make merging the other bits easier).\n\nI agree that the patch is too large to fully grasp, but that problem will only get worse as the branches diverge further, and at this point it already seems to be unrealistic to get things in sync again without a large merged chunk.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"137a1cbe83e44b32435fc60057aff5b65485d5e7","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"978a29aa_16576da4","in_reply_to":"149b1192_377b4c66","updated":"2025-08-11 11:27:00.000000000","message":"Please disregard my previous comment about infinite loops and hanging of the riscv-tests testsuite. I accidently tested the `master` version of OpenOCD instead of this patch.\n\nThe status of `riscv-tests` on this patch is as follows:\n- Targets `spike32`, `spike64`\n  - These tests end with exception\n    - FreeRtosTest\n    - RepeatReadTest\n    - UnavailableHaltedTest\n  - Other tests pass\n- Targets `spike64_2`, `spike32_2`\n  - These tests end with exception\n    - RepeatReadTest\n    - UnavailableHaltedTest\n  - Other tests pass\n- Target `multispike`\n  - These tests end with exception\n    - DebugChangeString\n    - RepeatReadTest\n  - This test fails\n    - UserInterrupt\n  - Other tests pass\n\nI have not investigated the root cause of failing tests, however I have at least compared the results of the listed tests to master commit 66ea461846a3a4a96687c9287c3f61ae8ce0b775, and I get the same failures/exceptions for the tests listed.\n\nOverall, after reviewing the patch and running the testsuites, I am in favor of merging this, since this is a clear improvement for RISC-V over the current state. However, I would prefer if my minor findings from my previous comment were addressed.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002161,"name":"Anatoly P","email":"kupokupokupopo@gmail.com","username":"ecco_the_dolphin"},"change_message_id":"7435153058319affc18132258a0869071a5bd841","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"9707e7e0_ec800104","in_reply_to":"253e1f86_6266fd6f","updated":"2025-10-22 11:44:29.000000000","message":"\u003e As you may not be familiar with gerrit, here is how to do so:\n\nYeah... This the case. I\u0027n not quite familiar with gerrit. Thanks for pointing these steps out. I\u0027ll try to re-apply  patches and re-run testing.\n\n\u003e BTW What is ProgramSwWatchpoint test? The name suggest software watchpoint, it sounds kind of unbelievable...\n\nIt is precisely that. The GDB has this feature. Basically, GDB tries to single step the program till the expression specified by user changes (or the condition becomes true).\n\nIn that case since OpenOCD attempts \"fake step\" no forward progress is made, resulting in a hang.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3a82bb31641fd43bb5fe95c2fb107e0b49f3064c","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"6093397d_50f029ea","in_reply_to":"273d0dc8_240dfc77","updated":"2025-07-26 09:26:59.000000000","message":"The v1.0.0-rc1 is still not tagged.\nIt could be nice to have this merged to move upstream the future dev of risc-v, but I don\u0027t have chips for testing (and probably nor even time for them).\nI\u0027m also reconsidering merging the cJTAG patch to complete the sync with risc-v fork.\n\nIf Codasip and Syntacore can verify that there is no regression for their tests, I would suggest to proceed with merge and use the rc2 to further mature this.\nIn case of regressions, let\u0027s check the workload to fix them.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"56e77eae598d0fd1b84976654b9bbef2cfdd647a","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"fe2a4770_b77a8d39","in_reply_to":"2927e522_e5c48489","updated":"2025-08-19 07:54:17.000000000","message":"All tests I have done here compared version with the commit this patch adds and the version without this commit. The internal version we have does not contain anything related to RISC-V aside from backports. Trough it is based on the `riscv-openocd` version.\n\nOur internal test suite runs on internal RTL models running in RTL simulation.\n\nAs for the fails related to RTOS. Question is if we want to expand this sync patch with the RTOS changes as well. I am in favor of merging this patch without those changes. This patch is already large as it is. Trough I don\u0027t have a particularly strong opinion on it.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"8df95abe5593c575a91bfcc33d22bac17719f658","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"6129a49b_4654af88","in_reply_to":"2d1a744f_7a116111","updated":"2025-11-11 13:08:52.000000000","message":"The series has been marked as submittable for a week. I plan to merge it tomorrow. If you have any important comments, please be quick.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"29add57e64921b69b06940ec111545c00e9553e6","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"a3bba14e_ba7f5d06","in_reply_to":"30ff1a8c_c7bea2cd","updated":"2025-11-03 22:23:34.000000000","message":"For details from testing see\nhttps://github.com/riscv-collab/riscv-openocd/issues/979\n\nI finished the tests.\nRun https://github.com/riscv-software-src/riscv-tests/ on spike, HiFive1 rev B (debug spec 0.11), GD32VF103, RP2350 and PolarFire SOC.\nTo ensure that hwthread and other patches outside src/target/riscv do not cause some regression, I \"ported\" the architecture less dependent part of riscv-tests to run on Cortex-M (RP2350) and Cortex-A (STM32MP157) - available only 26 - 28 tests, undoubtedly worth the effort expended. With mini series of Cortex-A targeted fixes all tests passed\n9211: target/cortex_a: fix HW breakpoint length for gdb kind 3 | https://review.openocd.org/c/openocd/+/9211\nI\u0027d like to add also aarch64 target, but I run out with my free time.\n\nTo complete the series we need to import\nhttps://github.com/riscv-collab/riscv-openocd/pull/1304\n@Evgeniy, could you please submit it here?\n\nand solve the wrong read on re-tried batch\nhttps://github.com/riscv-collab/riscv-openocd/issues/979#issuecomment-3468569015\n\nI\u0027ll start setting +2 scores.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"d62714cce7e8314ad123491afa081c45f3909cd5","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"5f2b7566_2a16809e","in_reply_to":"3203b760_eee1efc0","updated":"2025-08-12 14:28:57.000000000","message":"You can reproduce the assertion failure using the following script:\n\n```bash\n#!/usr/bin/env bash\n\nWORKDIR\u003d${WORKDIR:-~/repro}\nmkdir -p \"$WORKDIR\"\n\n# Download and build OpenOCD\nOPENOCD_REPO_URL\u003d${OPENOCD_REPO_URL:-https://review.openocd.org/openocd}\nOPENOCD_REVISION\u003d${OPENOCD_REVISION:-refs/changes/93/8893/10}\nopenocd_repo_path\u003d\"${WORKDIR}\"/openocd\nenv -C \"$WORKDIR\" git clone --depth\u003d1 --revision\u003d\"$OPENOCD_REVISION\" \"$OPENOCD_REPO_URL\" \\\n|| (\n\tenv -C \"$WORKDIR\" git clone -n --depth\u003d1 \"$OPENOCD_REPO_URL\" \\\n\t\u0026\u0026 git -C \"$openocd_repo_path\" fetch --depth\u003d1 origin \"$OPENOCD_REVISION\" \\\n\t\u0026\u0026 git -C \"$openocd_repo_path\" checkout FETCH_HEAD \\\n)\ncd \"$openocd_repo_path\"\n./bootstrap with-submodules\n./configure \\\n\t--enable-internal-libjaylink \\\n\t--enable-internal-jimtcl \\\n\t--enable-remote-bitbang\nmake -j\ncd -\n\n# Install Syntacore Development Toolkit\n# (includes cross GNU binutils and GDB for RISC-V)\n# See https://syntacore.com/tools/development-tools\nSC_DT_URL\u003d${SC_DT_URL:-\u0027https://drive.syntacore.com/s/8Atb2bcYjZS8eHE/download?path\u003d/2025/2025.06\u0026files\u003dsc-dt-2025.06.tar.gz\u0027}\ncurl \"$SC_DT_URL\"| tar -C \"$WORKDIR\" -xz\nsource \"$WORKDIR\"/sc-dt/env.sh\n\n# Download and build Spike -- RISC-V ISA simulator.\n# Building Spike requires some system packages, like Device Tree Compiler.\n# See https://github.com/riscv-software-src/riscv-isa-sim?tab\u003dreadme-ov-file#build-steps\nSPIKE_REPO_URL\u003d${SPIKE_REPO_URL:-https://github.com/riscv-software-src/riscv-isa-sim.git}\nenv -C \"$WORKDIR\" git clone --depth\u003d1 \"$SPIKE_REPO_URL\"\nspike_repo\u003d\"$WORKDIR\"/riscv-isa-sim\ncd \"$spike_repo\"\n./configure\nmake -j$(($(nproc) / 2))\ncd -\n\n# To launch Spike, a target ELF file is needed.\n# The following steps create a suitable dummy executable.\nboot_spike_base\u003d\"$WORKDIR\"/boot_spike64\ncat /dev/zero | head -c 1 \u003e \"$boot_spike_base\".bin\nriscv64-unknown-elf-objcopy \\\n\t--input-target\u003dbinary \\\n\t--output-target\u003delf64-littleriscv \\\n\t\"$boot_spike_base\".bin \\\n\t\"$boot_spike_base\".o\nriscv64-unknown-elf-ld \"$boot_spike_base\".o -o \"$boot_spike_base\".elf\n\n# Launch Spike in background.\n# Adjust memory map (`-m`) if using a different binary/linker script.\n\"$spike_repo\"/spike \\\n\t-p2 \\\n\t--isa RV64IV_Zvl512b \\\n\t-m0x10000:0x20000 \\\n\t--rbb-port 7777 \\\n\t\"$boot_spike_base\".elf \\\n\t\u003c /dev/null \u0026\nspike_pid\u003d$!\n\n# Launch GDB. Observe the assertion failure.\nriscv64-unknown-elf-gdb \\\n\t-ex \"target remote | \\\n\t\t\u0027$openocd_repo_path/src/openocd\u0027 \\\n\t\t\t-c \u0027gdb_port pipe\u0027 \\\n\t\t\t-c \u0027adapter driver remote_bitbang\u0027 \\\n\t\t\t-c \u0027remote_bitbang port 7777\u0027 \\\n\t\t\t-c \u0027jtag newtap riscv cpu -irlen 5\u0027 \\\n\t\t\t-c \u0027target create c0 riscv -chain-position riscv.cpu -rtos hwthread\u0027 \\\n\t\t\t-c \u0027target create c1 riscv -chain-position riscv.cpu -rtos hwthread\u0027 \\\n\t\t\t-c \u0027target smp c0 c1\u0027\" \\\n\t-ex \u0027thread 2\u0027 \\\n\t-ex \u0027p $v0\u0027 \\\n\t--batch\n\n# Reap Spike.\nkill -TERM $spike_pid\nwait $spike_pid\n```\n\nFor instructions on how to run the full RISC-V Tests debug testsuite see [1].\n\nI\u0027ll try to post further analysis of the failures sometime this week.\n\n[1]: https://github.com/riscv-software-src/riscv-tests/tree/master/debug#debug-tests","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"9ee9cd47badd1a90046bccedff966fe0f5a4c72d","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"10b05547_1ebfb162","in_reply_to":"3f4c5d06_d70c8e1d","updated":"2025-09-13 21:59:04.000000000","message":"I finally had time to run\nhttps://github.com/riscv-software-src/riscv-tests/\nwith freshly build spike.\n\nI compared this patch with the new follow-ups up to \n9127: target, flash, doc: Create riscv repeat_read command | https://review.openocd.org/c/openocd/+/9127\nversus the fresh https://github.com/riscv-collab/ code, 48483a84a064ee5487aa3e8a2c2494722a3c3849\n\nOn target spike64-2-hwthread both OpenOCD versions pass 59 tests,\n9 tests returned not_applicable.\n\n2 tests returned fail:\n- IcountTest\n- MulticoreRtosSwitchActiveHartTest\n\n3 tests returned exception or does not finish\n- PrivChange\n- StepTest\n- UnavailableHaltedTest\n\nAll was run on aarch64, so the problems might be due to unusual host arch.\nI will eventually re-run on x86-64 to see if it helps.\n\nAnyway **there is no difference spotted by the test suite between RISC-V fork and the planned sync**: please review following patches in the series and we will be ready to sync!","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"c6271e78c1ff1b6ca344b59ac0ce55d4917c5a26","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"0e891e3e_21ffbeaf","in_reply_to":"40e3c16d_6d431015","updated":"2025-06-19 12:28:22.000000000","message":"I\u0027m sorry for taking so long to reply.\n\n\u003e I\u0027ve tested the combination quite extensively - there\u0027s probably a few code paths in target/riscv that can\u0027t be reached in upstream openocd, but the parts that are used work well (and should make merging the other bits easier).\n\nPlease, consider running the following sequence of commands on any RISC-V target:\n```\n\u003e version git\nv0.12.0-1010-g9f5275b05\n\u003e reset halt\nJTAG tap: riscv.cpu tap/device found: 0xdeadbeef (mfg: 0x777 (Fabric of Truth Inc), part: 0xeadb, ver: 0xd)\n\u003e reg pc\npc (/64): 0x0000000000001000\n\u003e reg pc 0\npc (/64): 0x0000000000001000\n\u003e reg pc\npc (/64): 0x0000000000000000\n```\nAs you can see, there is a bug. The `reg pc 0` should have returned `pc (/64): 0x0000000000000000` (this is the case for all but one other registers). This is a known issue and there is a patch that fixes it [1], but it is not merged yet.\n\nI do agree that this bug is minor. However, the point I\u0027m trying to make is: RISC-V OpenOCD is poorly tested even in the configuration that is in the fork.\nMy opinion is -- it\u0027s not production-ready code and it should not be included in the upcoming release.\n\n[1]: https://github.com/riscv-collab/riscv-openocd/pull/1187","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3f310a6164143d32e333a2e0735f96460b9aaf84","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"dfe66bc5_c8a36f4d","in_reply_to":"538fe9c9_624db61f","updated":"2025-05-07 14:07:58.000000000","message":"There is also something to upstream in folder `doc`","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f618e9a189d38f6bb9934625e3112d43cec690a2","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"30ff1a8c_c7bea2cd","in_reply_to":"5af3ecee_3e1ba744","updated":"2025-10-23 06:51:38.000000000","message":"Anatoly,\nyour feedback is very valuable!\n\nThe last patched OpenOCD version still lacked\n9176: rtos: server: target: ask the RTOS which target to set swbp on. | https://review.openocd.org/c/openocd/+/9176\nEvgeniy submitted it based on our git master but there was lot of conflicts with the riscv-sync series.\n\nToday I removed some conflicting work from the series, namely\n9125: target/breakpoints: breakpoint_add() rework | https://review.openocd.org/c/openocd/+/9125\nand relatives and put 9176 instead of it.\n\nMy run of riscv-tests suite with spike64-2-hwthread target showed failures\nin\n- MulticoreRtosSwitchActiveHartTest\n- PrivChange\n- StepTest\n- UnavailableHaltedTest\nwhich is very similar to my previous tests - see my comment from Sept 19th.\n\nI will upload the modified series soon.\n\n\u003e 2. I want to make sure I\u0027m communicating this correctly. Is this discussion the right place for this, or would starting a new thread be better? Any guidance would be appreciated.\n\nWell, I admit the narrow gerrit discussion format is not ideal for such long discussion. If you prefer we can move to riscv-collab github","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0a0737ef55b13def7d9afcc87d0ac9f32b5be4be","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"87f9645d_6e54b5de","in_reply_to":"5f2b7566_2a16809e","updated":"2025-08-13 09:09:44.000000000","message":"Thanks both for testing and for providing a way to reproduce it.\nNot working on RISC-V, I was not aware of \u0027spike\u0027, nice!\n\nQuestion for Evgeniy and Marek to eventually address the fix:\nWhich version of OpenOCD is your reference? I mean, this patch adds issues wrt which version? The upstream, the RISC-V fork, your company\u0027s internal one?","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"d035a1b18bf0af48aea78beeafd687d05adadd4e","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"0a08fb13_7ed40fbe","in_reply_to":"6093397d_50f029ea","updated":"2025-07-30 11:57:01.000000000","message":"Hello, thanks for preparing this MR.\n\nMy colleague Jan is currently occupied with non-OpenOCD work.\nMyself, I should be able to take a look at this MR next week if things go well.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"35c8d307dd56a30d8932085324418580803b1ddb","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"40e3c16d_6d431015","in_reply_to":"76252da2_e84b6d5e","updated":"2025-06-19 08:02:53.000000000","message":"Evgeniy, could you please give your opinions to my reply and in the light of (small but at least some) progress of RISC-V sync series? I also add Jan to reviewers.\n\nI agree with Benhard: let\u0027s focus first to the easier parts of sync and bring something usable to upstream. The more complicated and not absolutely necessary parts can wait. Could we manage it ready for 1.0 release?","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"085befb89379ac27bf791c045ab3534a4692569a","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"11514ec8_d424208d","in_reply_to":"7a9b9814_3d682437","updated":"2025-05-19 09:11:28.000000000","message":"Evgeniy,\n\n\u003e There are significant changes in the RISC-V OpenOCD fork outside of target/riscv.\n\u003e Namely (from diff between current master and merge from master to riscv-openocd/riscv[1]):\n\u003e\n\u003e    server/gdb_server.c -- handling of unavailable targets\n\u003e    target/breakpoints.c in breakpoint_add/remove() etc.\n\nIn the `riscv sync` series I imported hopefully all changes related to unavailable targets except `target/breakpoints: Clear software breakpoints from available targets #879` which is IMO optional, lot of changed code and for the moment not absolutely necessary.\nI\u0027m sure there is still lot of TODOs for unavailable targets: e.g. reset handling,\nunavailable during examine etc... Anyway the new code at least should not cause any regressions to targets which does not use it at all.\n\n\n\u003e    target/target.c in target_examine()\n\nand mostly related `handle_target()`\nHmm, to be honest it\u0027s not a good code. Neither in the upstream repo nor in riscv-collab. It\u0027s just different.\n - riscv polls not yet examined targets: generally not a bad idea but will break many of other targets, also in collision with examine deferred \n - static variable `examine_attempted`: strange, examination of any target starts re-examinations of all others - seems that riscv team focuses on SMP and neglect AMP\n - `riscv_openocd_poll()` is screwed in that each call of poll of any target from a SMP group causes all harts in the group are polled. If we have 8 cores in SMP, each core will be polled 8 times in one poll interval. Undoubtedly waste of debug interface throughput, it may also conceal some problems in riscv poll.\n\nI\u0027m afraid we need a substantial rework of both `handle_target()` and `riscv_openocd_poll()`. The former has been on my TODO list for long time...\n\n\n\u003e    src/rtos -- there are many changes. The majority is related to FreeRTOS, however there is also changes to rtos/rtos.c itself.\n\nYes, lot of work. The part of rtos/hwthread handling of unavailable targets\nis in the `riscv sync` series. Is there anything else what is necessary for debugging without FreeRTOS?","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"3084977c192c7c2f6fd6e87dab266841e8ee61f6","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"2927e522_e5c48489","in_reply_to":"87f9645d_6e54b5de","updated":"2025-08-13 09:32:11.000000000","message":"This particular platform is not tested in RISC-V OpenOCD\u0027s CI, so I\u0027m comparing with an internal version (it is included in the same devtoolkit from the reproduction and can be found here [1]).\n\nI can double-check, but I\u0027m pretty sure RISC-V OpenOCD\u0027s TOT passes these tests.\n\nAFAIU, the assertion failure is related to commit ef3e61bebc53f619f42bb06cfd194cd547cceb69 (\"Dynamically allocate memory for RTOS registers. (#647)\") [2].\n\nIn any case, at least for the RISC-V Tests [3] on Spike, I believe they either should pass or should be adjusted before the patch is merged -- the testsuite is quite small and does not require any special hardware to run (when running on Spike).\n\n1: https://github.com/syntacore/openocd\n2: https://github.com/riscv-collab/riscv-openocd/commit/ef3e61bebc53f619f42bb06cfd194cd547cceb69\n3: https://github.com/riscv-software-src/riscv-tests/tree/master/debug","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002161,"name":"Anatoly P","email":"kupokupokupopo@gmail.com","username":"ecco_the_dolphin"},"change_message_id":"581350b9a3c33fdf089a48a96a67aed1abe14b57","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"5af3ecee_3e1ba744","in_reply_to":"9707e7e0_ec800104","updated":"2025-10-22 21:41:14.000000000","message":"@Tomas\n\n\u003e For the next time please be sure to include whole patch series\n\nDone. I used the following command to fetch the series (just for the reference):\n\n\n```\ngit fetch https://review.openocd.org/openocd refs/changes/77/9177/2 \u0026\u0026 git checkout FETCH_HEAD\n```\n\n___\n\nTest environment:\n\nThis time I\u0027ve run riscv-test from https://github.com/riscv-software-src/riscv-tests/commit/59554a6a1deae92df4480918cc1432cc5a312fd2 (I\u0027ve bumped the revision to the current TOT since last time, but I don\u0027t think that there were changes that could affect results).\n\nI\u0027ve run testsuite 10 times (each run used different seed for PRNG).\n\nSame 6 platforms.\n___\n\n Results:\n \n - spike32-2/spike64-2: no failures\n - spike32/spike64: only FreeRtosTest fails (as expected)\n - spike32-2-hwthread/spike64-2-hwthread:\n     - DebugTurbostep (4 of 10 failures)\n     - HwbpManual (4 of 10 failures)\n     - InstantChangePc (7 of 10 failures)\n     - StepTest (4 of 10 failures)\n     - StepThread2Test (10 if 10 failures)\n     - ProgramSwWatchpoint (5 of 10 failures, finished with exception)\n     \nNOTE: no hangs this time.\n\n___\n\nI **briefly** looked at some of test logs. Here is what I derive from ProgramSwWatchpoint. The communication on gdbremote looks as follows:\n\nroi from openocd log, near the end of session\n\n```\ngdb_log_incoming_packet(): [riscv.cpu0] {1} received packet: vCont;s:1\ngdb_handle_vcont_packet(): [riscv.cpu0] single-step thread 1\n...\nriscv_step_rtos_hart(): [riscv.cpu0] Stepping.\n..\ntarget_call_event_callbacks(): target event 2 (resumed) for core riscv.cpu0                                            \ntarget_call_event_callbacks(): target event 0 (gdb-halt) for core riscv.cpu0                                           \ntarget_call_event_callbacks(): target event 1 (halted) for core riscv.cpu0                                             \ntarget_call_event_callbacks(): target event 8 (gdb-end) for core riscv.cpu0                                            \ntarget_call_event_callbacks(): target event 6 (step-end) for core riscv.cpu0\n...\nriscv_openocd_poll(): [riscv.cpu0] should_remain_halted\u003d0, should_resume\u003d0                                              \nhwthread_update_threads(): [riscv.cpu0] current_thread\u003d2, threads_found\u003d2\n// This looks weird, why do we refer to riscv.cpu1?\ngdb_last_signal(): [riscv.cpu1] Debug reason is: SINGLESTEP\n// And this looks like an error to me.\ngdb_log_outgoing_packet(): [riscv.cpu0] {1} sending packet: $T05thread:2;#d8\n```\n\nBoom! We\u0027re running into a GDB crash (using a version based on 16.2). As per the log above, the issue occurred when GDB requested to single-step thread 1, but OpenOCD instead replied with a state change for thread 2.\n\nFor reference, the vCont format is `vCont[;action[:thread-id]]…` (https://sourceware.org/gdb/current/onlinedocs/gdb.html/Packets.html#vCont-packet).\n\nMy **guess** is that StepThread2Test is broken for a similar reason. The logs indicate that the active thread changed unexpectedly, though I\u0027m not sure why - I haven\u0027t had time to investigate.\n\n**If** it would be useful - I can debug this further tomorrow. \n\nFew additional notes:\n1. I\u0027m just not sure if someone is already working on this kind of issue (I\u0027ve seen several merge requests related to SMP, stepping, and breakpoint handling from various people).\n2. I want to make sure I\u0027m communicating this correctly. Is this discussion the right place for this, or would starting a new thread be better? Any guidance would be appreciated.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"0ae5e7a0634fc880730519a95c0684c943365240","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"3203b760_eee1efc0","in_reply_to":"978a29aa_16576da4","updated":"2025-08-11 16:01:44.000000000","message":"I\u0027ve been able to run the tests but I\u0027m still analyzing the results.\n\nWhat I have found so far is: the patch fails with an assertion while running `CustomRegisterTest` on `spike64-2-hwthread` target from RISC-V Debug Tests.\n```\nopenocd: ocd_sources/src/rtos/hwthread.c:327: hwthread_get_thread_reg: Assertion `bytes \u003c\u003d sizeof(rtos_reg-\u003evalue)\u0027 failed.\n```\nI will double-check and provide a detailed instruction how to reproduce this.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"302e2bc667c891f71181f2bfe4567281e93d73eb","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"2d1a744f_7a116111","in_reply_to":"a3bba14e_ba7f5d06","updated":"2025-11-06 10:54:55.000000000","message":"\u003e @Evgeniy, could you please submit it here?\n\nDone.\n9233: target/riscv: fix progbuf memory writes in case last write is busy | https://review.openocd.org/c/openocd/+/9233\n\nThere is an assertion failure when force-reading a dirty register. See https://github.com/riscv-collab/riscv-openocd/issues/1309\nIt does reproduce on c1d8ff3022aabf969d23538f8938a0e96fe2698f.\nHowever, I\u0027d suggest addressing it later and finishing the sink without fixing it.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a0b3b5b71f29e6613d2a50f09227cefc15576b12","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"fa71f5b9_a5a9e874","in_reply_to":"aee9b780_548d97ff","updated":"2025-09-19 19:42:07.000000000","message":"More detail on failed tests from\nhttps://github.com/riscv-software-src/riscv-tests/\n\nIcountTest:\nFails because gdb (both 13.1 and 15) creates a temporary breakpoint to skip over the breakpoint set by the test @ main(). Undoubtedly not related to OpenOCD\n\nPrivChange and StepTest:\ngdb (both 13.1 and 15) prefers its own step implementation setting a temporary breakpoint @ next instruction and issuing packet vCont;c instead of direct stepping vCont;s\nMight be related to https://sourceware.org/bugzilla/show_bug.cgi?id\u003d28440\nAnyway not related to OpenOCD, test would work if `stepi` were replaced by `maintenance packet vCont;c` and `maintenance flush register-cache`.\n\nUnavailableHaltedTest:\nAlthough fails with both upstream and RISC-V OpenOCD version, the results differ. As I expected I found another important patch missing in upstream:\n9138: gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not implemented | https://review.openocd.org/c/openocd/+/9138\n\nMulticoreRtosSwitchActiveHartTest:\nSeems me very strange. The test expects harts to run one by one, not all as SMP target always run. No idea how it could ever work. Does it require FreeRTOS target? Please explain if you know more.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"d264f6a63a1794c32866ac4c870a2a70227d9df7","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"3f4c5d06_d70c8e1d","in_reply_to":"af401c28_bff8c481","updated":"2025-09-12 08:37:32.000000000","message":"I think this is a good approach. cJTAG functionality is not critical for this sync to work. I prefer to keep patches self-contained as possible trough with RISC-V sync this isn\u0027t possible.\n\nQuestion is, do we want an \"incomplete version\" in upstream OpenOCD? Maybe we could add a warning on RISC-V target startup here to warn users about it.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"34fcb9a14a5abf05ee3667f668ff4c4983bdb80b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"253e1f86_6266fd6f","in_reply_to":"b0dc6854_820cebb4","updated":"2025-10-22 11:11:19.000000000","message":"Anatoly, thanks for testing and for finding another missing patch!\n\nFor the next time please be sure to include whole patch series (currently 34 patches). To get representative test results avoid testing of just some partial selection of patches.\nAs you may not be familiar with gerrit, here is how to do so:\n- show a gerrit page of any patch from the series\n- press `SHOW ALL` button right of `Relation chain` title\n- select top most patch from the `Relation chain` list which is not marked as `Merged` - this is currently\n9177: server: rtos: don\u0027t fake step for hwthread rtos. | https://review.openocd.org/c/openocd/+/9177\n- press DOWNLOAD and select branch\n- after pasting it to command line, you may change branch name from `-b change-8913` to something more human friendly\n- you may or may not `git rebase origin/master` where origin is set to review.openocd.org\n\nBTW What is ProgramSwWatchpoint test? The name suggest software watchpoint, it sounds kind of unbelievable...","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002366,"name":"Liam Fletcher","display_name":"Li-Fletch","email":"liam.fletcher@microchip.com","username":"Li-Fletch","status":"Microchip"},"change_message_id":"294c201d0b75a12c336443df70b63dbe57635a27","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"7a9b9814_3d682437","in_reply_to":"dfe66bc5_c8a36f4d","updated":"2025-05-16 06:54:03.000000000","message":"\u003e Distinguish changes to the \"core\" code (e.g. target_examine()) from additional RISC-V independent features (e.g. the change to FreeRTOS support).\n\nFWIW, I have tested this patchset out w.r.t multi DM\u0027s on a DMI (similar to the change #8893 that I have proposed). I\u0027m happy that this incoming patchset works. Just to note, I am also happy enough to close #8893 in an effort to reduce the amount of review if this patchset is moving forward?\n \nAlso, happy to test any subsequent bumps.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f747c8fe5a9f83682b8b93397f9b8e1d2aa53bfb","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"0d9ffbc1_9c327a95","in_reply_to":"fa71f5b9_a5a9e874","updated":"2025-10-21 06:45:25.000000000","message":"Antonio wrote in 9165: target: riscv: move the SMP commands under riscv | https://review.openocd.org/c/openocd/+/9165:\n\n\u003e By the way, what should we do with this series?\n\u003e Apart possibly reverting my changes in the commit message 9127 9141 9143 9144, anything else we are waiting for?\n\u003e But I\u0027ve not seen new reports on testing this series\n\nYes, it makes me sad. Except couple of older negative scores from Evgeniy and Marek, almost nobody cares. We probably should start merging the series.\n\nPotentially problematic:\n9123: rtos: Dynamically allocate memory for RTOS registers | https://review.openocd.org/c/openocd/+/9123\nHopefully solved by 9135, to be confirmed by Marek.\n\n8913: server/gdb_server: Step unavailable targets. | https://review.openocd.org/c/openocd/+/8913\nRelevant comment by Evgeniy, however the solution is not trivial and nobody has submitted any patch - IMO we can use what riscv-collab uses - not perfect but works\n\n9125: target/breakpoints: breakpoint_add() rework | https://review.openocd.org/c/openocd/+/9125\nI\u0027m not too happy with this my own patch. After introducing target capability bits we could go easier way and instead of complicated try and possible return ERROR_BREAKPOINT_NOT_SET_TRY_NEXT_SMP_CORE we could use the finer grained target capabilities and keep all SMP target selection logic in breakpoint.c\nAnyway there is lot of pending patches around BP/WP handling. 9125 and 9126 are not crucial for RISC-V support and we can merge the series without them.\n\nSoft breakpoint removal does not handle unavailable targets (the Tim\u0027s patch https://github.com/riscv-collab/riscv-openocd/commit/39a4f37f84d52aa38ffa1a7db703ad57deec4fdc\nassumes the target has to be halted and available to remove BP - so we cannot import it directly) - IMO we can go without it, similarly as with the previous one.\n\nAny other problems?","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"f5c02a2f4f56c5ac7e3a205eb4238c374b4ddf3e","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":4,"id":"af401c28_bff8c481","in_reply_to":"fe2a4770_b77a8d39","updated":"2025-08-19 08:25:05.000000000","message":"The effort to merge this huge patch is to get aligned upstream and riscv fork, in the wish to continue the development in a single place.\nI have separately rebased the part related to cJTAG for the same reason\nhttps://review.openocd.org/c/openocd/+/6981\n\nIf the lack of sync on RTOS can prevent someone to use the code upstream, I would like to get it merged too (not in this same patch).\nThe big diffs are on `rtos.c`, `rtos.h`, `hwthread.c`, `rtos_standard_stackings.c` and`freertos.c`.\nComments are welcome","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"de8319db1c077fa3a88fb235ad032e9eb99f431b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"63f16203_8fb8b091","updated":"2025-05-05 23:26:01.000000000","message":"This should address all remaining comments.","commit_id":"027fd6f80b280a32a7d8f9f522ceb4e4f9935c3b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1279688124573c2fea2bc0d13d2c4682338a710e","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":7,"id":"35c0fa2d_f74a48f4","updated":"2025-05-18 06:05:51.000000000","message":"Good work, Bernard.\n\nI have no objections against the huge sync patch in the riscv subdir.\nHowever I would prefer more review friendly patches for the changes in OpenOCD\ncore code.\n\nI submitted the original PR https://github.com/riscv-collab/riscv-openocd/pull/752 which adds target unavailable state because I used it before in my not yet upstreamed work. Could you please rebase this one on top of\n8911: target: Add TARGET_UNAVAILABLE state | https://review.openocd.org/c/openocd/+/8911\n\nI think we should treat this way other differences spotted by Evgeniy","commit_id":"1dbb329bfe827424ea66115024f452996794cc64"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"81281ca41c6c6e551a0a9af171ae6a2fbc907ae3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"cc1473ae_9dbf0502","in_reply_to":"35c0fa2d_f74a48f4","updated":"2025-05-25 21:22:27.000000000","message":"Done. There are no other changes outside of src/target/riscv left in this patch.","commit_id":"1dbb329bfe827424ea66115024f452996794cc64"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"81281ca41c6c6e551a0a9af171ae6a2fbc907ae3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"4781014e_bf937df9","updated":"2025-05-25 21:22:27.000000000","message":"Patchset 8 - rebasing to current master + 8891 - added","commit_id":"9f5275b059ff27acf69921761008509a4683adcb"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"ae624ff6cd120e154bec5a001bb0fde0c71b4473","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":9,"id":"b61e43b2_2e2bbe94","updated":"2025-08-06 07:47:24.000000000","message":"Here are few things I have found, please, also add the commit which this sync is based on to the commit message. It appears that this is based on an unmerged PR: https://github.com/riscv-collab/riscv-openocd/pull/1253","commit_id":"681743f8defc7a70460e832b4a79deaca70c17a5"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"8ec0573ab7d81da521185308759f9a0e4425e085","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":9,"id":"7aee1575_c329a5fd","updated":"2025-08-03 10:45:54.000000000","message":"rebased to solve the merge conflict created by\nhttps://review.openocd.org/c/openocd/+/8989\n\nI have changed the title of the commit message to match OpenOCD style\n`s,\\[target/riscv\\],target: riscv:,`\n\nI add -1 because this rebase removes the -1 from Evgeniy","commit_id":"681743f8defc7a70460e832b4a79deaca70c17a5"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"6c0326aa75805a1d296c884c1a881906c8abdf2d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"4fc4226b_3a8c92bb","updated":"2025-08-17 11:24:08.000000000","message":"I just ran the patch against my test bench and found a memory leak, see comment below.","commit_id":"0d8925f7812ef197fb12860a0407c39e04ea65a6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"bf972ec4728c0d3e5a71dbf330a8f365813417c0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"03b59210_e6eaf0b0","updated":"2025-09-15 07:52:49.000000000","message":"I noticed this patch lacks doc changes.\nAdded in separate patch\n9130: doc: import document changes relevant to riscv code update | https://review.openocd.org/c/openocd/+/9130","commit_id":"0d8925f7812ef197fb12860a0407c39e04ea65a6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"08f28040f6ffc9e206fecb84215dd24dfbde3841","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":10,"id":"b60e929d_08f3b071","updated":"2025-08-05 08:55:39.000000000","message":"Re added -1 from Evgeniy","commit_id":"0d8925f7812ef197fb12860a0407c39e04ea65a6"}],"src/helper/Makefile.am":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[{"line_number":19,"context_line":"\t%D%/jim-nvp.c \\"},{"line_number":20,"context_line":"\t%D%/nvp.c \\"},{"line_number":21,"context_line":"\t%D%/align.h \\"},{"line_number":22,"context_line":"\t%D%/binarybuffer.h \\"},{"line_number":23,"context_line":"\t%D%/bits.h \\"},{"line_number":24,"context_line":"\t%D%/configuration.h \\"},{"line_number":25,"context_line":"\t%D%/list.h \\"}],"source_content_type":"application/octet-stream","patch_set":1,"id":"d184a46a_6cc4c149","line":22,"updated":"2025-05-04 20:34:48.000000000","message":"Please add also `base64.h`, otherwise this will not pass `make distcheck`","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"aeabf98c2c4aa6e744ebb523bb0481bd10448de9","unresolved":false,"context_lines":[{"line_number":19,"context_line":"\t%D%/jim-nvp.c \\"},{"line_number":20,"context_line":"\t%D%/nvp.c \\"},{"line_number":21,"context_line":"\t%D%/align.h \\"},{"line_number":22,"context_line":"\t%D%/binarybuffer.h \\"},{"line_number":23,"context_line":"\t%D%/bits.h \\"},{"line_number":24,"context_line":"\t%D%/configuration.h \\"},{"line_number":25,"context_line":"\t%D%/list.h \\"}],"source_content_type":"application/octet-stream","patch_set":1,"id":"1d1b38f5_b050c9bb","line":22,"in_reply_to":"d184a46a_6cc4c149","updated":"2025-05-05 01:22:09.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"}],"src/helper/base64.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * Base64 encoding/decoding (RFC1341)"},{"line_number":3,"context_line":" * Copyright (c) 2005-2011, Jouni Malinen \u003cj@w1.fi\u003e"},{"line_number":4,"context_line":" *"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"b7d8c5c1_8f0e7194","line":1,"updated":"2025-05-04 20:34:48.000000000","message":"Please change the comment as:\n```\n// SPDX-License-Identifier: BSD-3-Clause\n\n/*\n * Base64 encoding/decoding (RFC1341)\n * Copyright (c) 2005-2011, Jouni Malinen \u003cj@w1.fi\u003e\n *\n * Original file from FreeBSD code\n * https://cgit.freebsd.org/src/commit/contrib/wpa/src/utils/base64.c?id\u003df05cddf940db\n */\n```","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"aeabf98c2c4aa6e744ebb523bb0481bd10448de9","unresolved":false,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * Base64 encoding/decoding (RFC1341)"},{"line_number":3,"context_line":" * Copyright (c) 2005-2011, Jouni Malinen \u003cj@w1.fi\u003e"},{"line_number":4,"context_line":" *"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"76258946_92754221","line":1,"in_reply_to":"b7d8c5c1_8f0e7194","updated":"2025-05-05 01:22:09.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[{"line_number":42,"context_line":"\tif (olen \u003c len)"},{"line_number":43,"context_line":"\t\treturn NULL; /* integer overflow */"},{"line_number":44,"context_line":"\tout \u003d malloc(olen);"},{"line_number":45,"context_line":"\tif (out \u003d\u003d NULL)"},{"line_number":46,"context_line":"\t\treturn NULL;"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"\tend \u003d src + len;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"23451f28_7af9db28","line":45,"updated":"2025-05-04 20:34:48.000000000","message":"no NULL comparison. Use:\n` if (!out)`","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"b4e1ec60f1399f30a81e50206a11eb70d50918b7","unresolved":false,"context_lines":[{"line_number":42,"context_line":"\tif (olen \u003c len)"},{"line_number":43,"context_line":"\t\treturn NULL; /* integer overflow */"},{"line_number":44,"context_line":"\tout \u003d malloc(olen);"},{"line_number":45,"context_line":"\tif (out \u003d\u003d NULL)"},{"line_number":46,"context_line":"\t\treturn NULL;"},{"line_number":47,"context_line":""},{"line_number":48,"context_line":"\tend \u003d src + len;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"c5c562f7_9ea9bed9","line":45,"in_reply_to":"23451f28_7af9db28","updated":"2025-05-04 22:06:48.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[{"line_number":105,"context_line":""},{"line_number":106,"context_line":"\tmemset(dtable, 0x80, 256);"},{"line_number":107,"context_line":"\tfor (i \u003d 0; i \u003c sizeof(base64_table) - 1; i++)"},{"line_number":108,"context_line":"\t\tdtable[base64_table[i]] \u003d (unsigned char) i;"},{"line_number":109,"context_line":"\tdtable[\u0027\u003d\u0027] \u003d 0;"},{"line_number":110,"context_line":""},{"line_number":111,"context_line":"\tcount \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8a387c1d_2b1cd2e6","line":108,"updated":"2025-05-04 20:34:48.000000000","message":"no space between cast and variable `i`","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"b4e1ec60f1399f30a81e50206a11eb70d50918b7","unresolved":false,"context_lines":[{"line_number":105,"context_line":""},{"line_number":106,"context_line":"\tmemset(dtable, 0x80, 256);"},{"line_number":107,"context_line":"\tfor (i \u003d 0; i \u003c sizeof(base64_table) - 1; i++)"},{"line_number":108,"context_line":"\t\tdtable[base64_table[i]] \u003d (unsigned char) i;"},{"line_number":109,"context_line":"\tdtable[\u0027\u003d\u0027] \u003d 0;"},{"line_number":110,"context_line":""},{"line_number":111,"context_line":"\tcount \u003d 0;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"dd602108_cf24e944","line":108,"in_reply_to":"8a387c1d_2b1cd2e6","updated":"2025-05-04 22:06:48.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[{"line_number":118,"context_line":"\t\treturn NULL;"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"\tolen \u003d count / 4 * 3;"},{"line_number":121,"context_line":"\tpos \u003d out \u003d malloc(olen);"},{"line_number":122,"context_line":"\tif (out \u003d\u003d NULL)"},{"line_number":123,"context_line":"\t\treturn NULL;"},{"line_number":124,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"5e99bdf1_3cc3da73","line":121,"updated":"2025-05-04 20:34:48.000000000","message":"No multiple assignments, no NULL comparison\n```\n\tout \u003d malloc(olen);\n\tif (!out)\n\t\treturn NULL;\n\tpos \u003d olen;\n```","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"b4e1ec60f1399f30a81e50206a11eb70d50918b7","unresolved":false,"context_lines":[{"line_number":118,"context_line":"\t\treturn NULL;"},{"line_number":119,"context_line":""},{"line_number":120,"context_line":"\tolen \u003d count / 4 * 3;"},{"line_number":121,"context_line":"\tpos \u003d out \u003d malloc(olen);"},{"line_number":122,"context_line":"\tif (out \u003d\u003d NULL)"},{"line_number":123,"context_line":"\t\treturn NULL;"},{"line_number":124,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":1,"id":"f5ee5541_e8f8dd31","line":121,"in_reply_to":"5e99bdf1_3cc3da73","updated":"2025-05-04 22:06:48.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"}],"src/helper/base64.h":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * Base64 encoding/decoding (RFC1341)"},{"line_number":3,"context_line":" * Copyright (c) 2005, Jouni Malinen \u003cj@w1.fi\u003e"},{"line_number":4,"context_line":" *"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"79c4f2a9_4ef31aa4","line":1,"updated":"2025-05-04 20:34:48.000000000","message":"The fun on licensing. It\u0027s missing SPDX. But at first we need to find where this file (and its partner .c) comes from.\nIt looks like:\nhttps://web.mit.edu/freebsd/head/contrib/wpa/src/utils/base64.c\nhttps://web.mit.edu/freebsd/head/contrib/wpa/src/utils/base64.h\nbut I cannot find the SHA1 related to this version of code. I have analyzed FreeBSD history, but still not clear.\nAnyway the full license is BSD-3-Clause.\n\n\nPlease change the comment as:\n```\n/* SPDX-License-Identifier: BSD-3-Clause */\n\n/*\n * Base64 encoding/decoding (RFC1341)\n * Copyright (c) 2005, Jouni Malinen \u003cj@w1.fi\u003e\n *\n * Original file from FreeBSD code\n * https://cgit.freebsd.org/src/commit/contrib/wpa/src/utils/base64.h?id\u003df05cddf940db\n */\n```","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"aeabf98c2c4aa6e744ebb523bb0481bd10448de9","unresolved":false,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * Base64 encoding/decoding (RFC1341)"},{"line_number":3,"context_line":" * Copyright (c) 2005, Jouni Malinen \u003cj@w1.fi\u003e"},{"line_number":4,"context_line":" *"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"50a0e122_da15b8ec","line":1,"in_reply_to":"6e6cb41d_11f48619","updated":"2025-05-05 01:22:09.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"b4e1ec60f1399f30a81e50206a11eb70d50918b7","unresolved":true,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * Base64 encoding/decoding (RFC1341)"},{"line_number":3,"context_line":" * Copyright (c) 2005, Jouni Malinen \u003cj@w1.fi\u003e"},{"line_number":4,"context_line":" *"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"6e6cb41d_11f48619","line":1,"in_reply_to":"79c4f2a9_4ef31aa4","updated":"2025-05-04 22:06:48.000000000","message":"I\u0027ve checked out the FreeBSD source from https://git.freebsd.org/src.git and a commit with that commit hash exists in the code.\n\nThere is a much newer version of the base64 code in place, but I\u0027ve had a quick look and it doesn\u0027t add anything useful in our context, just makes things more flexible to different newline styles etc. - so it makes sense to stay on this version.\n\n    commit f05cddf940dbfc5b657f5e9beb9de2c31e509e5b\n    Merge: 2173825bacf8 5e2639d568f6\n    Author: Rui Paulo \u003crpaulo@FreeBSD.org\u003e\n    Date:   Thu Jul 4 21:12:58 2013 +0000\n\n    Merge hostapd / wpa_supplicant 2.0.\n    \n    Reviewed by:    adrian (driver_bsd + usr.sbin/wpa)","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"521982004b44859ae6e8c191712c7110175a4c53","unresolved":true,"context_lines":[{"line_number":1,"context_line":"/* SPDX-License-Identifier: BSD-2-Clause"},{"line_number":2,"context_line":" *"},{"line_number":3,"context_line":" * Base64 encoding/decoding (RFC1341)"},{"line_number":4,"context_line":" * Copyright (c) 2005, Jouni Malinen \u003cj@w1.fi\u003e"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"47948c08_ba9cb4a1","line":1,"updated":"2025-05-05 09:44:53.000000000","message":"No, please modify the comment as I wrote in my previous review.\nThe license is BSD-3-Clause (as reported in the license file of the original project).\nKeep the SPDX as an independent comment\nDrop the lines below about BSD (it does not specify which) and about README (not used in this project for license).\nAnd please also add the origin URL where this comes from. It\u0027s relevant for the licensing too.\nAgain, it would be better to get this as a separate patch.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"de8319db1c077fa3a88fb235ad032e9eb99f431b","unresolved":false,"context_lines":[{"line_number":1,"context_line":"/* SPDX-License-Identifier: BSD-2-Clause"},{"line_number":2,"context_line":" *"},{"line_number":3,"context_line":" * Base64 encoding/decoding (RFC1341)"},{"line_number":4,"context_line":" * Copyright (c) 2005, Jouni Malinen \u003cj@w1.fi\u003e"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"7fcd2cfd_bd0a06ee","line":1,"in_reply_to":"47948c08_ba9cb4a1","updated":"2025-05-05 23:26:01.000000000","message":"Done and submitted separately at https://review.openocd.org/c/openocd/+/8895","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"}],"src/target/riscv/debug_defines.h":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"3c7008cc340f1174faaae45cba51b25952969d7d","unresolved":true,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * This file is auto-generated by running \u0027make debug_defines\u0027 in"},{"line_number":3,"context_line":" * https://github.com/riscv/riscv-debug-spec/ (40b9a05)"},{"line_number":4,"context_line":" */"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"#ifndef DEBUG_DEFINES_H"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"f19b37a5_428c9830","line":3,"updated":"2025-05-04 20:34:48.000000000","message":"This file, like the other auto-generated files, could have some exception wrt checkpatch.\nPlease see in `HACKING` how to add the tag `Checkpatch-ignore:` in the commit message for such exceptions.\n\nMore important, this file misses the license tag!\nWith Tim Newsome we have spent quite some time at clarifying the license of this file.\nOriginally it was CC-BY-4.0, not compatible with OpenOCD GPLv2, and after the merged of\nhttps://github.com/riscv/riscv-debug-spec/pull/968\nit become dual license BSD-2-Clause and CC-BY-4.0.\nTo accept this patch upstream, it is mandatory to first update this file in the riscv fork, using a version generated after the pull request above.","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"aeabf98c2c4aa6e744ebb523bb0481bd10448de9","unresolved":false,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * This file is auto-generated by running \u0027make debug_defines\u0027 in"},{"line_number":3,"context_line":" * https://github.com/riscv/riscv-debug-spec/ (40b9a05)"},{"line_number":4,"context_line":" */"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"#ifndef DEBUG_DEFINES_H"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"8a376c8b_e03c61e9","line":3,"in_reply_to":"db13a227_b62d50db","updated":"2025-05-05 01:22:09.000000000","message":"Done","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"b4e1ec60f1399f30a81e50206a11eb70d50918b7","unresolved":true,"context_lines":[{"line_number":1,"context_line":"/*"},{"line_number":2,"context_line":" * This file is auto-generated by running \u0027make debug_defines\u0027 in"},{"line_number":3,"context_line":" * https://github.com/riscv/riscv-debug-spec/ (40b9a05)"},{"line_number":4,"context_line":" */"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"#ifndef DEBUG_DEFINES_H"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"db13a227_b62d50db","line":3,"in_reply_to":"f19b37a5_428c9830","updated":"2025-05-04 22:06:48.000000000","message":"Will try to regenerate the file with current riscv-debug-spec git, and if successful, try to upstream the results to both versions","commit_id":"eaef40d67f200976bae4c67c16ba003ecc404fed"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"521982004b44859ae6e8c191712c7110175a4c53","unresolved":true,"context_lines":[{"line_number":1,"context_line":"/* SPDX-License-Identifier: BSD-2-Clause */"},{"line_number":2,"context_line":"/* This file was auto-generated by running \u0027make debug_defines\u0027 in https://github.com/riscv/riscv-debug-spec/ (22a7576) */"},{"line_number":3,"context_line":""},{"line_number":4,"context_line":"#ifndef DEBUG_DEFINES_H"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"0dab2668_81ed9ab8","line":1,"updated":"2025-05-05 09:44:53.000000000","message":"We cannot change the license at our wish, as we are not the owners of the file.\nThe autogenerated header is different.\nCheckpatch complains, that\u0027s true.\nI have just pushed https://review.openocd.org/c/openocd/+/8894\nCan you rebase this patch on top of it?","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"de8319db1c077fa3a88fb235ad032e9eb99f431b","unresolved":false,"context_lines":[{"line_number":1,"context_line":"/* SPDX-License-Identifier: BSD-2-Clause */"},{"line_number":2,"context_line":"/* This file was auto-generated by running \u0027make debug_defines\u0027 in https://github.com/riscv/riscv-debug-spec/ (22a7576) */"},{"line_number":3,"context_line":""},{"line_number":4,"context_line":"#ifndef DEBUG_DEFINES_H"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"95a65ea7_ddf1f9fd","line":1,"in_reply_to":"0dab2668_81ed9ab8","updated":"2025-05-05 23:26:01.000000000","message":"I\u0027m not a lawyer, but I\u0027m pretty sure in this particular case, changing the license to BSD-2-Clause is OK, because it is one of the licenses offered by the original file and neither one of the licenses says you can\u0027t impose additional restrictions on redistributions (such as leaving out one of the options).\n\nBut it\u0027s certainly better to keep the license as it is once that doesn\u0027t cause problems with the license checks in OpenOCD anymore. Changed back to the original options.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"521982004b44859ae6e8c191712c7110175a4c53","unresolved":true,"context_lines":[{"line_number":3204,"context_line":"\tAC_ACCESS_MEMORY_ORDINAL,"},{"line_number":3205,"context_line":"\tVIRT_PRIV_ORDINAL"},{"line_number":3206,"context_line":"};"},{"line_number":3207,"context_line":"typedef struct {"},{"line_number":3208,"context_line":"\tstruct {"},{"line_number":3209,"context_line":"\t\tunsigned int value; int is_set;"},{"line_number":3210,"context_line":"\t} DXLEN;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"1cc26472_bb0e7a12","line":3207,"updated":"2025-05-05 09:44:53.000000000","message":"Four new typedef.\nI need to think about this. Maybe I will add a patch on top of this change","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"},{"author":{"_account_id":1002269,"name":"Bernhard Rosenkränzer","display_name":"Bernhard \"bero\" Rosenkränzer","email":"bero@baylibre.com","username":"bero","status":"BayLibre"},"change_message_id":"de8319db1c077fa3a88fb235ad032e9eb99f431b","unresolved":false,"context_lines":[{"line_number":3204,"context_line":"\tAC_ACCESS_MEMORY_ORDINAL,"},{"line_number":3205,"context_line":"\tVIRT_PRIV_ORDINAL"},{"line_number":3206,"context_line":"};"},{"line_number":3207,"context_line":"typedef struct {"},{"line_number":3208,"context_line":"\tstruct {"},{"line_number":3209,"context_line":"\t\tunsigned int value; int is_set;"},{"line_number":3210,"context_line":"\t} DXLEN;"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"33ca45cb_a8c03f23","line":3207,"in_reply_to":"1cc26472_bb0e7a12","updated":"2025-05-05 23:26:01.000000000","message":"I have a version without those typedefs -- but I\u0027d rather keep them in place to make it less of a pain to update the autogenerated files when the spec changes.\n\nI\u0027ll submit the typedef removals separetely, but would prefer that patch to be dropped. But it\u0027s your call.","commit_id":"650cd8882fb2f9932082891e2b087615104c4255"}],"src/target/riscv/riscv.c":[{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"6c0326aa75805a1d296c884c1a881906c8abdf2d","unresolved":true,"context_lines":[{"line_number":4223,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":4224,"context_line":""},{"line_number":4225,"context_line":"\tRISCV_INFO(r);"},{"line_number":4226,"context_line":"\tbool *wps_to_enable \u003d calloc(r-\u003etrigger_count, sizeof(*wps_to_enable));"},{"line_number":4227,"context_line":"\tif (disable_watchpoints(target, wps_to_enable) !\u003d ERROR_OK) {"},{"line_number":4228,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Failed to temporarily disable \""},{"line_number":4229,"context_line":"\t\t\t\t\"watchpoints before single-step.\");"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"7844f573_981c9dbe","line":4226,"updated":"2025-08-17 11:24:08.000000000","message":"This is never free\u0027d and causes a memory leak. You can reproduce this by executing a single-step. Target was a SiFive HiFive1 board.","commit_id":"0d8925f7812ef197fb12860a0407c39e04ea65a6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"8df95abe5593c575a91bfcc33d22bac17719f658","unresolved":false,"context_lines":[{"line_number":4223,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":4224,"context_line":""},{"line_number":4225,"context_line":"\tRISCV_INFO(r);"},{"line_number":4226,"context_line":"\tbool *wps_to_enable \u003d calloc(r-\u003etrigger_count, sizeof(*wps_to_enable));"},{"line_number":4227,"context_line":"\tif (disable_watchpoints(target, wps_to_enable) !\u003d ERROR_OK) {"},{"line_number":4228,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Failed to temporarily disable \""},{"line_number":4229,"context_line":"\t\t\t\t\"watchpoints before single-step.\");"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"faf0ff54_e19a51b0","line":4226,"in_reply_to":"022b1328_d322d567","updated":"2025-11-11 13:08:52.000000000","message":"Fixed in\n9163: target: riscv: fix memory leak in riscv_openocd_step_impl() | https://review.openocd.org/c/openocd/+/9163","commit_id":"0d8925f7812ef197fb12860a0407c39e04ea65a6"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"b12f1e087dfcd9b4aa52205a2e9507bbf20a95e9","unresolved":true,"context_lines":[{"line_number":4223,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":4224,"context_line":""},{"line_number":4225,"context_line":"\tRISCV_INFO(r);"},{"line_number":4226,"context_line":"\tbool *wps_to_enable \u003d calloc(r-\u003etrigger_count, sizeof(*wps_to_enable));"},{"line_number":4227,"context_line":"\tif (disable_watchpoints(target, wps_to_enable) !\u003d ERROR_OK) {"},{"line_number":4228,"context_line":"\t\tLOG_TARGET_ERROR(target, \"Failed to temporarily disable \""},{"line_number":4229,"context_line":"\t\t\t\t\"watchpoints before single-step.\");"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"022b1328_d322d567","line":4226,"in_reply_to":"7844f573_981c9dbe","updated":"2025-08-18 13:19:08.000000000","message":"Thanks for the catch!\nIt\u0027s my bad.\nThe leak was introduced in commit 5a8697b3cf5c4e4abde77ac1726a76877592dfa9 (\"target/riscv: manage triggers available to OpenOCD for internal use\")[1]. I don\u0027t quite understand how we have missed it during the review [2].\n\nI\u0027ve filed an issue in RISC-V OpenOCD regarding this [3].\nIt\u0027s strange that we didn\u0027t catch it: we do run RISC-V Tests internally under Valgrind and with Address Sanitizer, and AFAIU there are tests covering watchpoints. Will investigate in the issue.\n\n1: https://github.com/riscv-collab/riscv-openocd/commit/5a8697b3cf5c4e4abde77ac1726a76877592dfa9\n2: https://github.com/riscv-collab/riscv-openocd/pull/1111\n3: https://github.com/riscv-collab/riscv-openocd/issues/1284","commit_id":"0d8925f7812ef197fb12860a0407c39e04ea65a6"}]}