)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"45853f4f337a44fb174dc82d471f4a850582e16f","unresolved":true,"context_lines":[{"line_number":9,"context_line":"Take endianness into account when inserting software breakpoints"},{"line_number":10,"context_line":"since, cortex_a target is also used by cortex_r and some MCUs of the"},{"line_number":11,"context_line":"architecture start in big-endian by default (e.g. TMS570)"},{"line_number":12,"context_line":"This was previously commited by Andrey Smirnov on 2014-07-12 in a"},{"line_number":13,"context_line":"similar way."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"Change-Id: I68b7fe7c4604de67fee2e64fff0fad2691659a58"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"64c2b66e_8b5fea23","line":12,"updated":"2025-05-17 14:02:38.000000000","message":"Jenkins auto-builder detected a typo here for \"committed\".\nNever mind, as this will not show in the commit message if you follow my previous instructions.","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"b606e8a94810b7cc9e510f5dc04b4b4176d42940","unresolved":false,"context_lines":[{"line_number":9,"context_line":"Take endianness into account when inserting software breakpoints"},{"line_number":10,"context_line":"since, cortex_a target is also used by cortex_r and some MCUs of the"},{"line_number":11,"context_line":"architecture start in big-endian by default (e.g. TMS570)"},{"line_number":12,"context_line":"This was previously commited by Andrey Smirnov on 2014-07-12 in a"},{"line_number":13,"context_line":"similar way."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"Change-Id: I68b7fe7c4604de67fee2e64fff0fad2691659a58"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"83086c4d_da32375f","line":12,"in_reply_to":"64c2b66e_8b5fea23","updated":"2025-05-20 13:55:48.000000000","message":"Ack","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"39d08801a520726d4c8412f383253841dd23bb9e","unresolved":false,"context_lines":[{"line_number":9,"context_line":"Take endianness into account when inserting software breakpoints"},{"line_number":10,"context_line":"since, cortex_a target is also used by cortex_r and some MCUs of the"},{"line_number":11,"context_line":"architecture start in big-endian by default (e.g. TMS570)"},{"line_number":12,"context_line":"This was previously commited by Andrey Smirnov on 2014-07-12 in a"},{"line_number":13,"context_line":"similar way."},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"Change-Id: I68b7fe7c4604de67fee2e64fff0fad2691659a58"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"c44ac929_c46cfca9","line":12,"in_reply_to":"64c2b66e_8b5fea23","updated":"2025-05-20 13:52:23.000000000","message":"Done","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"7dffb33fa2e177b05d0794e6cb19d3587580d9ac","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"973895ac_2682b6d1","updated":"2025-05-16 13:54:50.000000000","message":"Hey, you might want to have a look at this 😊","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0f3125e2bddbba212059639659358b9e9d0bb1ef","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"5e24e286_b6b5f64c","updated":"2025-05-17 08:34:17.000000000","message":"Hi Lucien,\nthanks for taking alive this old patch. I will take care of the merge.\n\nTo keep the history in gerrit and to correctly maintain the authorship, I would prefer that you \"abandon\" this change number 8909, then you push again this same patch but:\n- with the same change-id of the original change https://review.openocd.org/c/openocd/+/2208\n- with author Andrey Smirnov \u003candrew.smirnov@gmail.com\u003e\n- with double signed off, having Adrey as first and you as second,\n- the commit message does not need to report the old commit, as it would be implicit in gerrit history\n\nThe patch 2208 is part of a patch series, but you can ignore that","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"075e3093207c9df3f59dee67ad38f21b224565e3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"e5c2878e_57e6913e","updated":"2025-05-18 09:04:05.000000000","message":"Is this patch really correct? According to the Cortex-A/R docs [1,2], instruction fetches are always treated as little-endian except for Cortex-R4/R5 (legacy reasons).\n\n[1] https://developer.arm.com/documentation/den0042/a/Coding-for-Cortex-R-Processors/Endianness\n[2] https://developer.arm.com/documentation/den0013/d/Porting/Endianness","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"0f5a593babab009c488b0e6fd5d9b2f2f0a79b24","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"ef143788_0a18207f","in_reply_to":"00d818df_f60de433","updated":"2025-05-19 09:31:03.000000000","message":"Thanks at all, very cool investigations.\n\nI can confirm that 0xc14 is part of my cpuid: 0x411fc143\n(\"TMS570LS1224 integrates the ARM Cortex-R4F\")","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"39d08801a520726d4c8412f383253841dd23bb9e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"a020159b_034cf3b5","in_reply_to":"5e24e286_b6b5f64c","updated":"2025-05-20 13:52:23.000000000","message":"The patch is now changed considerably wrt patch 2208.\nI don\u0027t see the need to keep it in the same history.","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"b606e8a94810b7cc9e510f5dc04b4b4176d42940","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"758ef924_e55f875f","in_reply_to":"5e24e286_b6b5f64c","updated":"2025-05-20 13:55:48.000000000","message":"since it is now something","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"46ceba896ecf4b0ec62a3374c6b965adaba3e56e","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"00d818df_f60de433","in_reply_to":"e5c2878e_57e6913e","updated":"2025-05-18 21:47:31.000000000","message":"Thanks for the links, Marc.\nIn my big-endian tests I compile OpenOCD for Cortex-A7 big-endian and run it on qemu.\nI have checked the generated binary and the instructions are in the binary as in little-endian!\nThis patch will definitively not work for big-endian Cortex-A7.\n\nAccording to\nhttps://en.wikipedia.org/wiki/ARM_architecture_family#Cores\nthere are 4 possible ARMv7-R cores: Cortex-R4, R5, R7 an R8.\nAnd ARM doc you pointed say that only\n\u003e The Cortex-R4 and Cortex-R5 can be configured to support big-endian Instruction code. This is to support legacy systems.\n\nThe original patch was for TMS570 that is a Cortex-R5F. It was ok for that CPU but breaks for others.\n\nWe cannot simply discriminate between Cortex-A and Cortex-R, we need something more.\nDuring `cortex_a_examine_first()` we already read the `CPUDBG_CPUID` register in variable `cpuid` (actually ARM doc calls it `MIDR`).\nFor Cortex-A7 the value of `cpuid` is 0x410fc075, where bits[15:4] \u003d 0xc07 means Cortex-A7 (see table in `arm_adi_v5.c`).\nThese bits[15:4] should be 0xc14 and 0xc15 respectively for Cortex-R4 and Cortex-R5 (not tested).\nThe CPU type should be saved (or only a bool for Cortex-R4 and Cortex-R5) and later, while setting the SW breakpoint, we need to swap only for Cortex-R4 and Cortex-R5 big-endian.\n\nThe same check is required also for disassembly the binary code in OpenOCD for Cortex-R4 and Cortex-R5 big-endian.\n\nI don\u0027t expect other parts of OpenOCD to be impacted.","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"b606e8a94810b7cc9e510f5dc04b4b4176d42940","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2c7f7a09_e4f94108","in_reply_to":"ef143788_0a18207f","updated":"2025-05-20 13:55:48.000000000","message":"Ack","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"39d08801a520726d4c8412f383253841dd23bb9e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"a12202bc_a4ae0db9","in_reply_to":"ef143788_0a18207f","updated":"2025-05-20 13:52:23.000000000","message":"Ack","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a385c16bb81373b5b621472c49111ae48ac6644a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"0b52c444_caf123b3","updated":"2025-05-20 12:51:59.000000000","message":"Nice simplification.\nFew comments below","commit_id":"0004f89ed4902b0c86502257a3028a65ea7ebecd"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"39d08801a520726d4c8412f383253841dd23bb9e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"9db29f91_42226f36","updated":"2025-05-20 13:52:23.000000000","message":"Looks ok for me, thanks.\nMarc, any comment?","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"9b9813cd6d7643bbdf327806531dab5e7b923cd7","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"3eef3185_345cc307","in_reply_to":"22b555d0_0a2341ad","updated":"2025-06-02 11:11:10.000000000","message":"Unfortunately I can not test anymore, as my XDS110 seems to be extremely unreliable at the moment (not working 99.9% of the time). Last time it worked quite well with the software version `2.3.0.5` (got shipped with this one 3-4 weeks ago), but then I updated it via the TI\u0027s uniflash tool to `3.0.0.36`. Downgrade is no option, as I do not have the firmware 2.3.0.5 and searching for it takes too much time.\n\nI have rebased the f0xx flash driver from Andrey Smirnov (2014) and fixed some things to get it nearly running. Maybe I should open a PR just to publish the current state. What I noted though, is that the needed endianess of the instructions matches the endianess in his compiled file: `https://review.openocd.org/c/openocd/+/2214/6/contrib/loaders/flash/f0xx/compiled/tms570-helper.h` . However, my rebased version with a current version of gcc created a wrong byte order for the `tms570_helper_text`, so I manually fixed this by a quick hack in the `https://review.openocd.org/c/openocd/+/2214/6/contrib/loaders/flash/f0xx/elf-to-h.py`.","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"991a6a8b76da3c0b11b1152a24fa697eda2e94b2","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"38064493_4809fd68","in_reply_to":"24cf084e_9a9275fc","updated":"2025-05-21 12:41:12.000000000","message":"Thanks Marc for testing it on real hardware, that gives us confidence there will be no degradation 👍\nI could only test it on the TMS570LS1224, as it is the only hardware I have.\nNote that I can not test any further patches, as I\u0027ve updated my freshly bought XDS110 from 2.3.0.5 to 3.0.0.32 which seem to have broken its full (hopefully full) functionality.\nIf possible keep the potential future shiny part_info-style completely separate from this patch, as it eases my future rebasing (or even keep it low prio 😊 ).\n\nI\u0027m not sure though, if I will/can continue working on this cool project. 🙏","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"6e524ea56af8470adbed17b07e9a4b363ec0eee5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"c7e19842_1250283d","in_reply_to":"32fa71bb_8bcd674e","updated":"2025-06-02 13:34:00.000000000","message":"Marc, I always though that `-endian` at `target create` should impact both data and instructions.\nBut what we see with Cortex-R4 is a potential mix, that\u0027s why I\u0027m looking for an automatic detection.\nI don\u0027t expect this patch to break anything, but to help debugging these TMS570 devices.\nI\u0027m ok to merge it and look for improvements later on","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"9a863aa7e3dfcc4fc951ad54ca19c22635457f79","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"ad49b657_edb630f3","in_reply_to":"38064493_4809fd68","updated":"2025-05-24 09:03:05.000000000","message":"Works as expected, tested on TMS570LS1224. For me the XDS110 interface does not work as well on the Launchpad. It works, but very slow, using the CMSIS-DAP adapter. Can you confirm this? For my tests I used an external debug adapter.\n\nWould be if you can adapt the commit message. It does not exactly cover the issue that is fixed here, right? Cortex-R4/R5 do not \u0027start\u0027 in BE but require BE for instructions.","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"07c22d16c7ea134a5eb3f28520766657b9b6f433","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"24cf084e_9a9275fc","in_reply_to":"389d54aa_3b210ba0","updated":"2025-05-21 12:35:01.000000000","message":"In the long term, yes, it would also be nice to have the processor type in the printed log during examine.\nBut I see this as outside the scope of this patch.\nThis patch also highlights that the name of the debug registers in OpenOCD do not match the ARM documentation. CPUID does not exists and it is instead MIDR. We need to run a full review of existing register names.","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"6cec45f5d8cd6f81bd30f06bc9826e11c2dafb08","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"32fa71bb_8bcd674e","in_reply_to":"3eef3185_345cc307","updated":"2025-06-02 11:29:13.000000000","message":"Hmm, I have to take back the flame against the version `3.0.0.36`, today the XDS110 is working well. Seems like it works on mondays. Maybe, last week, I powered the board first and then hot-plugged the XDS110.","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"232bed301744aeb03c579d77838e2382bd3568e5","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"22b555d0_0a2341ad","in_reply_to":"6662ecd3_8bdc5eb7","updated":"2025-06-01 14:47:20.000000000","message":"Thanks for the information Antonio - it\u0027s indeed a bit more complicated :-/ I experimented with the `SCTRL` register etc. and then I found out that I don\u0027t have a `TMS570LS1224` but `RM46L852`. There is a `TMS570` sticker on the development board, which caused the confusion. According to the RM, the latter uses little-endian for instruction fetches. This is also what I see in the `SCTRL` register. The `TMS570LS1224` uses big-endian according to the RM. I will some more tests, maybe also with some more targets once I have access.\n\n@Lucien can you confirm the big-endian in the `SCTLR`?\n\nAs far as I can see is the `endian` flag implicitly used for *data endianness*. \nWith this patch it is mixed with *instruction endiannness*. For that reason I would suggest not to merge this patch as-is. What do you think Antonio? What\u0027s the reason to merge it? It implements a broken fix, no?","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"1ec28172ee68e69a4477f61781678902ee41db91","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"389d54aa_3b210ba0","in_reply_to":"9db29f91_42226f36","updated":"2025-05-21 06:43:38.000000000","message":"I would prefer a \u0027part_info\u0027 approach like for Cortex-M processors. I can extend this in a followup patch. What do you think Antonio?\n\nThe patch seems okay, let me check it on real hardware please.","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"24aeaba44bc2cf59d4842b8577e9995dee7262c0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"6662ecd3_8bdc5eb7","in_reply_to":"ad49b657_edb630f3","updated":"2025-05-24 16:30:33.000000000","message":"I\u0027m not asking to modify this patch, let\u0027s proceed merging it, but:\n\nLooking for the keyword `endian` in ARM DDI0406.\nThe endianness at start (reset) is defined by the SoC designer that has set the value of the external signal `ENDIANSTATE`.\nSW can change endianness at runtime with instruction `SETEND`.\nWe can have a different endian in the exception handler through `SCTLR.EE`.\nSince we can change endianness during exceptions, I think we can run userland applications of either little or big endian.\n\nSo the situation looks a little more complex than our simple model of using the static flag `-endian` to `target create`.\nProbably we should improve the flag `-endian` with a new value `auto` (or even completely ignore this flag on Cortex-A/R) and let OpenOCD to detect the current data endianness from `CPSR.E` and the instruction endianness from `SCTLR.IE`.\n\nIt should be interesting to check on your TMS570: after run the assembly instruction `SETEND 0`, does both `CPSR.E` and `SCTLR.IE` become zero?\nAnd the instructions after `SETEND 0` are fetched in little-endian?\nJust to understand if `SCTLR.IE` is a reliable info after changing endianness.\n\nMaybe I can test this with qemu-system-arm. It emulates cortex-r5 and cortex-r5f but I don\u0027t know if the switch LE \u003c\u003d\u003e BE is correctly implemented.","commit_id":"619b4734395d43aca099c5c1151ef5b1f8f43523"}],"src/target/cortex_a.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"45853f4f337a44fb174dc82d471f4a850582e16f","unresolved":true,"context_lines":[{"line_number":1327,"context_line":"\t\tuint8_t code[4];"},{"line_number":1328,"context_line":"\t\tif (breakpoint-\u003elength \u003d\u003d 2) {"},{"line_number":1329,"context_line":"\t\t\t/* length \u003d\u003d 2: Thumb breakpoint */"},{"line_number":1330,"context_line":"\t\t\ttarget_buffer_set_u16(target, code, (uint16_t) ARMV5_T_BKPT(0x11));"},{"line_number":1331,"context_line":"\t\t} else if (breakpoint-\u003elength \u003d\u003d 3) {"},{"line_number":1332,"context_line":"\t\t\t/* length \u003d\u003d 3: Thumb-2 breakpoint, actual encoding is"},{"line_number":1333,"context_line":"\t\t\t * a regular Thumb BKPT instruction but we replace a"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"51fe9a4a_831e803b","line":1330,"updated":"2025-05-17 14:02:38.000000000","message":"remove the space after the cast `(uint16_t)` to make checkpatch happy","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a385c16bb81373b5b621472c49111ae48ac6644a","unresolved":false,"context_lines":[{"line_number":1327,"context_line":"\t\tuint8_t code[4];"},{"line_number":1328,"context_line":"\t\tif (breakpoint-\u003elength \u003d\u003d 2) {"},{"line_number":1329,"context_line":"\t\t\t/* length \u003d\u003d 2: Thumb breakpoint */"},{"line_number":1330,"context_line":"\t\t\ttarget_buffer_set_u16(target, code, (uint16_t) ARMV5_T_BKPT(0x11));"},{"line_number":1331,"context_line":"\t\t} else if (breakpoint-\u003elength \u003d\u003d 3) {"},{"line_number":1332,"context_line":"\t\t\t/* length \u003d\u003d 3: Thumb-2 breakpoint, actual encoding is"},{"line_number":1333,"context_line":"\t\t\t * a regular Thumb BKPT instruction but we replace a"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"38e6e9c2_351b522f","line":1330,"in_reply_to":"51fe9a4a_831e803b","updated":"2025-05-20 12:51:59.000000000","message":"not anymore relevant in the new code","commit_id":"a016d4c29b75bb403198d1cbe3df470519437d4e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a385c16bb81373b5b621472c49111ae48ac6644a","unresolved":true,"context_lines":[{"line_number":1342,"context_line":"\t\t}"},{"line_number":1343,"context_line":""},{"line_number":1344,"context_line":"\t\t// ARM instruction fetches are usually LE, but not for the"},{"line_number":1345,"context_line":"\t\t// Cortex-R4(F?) and Cortex-R5(F?)"},{"line_number":1346,"context_line":"\t\tif (((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc140) ||"},{"line_number":1347,"context_line":"\t\t    ((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc150)) {"},{"line_number":1348,"context_line":"\t\t\tif (target-\u003eendianness !\u003d TARGET_LITTLE_ENDIAN)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"20e1bfc9_cd9a878b","line":1345,"updated":"2025-05-20 12:51:59.000000000","message":"Write more details. Plus, for multi-line comments the coding style requires comments as:\n```\n/*\n * ARMv7-A/R fetches instructions in little-endian on both LE and BE CPUs.\n * But Cortex-R4 and Cortex-R5 big-endian require BE instructions.\n * https://developer.arm.com/documentation/den0042/a/Coding-for-Cortex-R-Processors/Endianness\n * https://developer.arm.com/documentation/den0013/d/Porting/Endianness\n */\n```","commit_id":"dfdb6dfba94601b848b2691daae33d9b13a074f6"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"b606e8a94810b7cc9e510f5dc04b4b4176d42940","unresolved":false,"context_lines":[{"line_number":1342,"context_line":"\t\t}"},{"line_number":1343,"context_line":""},{"line_number":1344,"context_line":"\t\t// ARM instruction fetches are usually LE, but not for the"},{"line_number":1345,"context_line":"\t\t// Cortex-R4(F?) and Cortex-R5(F?)"},{"line_number":1346,"context_line":"\t\tif (((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc140) ||"},{"line_number":1347,"context_line":"\t\t    ((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc150)) {"},{"line_number":1348,"context_line":"\t\t\tif (target-\u003eendianness !\u003d TARGET_LITTLE_ENDIAN)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"0344cecc_27d419a8","line":1345,"in_reply_to":"20e1bfc9_cd9a878b","updated":"2025-05-20 13:55:48.000000000","message":"Ack","commit_id":"dfdb6dfba94601b848b2691daae33d9b13a074f6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"39d08801a520726d4c8412f383253841dd23bb9e","unresolved":false,"context_lines":[{"line_number":1342,"context_line":"\t\t}"},{"line_number":1343,"context_line":""},{"line_number":1344,"context_line":"\t\t// ARM instruction fetches are usually LE, but not for the"},{"line_number":1345,"context_line":"\t\t// Cortex-R4(F?) and Cortex-R5(F?)"},{"line_number":1346,"context_line":"\t\tif (((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc140) ||"},{"line_number":1347,"context_line":"\t\t    ((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc150)) {"},{"line_number":1348,"context_line":"\t\t\tif (target-\u003eendianness !\u003d TARGET_LITTLE_ENDIAN)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"70dd8885_457265ce","line":1345,"in_reply_to":"20e1bfc9_cd9a878b","updated":"2025-05-20 13:52:23.000000000","message":"Done","commit_id":"dfdb6dfba94601b848b2691daae33d9b13a074f6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"a385c16bb81373b5b621472c49111ae48ac6644a","unresolved":true,"context_lines":[{"line_number":1345,"context_line":"\t\t// Cortex-R4(F?) and Cortex-R5(F?)"},{"line_number":1346,"context_line":"\t\tif (((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc140) ||"},{"line_number":1347,"context_line":"\t\t    ((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc150)) {"},{"line_number":1348,"context_line":"\t\t\tif (target-\u003eendianness !\u003d TARGET_LITTLE_ENDIAN)"},{"line_number":1349,"context_line":"\t\t\t\t// In place swapping is allowed"},{"line_number":1350,"context_line":"\t\t\t\tbuf_bswap32(code, code, 4);"},{"line_number":1351,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"771cd2ba_4f34672e","line":1348,"updated":"2025-05-20 12:51:59.000000000","message":"Put all in a single `if` condition.\nAnd we have the enum `TARGET_BIG_ENDIAN`, you can use it here since we swap only in big-endian case.\n\nI see in https://en.wikipedia.org/wiki/ARM_architecture_family#Cores\nthat there are non-ARM CPU in the list of ARMv7-A.\nSo checking only the bits[15:4] of cpuid could be not enough.\nWe already had issues with the CPUID of Cortex-M not made by ARM, I don\u0027t want we get issues later on Cortex-A/R too.\n\nPlease define in src/target/cortex_a.h after CPUDBG_CPUID:\n```\n#define CPUDBG_CPUID_MASK      0xff00fff0\n#define CPUDBG_CPUID_CORTEX_R4 0x4100c140\n#define CPUDBG_CPUID_CORTEX_R5 0x4100c150\n```\nand in this test use something like\n`((cortex_a-\u003ecpuid \u0026 CPUDBG_CPUID_MASK) \u003d\u003d CPUDBG_CPUID_CORTEX_R4)`","commit_id":"dfdb6dfba94601b848b2691daae33d9b13a074f6"},{"author":{"_account_id":1002405,"name":"Lucien Buchmann","email":"lucien.buchmann@dufour.aero","username":"lucien"},"change_message_id":"b606e8a94810b7cc9e510f5dc04b4b4176d42940","unresolved":false,"context_lines":[{"line_number":1345,"context_line":"\t\t// Cortex-R4(F?) and Cortex-R5(F?)"},{"line_number":1346,"context_line":"\t\tif (((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc140) ||"},{"line_number":1347,"context_line":"\t\t    ((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc150)) {"},{"line_number":1348,"context_line":"\t\t\tif (target-\u003eendianness !\u003d TARGET_LITTLE_ENDIAN)"},{"line_number":1349,"context_line":"\t\t\t\t// In place swapping is allowed"},{"line_number":1350,"context_line":"\t\t\t\tbuf_bswap32(code, code, 4);"},{"line_number":1351,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"6cd10133_14765bed","line":1348,"in_reply_to":"771cd2ba_4f34672e","updated":"2025-05-20 13:55:48.000000000","message":"Done","commit_id":"dfdb6dfba94601b848b2691daae33d9b13a074f6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"39d08801a520726d4c8412f383253841dd23bb9e","unresolved":false,"context_lines":[{"line_number":1345,"context_line":"\t\t// Cortex-R4(F?) and Cortex-R5(F?)"},{"line_number":1346,"context_line":"\t\tif (((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc140) ||"},{"line_number":1347,"context_line":"\t\t    ((cortex_a-\u003ecpuid \u0026 0xFFF0) \u003d\u003d 0xc150)) {"},{"line_number":1348,"context_line":"\t\t\tif (target-\u003eendianness !\u003d TARGET_LITTLE_ENDIAN)"},{"line_number":1349,"context_line":"\t\t\t\t// In place swapping is allowed"},{"line_number":1350,"context_line":"\t\t\t\tbuf_bswap32(code, code, 4);"},{"line_number":1351,"context_line":"\t\t}"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"848d9b5c_738815ef","line":1348,"in_reply_to":"771cd2ba_4f34672e","updated":"2025-05-20 13:52:23.000000000","message":"Done","commit_id":"dfdb6dfba94601b848b2691daae33d9b13a074f6"}]}