)]}'
{"src/target/cortex_m.c":[{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"05d6edabe9708acf962efc4d3c751a133c3e4ddb","unresolved":true,"context_lines":[{"line_number":2576,"context_line":"\tuint32_t dscsr;"},{"line_number":2577,"context_line":"\tint retval \u003d target_read_u32(target, DCB_DSCSR, \u0026dscsr);"},{"line_number":2578,"context_line":"\tif (retval !\u003d ERROR_OK) {"},{"line_number":2579,"context_line":"\t\tLOG_ERROR(\"ARMv8M set secure: DSCSR read failed\");"},{"line_number":2580,"context_line":"\t\treturn retval;"},{"line_number":2581,"context_line":"\t}"},{"line_number":2582,"context_line":"\tif (!(dscsr \u0026 DSCSR_CDS)) {"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"21186255_0ea2a366","line":2579,"updated":"2025-06-20 13:28:00.000000000","message":"LOG_TARGET_ERROR()?","commit_id":"6136cd82f0c4b7a220097674be4e4a24e6b7b780"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"95ce6976ea7140d1ca053786e1d2026dfa01ce2e","unresolved":false,"context_lines":[{"line_number":2576,"context_line":"\tuint32_t dscsr;"},{"line_number":2577,"context_line":"\tint retval \u003d target_read_u32(target, DCB_DSCSR, \u0026dscsr);"},{"line_number":2578,"context_line":"\tif (retval !\u003d ERROR_OK) {"},{"line_number":2579,"context_line":"\t\tLOG_ERROR(\"ARMv8M set secure: DSCSR read failed\");"},{"line_number":2580,"context_line":"\t\treturn retval;"},{"line_number":2581,"context_line":"\t}"},{"line_number":2582,"context_line":"\tif (!(dscsr \u0026 DSCSR_CDS)) {"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"a73872ca_6a9cbfc8","line":2579,"in_reply_to":"21186255_0ea2a366","updated":"2025-06-20 15:57:22.000000000","message":"Good point! Expected use is on the flash controlling core (core 0) but logging target name certainly makes no harm.","commit_id":"6136cd82f0c4b7a220097674be4e4a24e6b7b780"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"1ab597fdfdcfb5ce8524b1d352bd897e0364c984","unresolved":false,"context_lines":[{"line_number":2576,"context_line":"\tuint32_t dscsr;"},{"line_number":2577,"context_line":"\tint retval \u003d target_read_u32(target, DCB_DSCSR, \u0026dscsr);"},{"line_number":2578,"context_line":"\tif (retval !\u003d ERROR_OK) {"},{"line_number":2579,"context_line":"\t\tLOG_ERROR(\"ARMv8M set secure: DSCSR read failed\");"},{"line_number":2580,"context_line":"\t\treturn retval;"},{"line_number":2581,"context_line":"\t}"},{"line_number":2582,"context_line":"\tif (!(dscsr \u0026 DSCSR_CDS)) {"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"f204d766_591debfb","line":2579,"in_reply_to":"a73872ca_6a9cbfc8","updated":"2025-06-20 16:03:46.000000000","message":"Thanks","commit_id":"6136cd82f0c4b7a220097674be4e4a24e6b7b780"}],"src/target/cortex_m.h":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"72ef6466302e450b6b683f099a0da0ae8c5d07f3","unresolved":false,"context_lines":[{"line_number":269,"context_line":"\tbool incorrect_halt_erratum;"},{"line_number":270,"context_line":"};"},{"line_number":271,"context_line":""},{"line_number":272,"context_line":"struct cortex_m_saved_security {"},{"line_number":273,"context_line":"\tbool dscsr_dirty;"},{"line_number":274,"context_line":"\tuint32_t dscsr;"},{"line_number":275,"context_line":"\tbool sau_ctrl_dirty;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"70dc30f5_346bab71","line":272,"updated":"2025-06-20 16:56:21.000000000","message":"You need this for a specific use case. That looks fine! \nI\u0027m thinking if it would make sense to generalize this using the registers cache of cortex-m.\nAlso setting a SW breakpoint in RAM could require disabling MPU and SAU. Probably also observing data in memory.\n\nMaybe part of a future development!","commit_id":"70fc7dcc3117fb5722e05c8b359558549d2ee419"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"a3466a8fa2a4d91327c579782109e64ca831da8c","unresolved":false,"context_lines":[{"line_number":269,"context_line":"\tbool incorrect_halt_erratum;"},{"line_number":270,"context_line":"};"},{"line_number":271,"context_line":""},{"line_number":272,"context_line":"struct cortex_m_saved_security {"},{"line_number":273,"context_line":"\tbool dscsr_dirty;"},{"line_number":274,"context_line":"\tuint32_t dscsr;"},{"line_number":275,"context_line":"\tbool sau_ctrl_dirty;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"703f3caf_ea9385d3","line":272,"in_reply_to":"70dc30f5_346bab71","updated":"2025-06-22 10:27:40.000000000","message":"Yes, I considered the register cache too. It seems me too heavy implementation for saving a memory mapped register. On the other hand I would like to extend the working area support to allow saving specified (not allocated) memory area.\nSome flash drivers already need this and abuse allocation at workarea start get area at required address.\nIt could be usable for saving MPU and SAU regs as well.\n\n\u003e Also setting a SW breakpoint in RAM could require disabling MPU and SAU.\n\u003e Probably also observing data in memory.\n\nDon\u0027t think so. IMO the DAP debug access to an ARMv8M with secure profile requires proper setting of AP CSW bits (mainly SPROT) but cannot be blocked by MPU and is not attributed by SAU (unlike accesses originated from CPU)","commit_id":"70fc7dcc3117fb5722e05c8b359558549d2ee419"}]}