)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001410,"name":"Diego Herranz","email":"diegoherranz@diegoherranz.com","username":"diegoherranz"},"change_message_id":"cc68dcc8a26e7e17b5c69c5b3719828e517e2b8a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"6657d5b9_4f319b68","updated":"2025-11-08 14:32:52.000000000","message":"A couple of questions related to SRST. Thanks.","commit_id":"c72f669a4003df9b89bf984a1721c52f4eac766a"}],"tcl/board/nxp/frdm-imx93.cfg":[{"author":{"_account_id":1001410,"name":"Diego Herranz","email":"diegoherranz@diegoherranz.com","username":"diegoherranz"},"change_message_id":"cc68dcc8a26e7e17b5c69c5b3719828e517e2b8a","unresolved":true,"context_lines":[{"line_number":6,"context_line":"transport select swd"},{"line_number":7,"context_line":""},{"line_number":8,"context_line":"# default JTAG configuration has only SRST and no TRST"},{"line_number":9,"context_line":"reset_config srst_only srst_push_pull"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"# delay after SRST goes inactive"},{"line_number":12,"context_line":"adapter srst delay 70"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"549c7433_7a18a7b3","line":9,"updated":"2025-11-08 14:32:52.000000000","message":"What signal on the board would this SRST represent? Is it SYS_nRST (on P19)?\nIf so, is it really usable, given that it is an input to the PMIC which produces a cold reboot (rails are powered off and then on again)? Or is it meant to be another signal?","commit_id":"c72f669a4003df9b89bf984a1721c52f4eac766a"},{"author":{"_account_id":1001410,"name":"Diego Herranz","email":"diegoherranz@diegoherranz.com","username":"diegoherranz"},"change_message_id":"cc68dcc8a26e7e17b5c69c5b3719828e517e2b8a","unresolved":true,"context_lines":[{"line_number":9,"context_line":"reset_config srst_only srst_push_pull"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"# delay after SRST goes inactive"},{"line_number":12,"context_line":"adapter srst delay 70"},{"line_number":13,"context_line":""},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"# board has an i.MX93 with 2 Cortex-A55 cores"}],"source_content_type":"text/x-ttcn-cfg","patch_set":2,"id":"d9a500b5_89f6cd9e","line":12,"updated":"2025-11-08 14:32:52.000000000","message":"Where does the 70 ms come from? Honest question to understand it.","commit_id":"c72f669a4003df9b89bf984a1721c52f4eac766a"}]}