)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"change_message_id":"4b4fb52b4b589823324c1d3edcc7ae4a69c23358","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"tcl/target/stm32u3x: fix voltage scale before flashing from gdb"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"The config files of Cortex-M33 based devices (L5, U5, U3) intentionally"},{"line_number":10,"context_line":"dropped \u0027reset init\u0027 from the \u0027gdb-flash-erase-start\u0027 event to allow"},{"line_number":11,"context_line":"programming of unsecure part of flash in 0.5 RDP level."},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"STM32U3 needs to set voltage range 1 before flash programming,"},{"line_number":14,"context_line":"which was issued in the \u0027reset-init\u0027 event only before this patch."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"dc68fc97_c1dd880b","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":55},"updated":"2025-07-28 09:37:53.000000000","message":"I see it was introduced for L5 with c9d40366ad55ea3a83f2ff438aab1e62da653169 but I can not understand how it was supposed to guarantee predictable identical target state prior to actual flashing. It\u0027s important because end-user expects `load` in GDB to work at any moment all the same and for that the target must have all interrupts disabled, running from the clock source as assumed by the flash driver author etc. The default gdb-flash-erase-start handling was added in 207237b92005d604b75ff5280042a6c286a685f8 .","commit_id":"811551ecf124de8e8e859630cc26a694dfa84f9a"},{"author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"change_message_id":"890a6fec6327c9ff6817d2dd6bc10b12f5072a01","unresolved":false,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"tcl/target/stm32u3x: fix voltage scale before flashing from gdb"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"The config files of Cortex-M33 based devices (L5, U5, U3) intentionally"},{"line_number":10,"context_line":"dropped \u0027reset init\u0027 from the \u0027gdb-flash-erase-start\u0027 event to allow"},{"line_number":11,"context_line":"programming of unsecure part of flash in 0.5 RDP level."},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"STM32U3 needs to set voltage range 1 before flash programming,"},{"line_number":14,"context_line":"which was issued in the \u0027reset-init\u0027 event only before this patch."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"62e9785b_5bc35fbe","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":55},"in_reply_to":"c715e84b_dfdada81","updated":"2025-07-28 10:49:46.000000000","message":"I see, thank you for the detailed clarification! I\u0027m not sure about the interrupts, I have an impression many years ago I had a problem with them affecting flashing on another Cortex-M target but I might be mistaken, it might have been integrated watchdog too, can\u0027t remember.","commit_id":"811551ecf124de8e8e859630cc26a694dfa84f9a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"125b95bd5bd0ceb530bdef3f28582e53eb049bee","unresolved":true,"context_lines":[{"line_number":6,"context_line":""},{"line_number":7,"context_line":"tcl/target/stm32u3x: fix voltage scale before flashing from gdb"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"The config files of Cortex-M33 based devices (L5, U5, U3) intentionally"},{"line_number":10,"context_line":"dropped \u0027reset init\u0027 from the \u0027gdb-flash-erase-start\u0027 event to allow"},{"line_number":11,"context_line":"programming of unsecure part of flash in 0.5 RDP level."},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"STM32U3 needs to set voltage range 1 before flash programming,"},{"line_number":14,"context_line":"which was issued in the \u0027reset-init\u0027 event only before this patch."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":1,"id":"c715e84b_dfdada81","line":11,"range":{"start_line":9,"start_character":0,"end_line":11,"end_character":55},"in_reply_to":"dc68fc97_c1dd880b","updated":"2025-07-28 10:35:29.000000000","message":"Good point, Paul!\nUnfortunately there is no way to guarantee a predictable target state in RDP level 0.5 as debugging of the secure code is blocked and therefore OpenOCD can debug halt as late as after the transition to non-secure state. The secure code must be designed to allow non-secure flash programming.\nAnyway the `gdb-flash-erase-start` event may check if TrustZone is enabled and what is RDP level and omit `reset-init` only if the security state does not allow to use it. It could be a follow-up patch, this one is needed at least in RDP 0.5 state.\nFYI the flash programming of U3 does not have many prerequisites except the voltage range, so I successfully used GDB `load` as an ordinary end-user many times with this patch (no clock dependency, interrupts are masked by setting PRIMASK reg on programming algo start - see `cortex_m_restore_one()`). Of course some other things depend on the application, e.g. watchdog etc...","commit_id":"811551ecf124de8e8e859630cc26a694dfa84f9a"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"177c39ec2aeae08337f5e49d9988ab07a68112e0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"9a484f3b_267be422","updated":"2025-11-06 08:31:36.000000000","message":"Ahmed, Tarek, could you please review the patch?","commit_id":"811551ecf124de8e8e859630cc26a694dfa84f9a"},{"author":{"_account_id":1000160,"name":"Paul Fertser","email":"fercerpav@gmail.com","username":"pfertser"},"change_message_id":"4b4fb52b4b589823324c1d3edcc7ae4a69c23358","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"7ba82440_0dec655f","updated":"2025-07-28 09:37:53.000000000","message":"Hello Tomas,\n\nPlease see inline, I\u0027m not sure if the target gets actually reset with the code as it currently is, and if it does probably a comment to the corresponding Tcl command would be helpful.","commit_id":"811551ecf124de8e8e859630cc26a694dfa84f9a"},{"author":{"_account_id":1002386,"name":"Ahmed Haoues","email":"ahmed.haoues@st.com","username":"ahmed-haoues"},"change_message_id":"612b6d732b75a17f627f36591d597ad313284a02","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"5e3e8a56_f15bd218","updated":"2026-07-02 07:48:22.000000000","message":"Thank you for this useful patch","commit_id":"811551ecf124de8e8e859630cc26a694dfa84f9a"}]}