)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"bfe881d5a65eeb5972cf5ac639abe4a0ecd10691","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"e02470a3_663b9397","updated":"2025-08-21 09:46:33.000000000","message":"Looks like newly written code. What\u0027s the reason for not following the coding style? For example, single-line comments with `/* .. */`.","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"d11fc365eec8854db74185433deae39715214919","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"37e4b98f_3b3bf0b0","in_reply_to":"0495c5f3_95ae7f79","updated":"2025-08-21 10:02:42.000000000","message":"Yes, the naming rule to split consecutive words (see examples).","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"216d4333ba9285d5d2b145eee1c6de7f5ca897c1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"aaf679cf_627c9653","in_reply_to":"37e4b98f_3b3bf0b0","updated":"2025-08-21 12:43:18.000000000","message":"Done","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"8b7464de5fbe597362932c9bc46a8234b27ee94d","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"0495c5f3_95ae7f79","in_reply_to":"e02470a3_663b9397","updated":"2025-08-21 09:55:41.000000000","message":"dumb brain and following the similar code from other architecture.\nFrom you comment there is something else apart the single-line comment ... what?","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"af44897d7b06e0afa347dcdebba50fabe37c386b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"e8d89983_d3aa2f34","updated":"2025-08-23 10:05:08.000000000","message":"Tested with Atmel SAMV71 (Cortex-M7 r0p1) and STM32H7A3 (Cortex-M7 r1p1).\nThe cache parameters are reported correctly, breakpoints in RAM work (tested both non-cached ITCM RAM, where breakpoints work even without this patch, and AXI RAM, where cache handling is necessary).\n\nJust spotted time ineffective read of `CCR` register.","commit_id":"4b1c7f83256f5c66989dbba3391cdbaa0832a15b"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"82bf82456faf573672deb1cfd3171e4770aa4a68","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"c60fa1ea_678627b5","updated":"2025-08-21 13:06:36.000000000","message":"Thanks, patch works on hardware.","commit_id":"4b1c7f83256f5c66989dbba3391cdbaa0832a15b"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"cba49e694f4287e37df06db1234c9f9e5f2720f0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"ebf85b04_c0462fb2","updated":"2025-09-17 20:55:26.000000000","message":"Thanks.\nRe-tested with STM32H7A3 (Cortex-M7 r1p1).\nJust a question about checking target halted.","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"28b288cbbf193998b48012fb553a3e069ceef662","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"1deb7966_17605591","updated":"2025-09-19 09:43:57.000000000","message":"Sorry, upload of patchset 6 was not intentional. Will reload patchset 5","commit_id":"116a17794606dc0a66212b6b72f7e1be58ee8be3"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f9b03c6bdaa100034fbbbd4e1b3922dee17e4247","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"00bb1eaa_1fe361a2","updated":"2025-09-19 09:51:28.000000000","message":"Patchset 7 is reloaded patchset 5 without changes. Sorry again","commit_id":"8d45b39cf59ffa6fc2921d08bcfcf1e8befc4cc7"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0c9b2c3c9df60993580e10ca4a8533da322f1e53","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"9318b1f6_9ba24844","in_reply_to":"00bb1eaa_1fe361a2","updated":"2025-09-19 12:09:17.000000000","message":"No problem","commit_id":"8d45b39cf59ffa6fc2921d08bcfcf1e8befc4cc7"}],"src/target/armv7m_cache.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"cba49e694f4287e37df06db1234c9f9e5f2720f0","unresolved":true,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"bf6e5b92_fddc9838","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"updated":"2025-09-17 20:55:26.000000000","message":"Is this necessary?\nWhen you want to flush cache and keep it flushed, then you have to halt the target.\nBut for setting breakpoint it is perfectly okay to do it while CPU is running.\nAnd the running program just gets slowed down a little bit. Is there other source of conflict I\u0027m not aware of?","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"2e1091f6c0f3069f31bc84caf5dd4357133307ad","unresolved":false,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"3004aa46_57e0ef75","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"in_reply_to":"252a2a02_a765c427","updated":"2025-09-23 05:41:06.000000000","message":"Nice! Thanks a lot.\nRe-tested on STM32H7A3, works as expected","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"e0083bb61972b740b5fd2dca361e70d5310641cb","unresolved":true,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"b09e630a_b7d167d5","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"in_reply_to":"4ccc932c_4faf7e5b","updated":"2025-09-19 13:48:19.000000000","message":"There is also some different behavior due to cacheability setting in MPU (mem protection unit), so configuring HPROT should not be enough to allow dropping 1).\nI don\u0027t know what happen if MPU forces CPU to go non-cacheable and HPROT forces the write in cache. Cannot get such info from ARM doc. The HPROT is documented in IHI0031 (ADIv5) only, not in DDI0553 armv8m.\n\nAnyway, we are talking about the CPU that is writing in the same cache line that contains some code on which we apply a BP. So quite exotic use case.\nHaving the CPU loading from .text is normal (see load of `literals`), but writing it is quite odd.\n\nWhat you think could be the best approach?\nDropping the \u0027halted\u0027 requirement and wait for some odd case reported by users? Or being over cautious?","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"08f8df9a42f4cf7fb6c3d03b6f9dabef2973f6f2","unresolved":true,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"252a2a02_a765c427","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"in_reply_to":"6a333087_db11e651","updated":"2025-09-22 15:15:25.000000000","message":"Quite some rework.\nThe cache info that we get by reading banked register CCR is only related to the cache in the current state of the CPU (secure or non-secure).\nI could add some extra code to retrieve both CCR and CCR_NS (through DSCSR.SBRSEL), but it doesn\u0027t make too much sense as the cache maintenance registers are not banked. Much easier to simply flush/invalidate every time on devices with cache.\nThe check for halted is removed. No issues with GDB as we will always run BP add/remove on halted cores. The risk of having issues on telnet interface is minimal.","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"589bffba2325cdd25132a7b192aed9854bc9ebf0","unresolved":true,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"6a333087_db11e651","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"in_reply_to":"99978819_a354a811","updated":"2025-09-22 07:37:28.000000000","message":"I though about a 4 bytes BP not aligned at 4 bytes. It could go in two consecutive cache lines (half at the end of first line, half at the beginning of next line). The sync from D-Cache to I-Cache would be much more tricky.\nBut OpenOCD only supports 2 bytes BP on Cortex-M, so not possible now. See https://review.openocd.org/2312 . I will provide some comment on that code\n\nAnd I will send a new version with a warning message","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"6c922660368c7942dfffad6981629b0b903a531d","unresolved":false,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"4ccc932c_4faf7e5b","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"in_reply_to":"9cb6bd0e_0eefc2ac","updated":"2025-09-19 13:01:17.000000000","message":"Thanks for explanation!\nIf I understand correctly, if we were sure that data write goes to the cache (as requested by setting HPROT[3] in apcsw in the typical C-M7 config) we could leave out 1) and setting bp would be risk-free even while CPU is running.\n\nOtherwise the risk is questionable, as some apps may easily misfit RAM based functions with some frequently modified data to one cache line.","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"251953d2baace313c45cb60ce8f9f8939034e717","unresolved":true,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"99978819_a354a811","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"in_reply_to":"b09e630a_b7d167d5","updated":"2025-09-19 14:40:15.000000000","message":"\u003e Anyway, we are talking about the CPU that is writing in the same cache line that contains some code on which we apply a BP. So quite exotic use case.\n\u003e Having the CPU loading from .text is normal (see load of `literals`), but writing it is quite odd.\n\nI don\u0027t assume .text and written data could go to the same cache line.\nThe more risky case is an app with .text in flash has some fast functions relocated to .ramfunc (or whatever is called) segment which is next to .data segment.\n \n\u003e What you think could be the best approach?\n\u003e Dropping the \u0027halted\u0027 requirement and wait for some odd case reported by users? Or being over cautious?\n\nNo idea. Emit just a warning if not halted?\nAnyway setting (but not clearing) of soft breakpoints is blocked while target runs. It have been so for long time maybe always. Not quite sure if it is worth to change this old behaviour. If we enable it, the use-case of it would be very rare anyway.","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0c9b2c3c9df60993580e10ca4a8533da322f1e53","unresolved":true,"context_lines":[{"line_number":198,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":199,"context_line":"\t\treturn ERROR_OK;"},{"line_number":200,"context_line":""},{"line_number":201,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":202,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":203,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":204,"context_line":"\t}"},{"line_number":205,"context_line":""},{"line_number":206,"context_line":"\tif (!armv7m-\u003earmv7m_cache.d_u_cache_enabled)"},{"line_number":207,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"9cb6bd0e_0eefc2ac","line":204,"range":{"start_line":201,"start_character":1,"end_line":204,"end_character":2},"in_reply_to":"bf6e5b92_fddc9838","updated":"2025-09-19 12:09:17.000000000","message":"It is due to a (low probability) race condition.\nWhile set/remove the BP the sequence is:\n1) clean and invalidate data cache\n2) write at BP address (BP instruction or back the real instruction)\n3) again clean and invalidate data cache\n4) invalidate instruction cache\n\nDepending on CSW:HPROT[3:2] and how they are connected in the SoC, the write in 2) can go in cache or in memory or both in cache and in memory.\nWith CPU halted, the sequence above guarantees that the instruction goes in memory, so after 4) the fetch recovers it.\n\nBut if the CPU is running, it could break the sync.\nImagine if between 1) and 2) the CPU writes in memory, so now the cache holds the latest value. Then 2) write in memory bypassing the cache. 3) overwrites the memory with the cache line modified by the CPU. The BP is lost!\n\nWe could consider that this sequence is so low probability that we can ignore it.\nOr we could assume that CSW:HPROT works reliably and uniformly on every SoC, so by a proper configuration of CSW the issue never happens.\nShould we take this risk?","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"cba49e694f4287e37df06db1234c9f9e5f2720f0","unresolved":true,"context_lines":[{"line_number":228,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":229,"context_line":"\t\treturn ERROR_OK;"},{"line_number":230,"context_line":""},{"line_number":231,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":232,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":233,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":234,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"ed2fe3d3_d906c395","line":231,"updated":"2025-09-17 20:55:26.000000000","message":"Same as above","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0c9b2c3c9df60993580e10ca4a8533da322f1e53","unresolved":false,"context_lines":[{"line_number":228,"context_line":"\tif (!cache-\u003einfo_valid)"},{"line_number":229,"context_line":"\t\treturn ERROR_OK;"},{"line_number":230,"context_line":""},{"line_number":231,"context_line":"\tif (target-\u003estate !\u003d TARGET_HALTED) {"},{"line_number":232,"context_line":"\t\tLOG_TARGET_ERROR(target, \"not halted\");"},{"line_number":233,"context_line":"\t\treturn ERROR_TARGET_NOT_HALTED;"},{"line_number":234,"context_line":"\t}"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"a9a1adfa_80a6b063","line":231,"in_reply_to":"ed2fe3d3_d906c395","updated":"2025-09-19 12:09:17.000000000","message":"reply as above","commit_id":"8781bda3dbda048b94b7f6811f2d4b91c8026178"}],"src/target/armv7m_cache.h":[{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"d11fc365eec8854db74185433deae39715214919","unresolved":true,"context_lines":[{"line_number":19,"context_line":"\t/*  cache dimensioning */"},{"line_number":20,"context_line":"\tuint32_t linelen;"},{"line_number":21,"context_line":"\tuint32_t associativity;"},{"line_number":22,"context_line":"\tuint32_t nsets;"},{"line_number":23,"context_line":"\tuint32_t cachesize;"},{"line_number":24,"context_line":"\t/* info for set way operation on cache */"},{"line_number":25,"context_line":"\tuint32_t index;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"7b50db23_0423bf80","line":22,"updated":"2025-08-21 10:02:42.000000000","message":"`n_sets` or `num_sets`","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"216d4333ba9285d5d2b145eee1c6de7f5ca897c1","unresolved":false,"context_lines":[{"line_number":19,"context_line":"\t/*  cache dimensioning */"},{"line_number":20,"context_line":"\tuint32_t linelen;"},{"line_number":21,"context_line":"\tuint32_t associativity;"},{"line_number":22,"context_line":"\tuint32_t nsets;"},{"line_number":23,"context_line":"\tuint32_t cachesize;"},{"line_number":24,"context_line":"\t/* info for set way operation on cache */"},{"line_number":25,"context_line":"\tuint32_t index;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"37952a77_6407b819","line":22,"in_reply_to":"7b50db23_0423bf80","updated":"2025-08-21 12:43:18.000000000","message":"Done","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"d11fc365eec8854db74185433deae39715214919","unresolved":true,"context_lines":[{"line_number":20,"context_line":"\tuint32_t linelen;"},{"line_number":21,"context_line":"\tuint32_t associativity;"},{"line_number":22,"context_line":"\tuint32_t nsets;"},{"line_number":23,"context_line":"\tuint32_t cachesize;"},{"line_number":24,"context_line":"\t/* info for set way operation on cache */"},{"line_number":25,"context_line":"\tuint32_t index;"},{"line_number":26,"context_line":"\tuint32_t index_shift;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"7e28a9ee_9fc6da62","line":23,"updated":"2025-08-21 10:02:42.000000000","message":"`cache_size`","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"9f1b456dde16ae1376599208d384f9fd200768c1","unresolved":true,"context_lines":[{"line_number":20,"context_line":"\tuint32_t linelen;"},{"line_number":21,"context_line":"\tuint32_t associativity;"},{"line_number":22,"context_line":"\tuint32_t nsets;"},{"line_number":23,"context_line":"\tuint32_t cachesize;"},{"line_number":24,"context_line":"\t/* info for set way operation on cache */"},{"line_number":25,"context_line":"\tuint32_t index;"},{"line_number":26,"context_line":"\tuint32_t index_shift;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"bc96e61e_f79c8299","line":23,"in_reply_to":"7e28a9ee_9fc6da62","updated":"2025-08-21 10:05:50.000000000","message":"this struct is copied from the other archs.\nActually there is no common code, so we can diverge!\nWill send a v3","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"216d4333ba9285d5d2b145eee1c6de7f5ca897c1","unresolved":false,"context_lines":[{"line_number":20,"context_line":"\tuint32_t linelen;"},{"line_number":21,"context_line":"\tuint32_t associativity;"},{"line_number":22,"context_line":"\tuint32_t nsets;"},{"line_number":23,"context_line":"\tuint32_t cachesize;"},{"line_number":24,"context_line":"\t/* info for set way operation on cache */"},{"line_number":25,"context_line":"\tuint32_t index;"},{"line_number":26,"context_line":"\tuint32_t index_shift;"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"0ade4e8c_759ce82f","line":23,"in_reply_to":"bc96e61e_f79c8299","updated":"2025-08-21 12:43:18.000000000","message":"Done","commit_id":"7c49b5df437223028d9890def2dfd9b5087d885a"}],"src/target/cortex_m.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"af44897d7b06e0afa347dcdebba50fabe37c386b","unresolved":true,"context_lines":[{"line_number":930,"context_line":""},{"line_number":931,"context_line":"\tif (armv7m-\u003earmv7m_cache.info_valid) {"},{"line_number":932,"context_line":"\t\tuint32_t ccr;"},{"line_number":933,"context_line":"\t\tretval \u003d target_read_u32(target, CCR, \u0026ccr);"},{"line_number":934,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":935,"context_line":"\t\t\treturn retval;"},{"line_number":936,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"0e17a7b7_acda200f","line":933,"range":{"start_line":933,"start_character":11,"end_line":933,"end_character":26},"updated":"2025-08-23 10:05:08.000000000","message":"Could you please use non-atomic `mem_ap_read_u32()` instead of `target_read_u32()` similarly to reading the security state from `DCB_DSCSR` in case of ARM_ARCH_V8M.\n`cortex_m_debug_entry()` should be kept as fast as possible wrt stepping speed and the additional adapter turn-around delay doesn\u0027t seem necessary here.","commit_id":"4b1c7f83256f5c66989dbba3391cdbaa0832a15b"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"6d3894357869c69314a2260d97051fae5e5853eb","unresolved":false,"context_lines":[{"line_number":930,"context_line":""},{"line_number":931,"context_line":"\tif (armv7m-\u003earmv7m_cache.info_valid) {"},{"line_number":932,"context_line":"\t\tuint32_t ccr;"},{"line_number":933,"context_line":"\t\tretval \u003d target_read_u32(target, CCR, \u0026ccr);"},{"line_number":934,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":935,"context_line":"\t\t\treturn retval;"},{"line_number":936,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"5e75103c_5e79dca1","line":933,"range":{"start_line":933,"start_character":11,"end_line":933,"end_character":26},"in_reply_to":"0e17a7b7_acda200f","updated":"2025-09-16 02:06:59.000000000","message":"You are right, the implementation was not efficient at all!\nIt should be way better now","commit_id":"4b1c7f83256f5c66989dbba3391cdbaa0832a15b"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"82bf82456faf573672deb1cfd3171e4770aa4a68","unresolved":true,"context_lines":[{"line_number":3316,"context_line":"\t\t.usage \u003d \"[\u0027sysresetreq\u0027|\u0027vectreset\u0027]\","},{"line_number":3317,"context_line":"\t},"},{"line_number":3318,"context_line":"\t{"},{"line_number":3319,"context_line":"\t\t.name \u003d \"cache_info\","},{"line_number":3320,"context_line":"\t\t.handler \u003d handle_cortex_m_cache_info_command,"},{"line_number":3321,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":3322,"context_line":"\t\t.help \u003d \"display information about target caches\","}],"source_content_type":"text/x-csrc","patch_set":3,"id":"1fb1adb1_313f8188","line":3319,"updated":"2025-08-21 13:06:36.000000000","message":"Just to avoid another bunch of deprecated commands in the future. Do we expect other \"cache\" commands? If yes, I would prefer to have \"cache\" command group.","commit_id":"4b1c7f83256f5c66989dbba3391cdbaa0832a15b"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"b81a776d1c5e603c8d09f6a74865996db45ecf15","unresolved":false,"context_lines":[{"line_number":3316,"context_line":"\t\t.usage \u003d \"[\u0027sysresetreq\u0027|\u0027vectreset\u0027]\","},{"line_number":3317,"context_line":"\t},"},{"line_number":3318,"context_line":"\t{"},{"line_number":3319,"context_line":"\t\t.name \u003d \"cache_info\","},{"line_number":3320,"context_line":"\t\t.handler \u003d handle_cortex_m_cache_info_command,"},{"line_number":3321,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":3322,"context_line":"\t\t.help \u003d \"display information about target caches\","}],"source_content_type":"text/x-csrc","patch_set":3,"id":"e238e6de_6b0273dd","line":3319,"in_reply_to":"1fb1adb1_313f8188","updated":"2025-08-21 13:50:26.000000000","message":"There is a kind of anarchy on the name of cache management commands. A consolidation/standardization is welcome.\n\nFor the moment I would keep this common \"cache_info\", present on 5 other arch. I don\u0027t expect other cache commands for Cortex-M, but if we decide for standard names we could add them here too, even if not strictly required.\n\nThe strangest arch is Cortex-A. It has commands \"cortex_a cache_info\", \"cache l1 info\" and \"cache l2x info\".","commit_id":"4b1c7f83256f5c66989dbba3391cdbaa0832a15b"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"8aa3651483ede5376a4a2367771efd0caa3a0da3","unresolved":false,"context_lines":[{"line_number":3316,"context_line":"\t\t.usage \u003d \"[\u0027sysresetreq\u0027|\u0027vectreset\u0027]\","},{"line_number":3317,"context_line":"\t},"},{"line_number":3318,"context_line":"\t{"},{"line_number":3319,"context_line":"\t\t.name \u003d \"cache_info\","},{"line_number":3320,"context_line":"\t\t.handler \u003d handle_cortex_m_cache_info_command,"},{"line_number":3321,"context_line":"\t\t.mode \u003d COMMAND_EXEC,"},{"line_number":3322,"context_line":"\t\t.help \u003d \"display information about target caches\","}],"source_content_type":"text/x-csrc","patch_set":3,"id":"e1e2924f_3d50fdb9","line":3319,"in_reply_to":"e238e6de_6b0273dd","updated":"2025-08-21 14:01:20.000000000","message":"Okay, makes sense. Thanks!","commit_id":"4b1c7f83256f5c66989dbba3391cdbaa0832a15b"}]}