)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"9c9c0142ff98a5fd1dc8042fedb591d83948a4b0","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"cfc5c0c8_b97e62f1","updated":"2025-09-15 10:00:49.000000000","message":"Can this even happen? as target_add_breakpoint() already checks that the target is halted for software breakpoints.","commit_id":"c4997dcb8fe844fe451fd8e170379579250c8cfb"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"334881f4270ddd46e34d3949d44f46243c42a4fc","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"9c0782b9_433aabe3","in_reply_to":"52f64196_1b6ae487","updated":"2025-09-15 16:02:00.000000000","message":"Oh shit, spike code is correct. The crap is ours. Or better said yours, RISC-V fork guys!\nI quickly created openocd.cfg from\nhttps://review.openocd.org/c/openocd/+/8893/comments/538fe9c9_624db61f\nEvgeniy\u0027s comment from Aug 12. There are two targets defined:\n```\ntarget create c0 riscv -chain-position riscv.cpu -rtos hwthread\ntarget create c1 riscv -chain-position riscv.cpu -rtos hwthread\ntarget smp c0 c1\n```\nbut `-coreid` parameter is missing. Both upstream and RISC-V fork OpenOCD runs the config happily without logging an error but the hart selecting does not work - both harts have same index 0!!!\nPlease add a check for re-using the same core id on same DM!","commit_id":"c4997dcb8fe844fe451fd8e170379579250c8cfb"},{"author":{"_account_id":1002143,"name":"Marek Vrbka","email":"marek.vrbka@codasip.com","username":"MarekVCodasip"},"change_message_id":"cd335208f5bb5ba896a7cd61922942faff10043f","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"ec0af3b6_d4eb05df","in_reply_to":"9c0782b9_433aabe3","updated":"2025-09-17 13:47:14.000000000","message":"I agree, there should be checks for `coreid`. Created an issue for it: https://github.com/riscv-collab/riscv-openocd/issues/1293\n\nThat being said, this change checking for software breakpoints should ultimately go into the RISC-V fork","commit_id":"c4997dcb8fe844fe451fd8e170379579250c8cfb"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"4631ae14b1f673a48f4b5771b741a01c93d639eb","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"52f64196_1b6ae487","in_reply_to":"cfc5c0c8_b97e62f1","updated":"2025-09-15 14:27:47.000000000","message":"Yes, good point. We need to remove the check from `target_add_breakpoint()` (some targets like cortex-m have no problem setting soft bp while running, maybe it could be done even on RISC-V with sba).\nUnfortunately it also requires to add the halted test to all other targets or finally implement target capability flags.\n\nI\u0027m just struggling to simulate this case on spike. Unfortunately it looks like spike has a problem in controlling availability of harts by writing to DM_CUSTOM (bit 0 controls both hart 0 and 1, bit 1 does nothing)","commit_id":"c4997dcb8fe844fe451fd8e170379579250c8cfb"}]}