)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"aae72155a785277237ce158326d0d9cd9c10ec63","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"3b9ec8cb_795849a4","updated":"2025-10-24 14:40:28.000000000","message":"I\u0027m afraid supporting these on architectures like RISC-V will be problematic.\nIn general on RISC-V targets, there is no way to discover whether a feature is available until you try to use it.\nMoreover, the spec allows for a target that e.g. can perform memory accesses on a running target but only when the access is naturally aligned (in general, ability to access memory can depend on memory address). Therefore, discovering a capability like \"can the memory be accessed on a running target\" is practically impossible.\n\nMaybe we can:\n1. Make the capabilities three-state (yes/no/unknown).\n2. Allow the user to specify capabilities during target configuration (maybe something like `\u003ctargetname\u003e configure -capability ...`?).","commit_id":"680aac3515a09cb6a7d18ad191989046443762de"}],"src/target/target.h":[{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"aae72155a785277237ce158326d0d9cd9c10ec63","unresolved":true,"context_lines":[{"line_number":88,"context_line":""},{"line_number":89,"context_line":"#define TARGET_CAPAB_MEM_READ_WHILE_RUNNING\t\tBIT(0)"},{"line_number":90,"context_line":"#define TARGET_CAPAB_MEM_WRITE_WHILE_RUNNING\tBIT(1)"},{"line_number":91,"context_line":"#define TARGET_CAPAB_BP_WP_MANIP_AT_ANY_STATE\tBIT(2)"},{"line_number":92,"context_line":""},{"line_number":93,"context_line":"struct working_area {"},{"line_number":94,"context_line":"\ttarget_addr_t address;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"8a1b1d75_3e9fdb3f","line":91,"updated":"2025-10-24 14:40:28.000000000","message":"Tomas, I\u0027m a bit confused what this actually entails.\nAFAIU, setting a software breakpoint involves reading and writing memory. If for some reason the memory is modified in between the read and the write this will result in a hard-to-catch bug.\nThe same is true for some architectures for HW breakpoints: e.g. on RISC-V we need to first modify `tselect` register and then write `tdata1` to disable a HW breakpoint. `tselect` can be modified by SW running on the target in-between these operation.\n\n* Maybe the capability can be further detailed by splitting it into multiple bits (read/write, SW/HW, watchpoint/brakpoint)?\n* Could you add a comment describing the meaning of these capabilities?","commit_id":"680aac3515a09cb6a7d18ad191989046443762de"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"b2bba459d805fa35fae9c8855fcdb0c9c4087efe","unresolved":true,"context_lines":[{"line_number":707,"context_line":" */"},{"line_number":708,"context_line":"static inline bool target_has_capab(struct target *target, unsigned int capab)"},{"line_number":709,"context_line":"{"},{"line_number":710,"context_line":"\treturn (target_get_capab(target) \u0026 capab) \u003d\u003d capab;"},{"line_number":711,"context_line":"}"},{"line_number":712,"context_line":""},{"line_number":713,"context_line":"/** Return the *name* of this targets current state */"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"486bb685_020f05e6","line":710,"updated":"2025-10-21 20:32:33.000000000","message":"Antonio, just for curiosity:\ncheckpatch detected false error that space should not be before a cast?!\nand proposed fix:\n`return (target_get_capab(target)\u0026 capab) \u003d\u003d capab;`\nUnfortunately I\u0027m not able to reproduce the problem again.","commit_id":"680aac3515a09cb6a7d18ad191989046443762de"}],"src/target/target_type.h":[{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"aae72155a785277237ce158326d0d9cd9c10ec63","unresolved":true,"context_lines":[{"line_number":308,"context_line":""},{"line_number":309,"context_line":"\t/* Return target capabilities as TARGET_CAPAB_ bits."},{"line_number":310,"context_line":"\t * Assume zero return (no optional capabilities) if not implemented */"},{"line_number":311,"context_line":"\tunsigned int (*get_capab)(struct target *target);"},{"line_number":312,"context_line":"};"},{"line_number":313,"context_line":""},{"line_number":314,"context_line":"// Keep in alphabetic order this list of targets"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"dd61032f_1360677b","line":311,"updated":"2025-10-24 14:40:28.000000000","message":"Is the expectation for these capabilities to be available immediately after examine? Can the capabilities change?","commit_id":"680aac3515a09cb6a7d18ad191989046443762de"}]}