)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"19792920e4bb1551f68f3ee4aa174c78d1af175e","unresolved":true,"context_lines":[{"line_number":4,"context_line":"Commit:     Tomas Vanek \u003cvanekt@fbl.cz\u003e"},{"line_number":5,"context_line":"CommitDate: 2025-10-23 08:56:25 +0200"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"rtos: server: target: ask the RTOS which target to set swbp on."},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Checkpatch-ignore: UNKNOWN_COMMIT_ID"},{"line_number":10,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"1f202fcd_06f35b8e","line":7,"updated":"2025-10-25 14:35:29.000000000","message":"Confusing title. What about:\nserver: gdb: with hwthread, set SW bp on current thread\u0027s target","commit_id":"a28452ea4afd80a1698cb59ce87f0c2aa464b0b7"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"677a90d907e8bd9faf7a928d2f477708b211f5e3","unresolved":true,"context_lines":[{"line_number":4,"context_line":"Commit:     Tomas Vanek \u003cvanekt@fbl.cz\u003e"},{"line_number":5,"context_line":"CommitDate: 2025-10-23 08:56:25 +0200"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"rtos: server: target: ask the RTOS which target to set swbp on."},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Checkpatch-ignore: UNKNOWN_COMMIT_ID"},{"line_number":10,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"454e053e_2982ed1b","line":7,"in_reply_to":"1f202fcd_06f35b8e","updated":"2025-11-07 12:20:19.000000000","message":"Honestly I don\u0027t see much difference. Let\u0027s keep the title used in riscv-collab.","commit_id":"a28452ea4afd80a1698cb59ce87f0c2aa464b0b7"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"19792920e4bb1551f68f3ee4aa174c78d1af175e","unresolved":true,"context_lines":[{"line_number":10,"context_line":""},{"line_number":11,"context_line":"This is the result of squashing two commits from RISC-V OpenOCD, the"},{"line_number":12,"context_line":"first one is"},{"line_number":13,"context_line":"commit 52ca5d198e3b (\"Ask the RTOS which target to set swbp on. (#673)\")"},{"line_number":14,"context_line":"and the second one is"},{"line_number":15,"context_line":"commit 8ae41e86e15d (\"Fix breackpoint_add for rtos swbp (#734)\")."},{"line_number":16,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"520d79f4_413d77b1","line":13,"updated":"2025-10-25 14:35:29.000000000","message":"this creates a clickable link in gerrit and in gitk, but the link is not functional because it refers to another repository.\nAdd below, together with the signed-off\n```\nLink: https://github.com/riscv-collab/riscv-openocd/commit/52ca5d198e3b [1]\nLink: https://github.com/riscv-collab/riscv-openocd/commit/8ae41e86e15d [2]\n```\ndrop UNKNOWN_COMMIT_ID and here write something like:\n```\nThis is the result of squashing two commits from RISC-V OpenOCD\n- [1] (\"Ask the RTOS which target to set swbp on. (#673)\");\n- [2] (\"Fix breackpoint_add for rtos swbp (#734)\").\n```","commit_id":"a28452ea4afd80a1698cb59ce87f0c2aa464b0b7"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"677a90d907e8bd9faf7a928d2f477708b211f5e3","unresolved":false,"context_lines":[{"line_number":10,"context_line":""},{"line_number":11,"context_line":"This is the result of squashing two commits from RISC-V OpenOCD, the"},{"line_number":12,"context_line":"first one is"},{"line_number":13,"context_line":"commit 52ca5d198e3b (\"Ask the RTOS which target to set swbp on. (#673)\")"},{"line_number":14,"context_line":"and the second one is"},{"line_number":15,"context_line":"commit 8ae41e86e15d (\"Fix breackpoint_add for rtos swbp (#734)\")."},{"line_number":16,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"27cdfe1f_4d2a32c7","line":13,"in_reply_to":"520d79f4_413d77b1","updated":"2025-11-07 12:20:19.000000000","message":"Done","commit_id":"a28452ea4afd80a1698cb59ce87f0c2aa464b0b7"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"19792920e4bb1551f68f3ee4aa174c78d1af175e","unresolved":true,"context_lines":[{"line_number":15,"context_line":"commit 8ae41e86e15d (\"Fix breackpoint_add for rtos swbp (#734)\")."},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"The resulting change lets the RTOS pick the \"current\" target for setting"},{"line_number":18,"context_line":"the hardware breakpoint on, which matters if address translation differs"},{"line_number":19,"context_line":"between threads."},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"Change-Id: I67ce24d6aa0ca9225436b380065d1e265424e70f"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"d5858ff7_7ea1a3b3","line":18,"updated":"2025-10-25 14:35:29.000000000","message":"Not hardware, but software breakpoint.","commit_id":"a28452ea4afd80a1698cb59ce87f0c2aa464b0b7"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"677a90d907e8bd9faf7a928d2f477708b211f5e3","unresolved":false,"context_lines":[{"line_number":15,"context_line":"commit 8ae41e86e15d (\"Fix breackpoint_add for rtos swbp (#734)\")."},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"The resulting change lets the RTOS pick the \"current\" target for setting"},{"line_number":18,"context_line":"the hardware breakpoint on, which matters if address translation differs"},{"line_number":19,"context_line":"between threads."},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"Change-Id: I67ce24d6aa0ca9225436b380065d1e265424e70f"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":3,"id":"b0c6cb19_2492f82b","line":18,"in_reply_to":"d5858ff7_7ea1a3b3","updated":"2025-11-07 12:20:19.000000000","message":"Done","commit_id":"a28452ea4afd80a1698cb59ce87f0c2aa464b0b7"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"157a493f15f0229816575bdbcfa6dd9f4bf55b1a","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"81fb0559_8cb40d8b","updated":"2025-10-21 19:52:18.000000000","message":"At least breakpoint.c is in conflict with the riscv-sync series.\nI rebased the series recently to clean fragmentation after updates in the middle of the relation chain.\n\nGet the branch from the top of the relation chain - currently\n9165: target: riscv: move the SMP commands under riscv | https://review.openocd.org/c/openocd/+/9165\nand rebase the new imports/fixes on top of it. Thanks","commit_id":"f86c1deceea8db1da47e5537aae5c1daaeda28d4"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"b90c834184c7b2acdca685e97152364d1c214d60","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"fa771b1f_3b589d29","updated":"2025-10-21 18:10:26.000000000","message":"TBH, I\u0027m not sure this is correct. IMHO the case when address translation differs between targets in an SMP group, the strategy of setting the SW breakpoint on a single target from the group will not work. In any case this is the behavior in RISC-V OpenOCD at the moment.","commit_id":"f86c1deceea8db1da47e5537aae5c1daaeda28d4"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1a91929ac1c7de956822edd08e2f8d622a0d0de8","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"c511641f_1437ee74","in_reply_to":"81fb0559_8cb40d8b","updated":"2025-10-22 15:36:31.000000000","message":"The new head of series it\n9177: server: rtos: don\u0027t fake step for hwthread rtos. | https://review.openocd.org/c/openocd/+/9177","commit_id":"f86c1deceea8db1da47e5537aae5c1daaeda28d4"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5caa54b8356b47ce37933b6db17c14c95bbbffc1","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"4d0dc346_d6bfba69","in_reply_to":"fa771b1f_3b589d29","updated":"2025-10-22 15:48:04.000000000","message":"Just for curiosity, the same strategy should not work for removing BPs:\nhttps://github.com/riscv-collab/riscv-openocd/blob/riscv/src/target/breakpoints.c#L370","commit_id":"f86c1deceea8db1da47e5537aae5c1daaeda28d4"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"5e7f9fe018555c5e51d3e0471875f3a9d4fc00c2","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"ea68f5b4_e5f2307e","updated":"2025-10-23 06:16:01.000000000","message":"Evgeniy, I fixed this patch to fit in the riscv-sync series.\nIf you don\u0027t mind, I would upload the fixed version to publish the complete series for testing","commit_id":"aa2eddabeec04fe9d8483bbc8b65b97bf7304e3a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"1a91929ac1c7de956822edd08e2f8d622a0d0de8","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"9694074f_4b55ef6b","updated":"2025-10-22 15:36:31.000000000","message":"This one changes the game.\nI designed my\n9125: target/breakpoints: breakpoint_add() rework | https://review.openocd.org/c/openocd/+/9125\naccording to\nhttps://github.com/riscv-collab/riscv-openocd/pull/767\nand missed that its functionality is limited to hard BPs in the current riscv-collab code.\n\nOk, my fault. I\u0027ll have to rework it again. But I\u0027m bit clueless in making it universally suitable for all target types.\n\nUnfortunately the code in this patch could possibly break at least most of multicore ARM devices. The old code relied on the typical configuration where the first target in SMP list is also the controlling, always on core. But these devices (Cortex-A and aarch64) has address translation too. The old code seems me to simply ignore the problem. Antonio?","commit_id":"aa2eddabeec04fe9d8483bbc8b65b97bf7304e3a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f90b99502c94c0b3a1b175dfc844f063d4110338","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"fa2fba9d_9915a9f4","in_reply_to":"9694074f_4b55ef6b","updated":"2025-11-12 21:03:34.000000000","message":"Done","commit_id":"aa2eddabeec04fe9d8483bbc8b65b97bf7304e3a"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"7f9bf9ab1c68daa91f3449e78dd0e2ac54bc18ae","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"a42e7ef3_2cf8edef","in_reply_to":"ea68f5b4_e5f2307e","updated":"2025-10-23 11:53:05.000000000","message":"Thanks!","commit_id":"aa2eddabeec04fe9d8483bbc8b65b97bf7304e3a"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"f90b99502c94c0b3a1b175dfc844f063d4110338","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"b7de348d_244d2631","updated":"2025-11-12 21:03:34.000000000","message":"Although I previously assumed we could merge this one later, the current\n9183: rtos: server/gdb_server: fix missing thread ID in stop reply | https://review.openocd.org/c/openocd/+/9183\ndepends on it. I think the easiest way is to quickly review this one and merge both (without rebasing 9183)\n\nAntonio? Evgeniy?","commit_id":"bf9756481762412847fb390d50888d12ebe71f2c"},{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"fae9bdc277905442a4e5a98ef3cc4dde7106bf0b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"0b446ec1_0808c7cd","in_reply_to":"b7de348d_244d2631","updated":"2025-11-13 11:57:31.000000000","message":"Fine by me","commit_id":"bf9756481762412847fb390d50888d12ebe71f2c"}],"src/rtos/rtos.h":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"157a493f15f0229816575bdbcfa6dd9f4bf55b1a","unresolved":true,"context_lines":[{"line_number":79,"context_line":"\tint (*write_buffer)(struct rtos *rtos, target_addr_t address, uint32_t size,"},{"line_number":80,"context_line":"\t\t\tconst uint8_t *buffer);"},{"line_number":81,"context_line":"\t/* When a software breakpoint is set, it is set on only one target,"},{"line_number":82,"context_line":"\t * because we assume memory is shared across them. By default this is the"},{"line_number":83,"context_line":"\t * first target in the SMP group. Override this function to have"},{"line_number":84,"context_line":"\t * breakpoint_add() use a different target. */"},{"line_number":85,"context_line":"\tstruct target * (*swbp_target)(struct rtos *rtos, target_addr_t address,"},{"line_number":86,"context_line":"\t\t\t\t     uint32_t length, enum breakpoint_type type);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"ff1756dc_cdfaffcd","line":83,"range":{"start_line":82,"start_character":52,"end_line":83,"end_character":33},"updated":"2025-10-21 19:52:18.000000000","message":"This is changed in\n9125: target/breakpoints: breakpoint_add() rework | https://review.openocd.org/c/openocd/+/9125","commit_id":"f86c1deceea8db1da47e5537aae5c1daaeda28d4"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"677a90d907e8bd9faf7a928d2f477708b211f5e3","unresolved":false,"context_lines":[{"line_number":79,"context_line":"\tint (*write_buffer)(struct rtos *rtos, target_addr_t address, uint32_t size,"},{"line_number":80,"context_line":"\t\t\tconst uint8_t *buffer);"},{"line_number":81,"context_line":"\t/* When a software breakpoint is set, it is set on only one target,"},{"line_number":82,"context_line":"\t * because we assume memory is shared across them. By default this is the"},{"line_number":83,"context_line":"\t * first target in the SMP group. Override this function to have"},{"line_number":84,"context_line":"\t * breakpoint_add() use a different target. */"},{"line_number":85,"context_line":"\tstruct target * (*swbp_target)(struct rtos *rtos, target_addr_t address,"},{"line_number":86,"context_line":"\t\t\t\t     uint32_t length, enum breakpoint_type type);"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"360648fd_39c48871","line":83,"range":{"start_line":82,"start_character":52,"end_line":83,"end_character":33},"in_reply_to":"ff1756dc_cdfaffcd","updated":"2025-11-07 12:20:19.000000000","message":"The mentioned change is not intended to merge now.","commit_id":"f86c1deceea8db1da47e5537aae5c1daaeda28d4"}]}