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When accessing\na register, if the register depends on a specific\nextension, its availability will be verified based\non the current value of the misa register.\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"fe5b00710519e1f0a3e09501cf72da9c691ffa21":{"kind":"REWORK","_number":3,"created":"2025-11-28 06:24:34.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/3 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1ea763d23c2337374909170687e16d1c5b9d9e89","subject":"rtos: server/gdb_server: fix missing thread ID in stop reply"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-28 06:24:17.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage","message":"target/riscv: fix misa register extension usage\n\nIntroduce RISC-V-sepecific `configure` parameter\n`-cetrig`, which temporarily enables all MISA extensions\nand transmits the target description. When accessing\na register, if the register depends on a specific\nextension, its availability will be verified based\non the current value of the misa register.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"8f6d5b9b20fde2a05c417e845b3a12d4c9eecf0c":{"kind":"REWORK","_number":2,"created":"2025-11-28 04:40:51.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/2 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"1ea763d23c2337374909170687e16d1c5b9d9e89","subject":"rtos: server/gdb_server: fix missing thread ID in stop reply"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-28 04:39:57.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage","message":"target/riscv: fix misa register extension usage\n\nIntroduce RISC-V-sepecific `configure` parameter\n`-cetrig`, which temporarily enables all MISA extensions\nand transmits the target description. When accessing\na register, if the register depends on a specific\nextension, its availability will be verified based\non the current value of the misa register.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"838d7fba6dad2d3e9615e711ccd1959c6731fd34":{"kind":"REWORK","_number":5,"created":"2026-01-29 02:08:00.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/5","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/5","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/5 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch 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temporarily enables all MISA\nextensions and transmits the target description.\nWhen accessing a register, if the register depends\non a specific extension, its availability will be\nverified based on the current value of the misa register.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"84ac900063ffe44580051904db0055b16469d615":{"kind":"NO_CODE_CHANGE","_number":4,"created":"2025-12-01 01:46:31.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/4 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd 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register extension usage\n\nIntroduce RISC-V-sepecific `configure` parameter\n`-detect-misa`, which temporarily enables all MISA\nextensions and transmits the target description.\nWhen accessing a register, if the register depends\non a specific extension, its availability will be\nverified based on the current value of the misa register.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"3a0d6cf13b8ebf10cdf72d53b292ce7d8b41916d":{"kind":"NO_CODE_CHANGE","_number":7,"created":"2026-05-27 08:27:08.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/7","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/7","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/7 \u0026\u0026 git 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08:26:03.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage and trigger configuration","message":"target/riscv: fix misa register extension usage and trigger configuration\n\nIntroduce RISC-V-specific `configure` parameter `-detect-misa`, which\ntemporarily enables all MISA extensions and transmits the target description.\n\nAdditionally, improve trigger configuration validation by calculating\ntdata1_ignore_mask based on whether execution modes are enabled.\nSome chips\u0027 trigger mode settings depend on the MISA execution modes\n(S/U/H). When these execution modes are not enabled, the corresponding\ntrigger configuration bits should be ignored during validation to avoid\nfalse configuration failures.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"c0bea6e001a0907aa22b645fcfbd8a97c79069a8":{"kind":"REWORK","_number":6,"created":"2026-05-27 08:20:46.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/6","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/6","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/6 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/6","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"b9e40161613fd880fc85fdb357365b70e646ff23","subject":"flash/stm32l4x: Fix flash size address for STM32WBA5"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"Zane Leung","email":"zhen.liang@spacemit.com","date":"2026-05-27 08:06:22.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage and trigger configuration","message":"target/riscv: fix misa register extension usage and trigger configuration\n\nIntroduce RISC-V-specific `configure` parameter `-detect-misa`, which\ntemporarily enables all MISA extensions and transmits the target description.\n\nAdditionally, improve trigger configuration validation by calculating\ntdata1_ignore_mask based on whether execution modes are enabled.\nSome chips\u0027 trigger mode settings depend on the MISA execution modes (S/U/H).\nWhen these execution modes are not enabled, the corresponding trigger\nconfiguration bits should be ignored during validation to avoid false\nconfiguration failures.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"9fd37a5511dc6f4b444acf9da95a503720a95b21":{"kind":"REWORK","_number":9,"created":"2026-05-27 08:38:22.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/9","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/9","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/9 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/9 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/9 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/9 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/9","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/9 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"b9e40161613fd880fc85fdb357365b70e646ff23","subject":"flash/stm32l4x: Fix flash size address for STM32WBA5"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"Zane Leung","email":"zhen.liang@spacemit.com","date":"2026-05-27 08:37:12.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage and trigger configuration","message":"target/riscv: fix misa register extension usage and trigger configuration\n\nIntroduce RISC-V-specific `configure` parameter `-detect-misa`, which\ntemporarily enables all MISA extensions and transmits the target\ndescription.\n\nAdditionally, improve trigger configuration validation by calculating\ntdata1_ignore_mask based on whether execution modes are enabled.\nSome chips\u0027 trigger mode settings depend on the MISA execution modes\n(S/U/H). When these execution modes are not enabled, the corresponding\ntrigger configuration bits should be ignored during validation to avoid\nfalse configuration failures.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"e9b6a08728c6d8ee706a16359f029a394bc00379":{"kind":"NO_CODE_CHANGE","_number":8,"created":"2026-05-27 08:31:09.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/8","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/8","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/8 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/8 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/8 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/8 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/8","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/8 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"b9e40161613fd880fc85fdb357365b70e646ff23","subject":"flash/stm32l4x: Fix flash size address for STM32WBA5"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"Zane Leung","email":"zhen.liang@spacemit.com","date":"2026-05-27 08:29:35.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage and trigger configuration","message":"target/riscv: fix misa register extension usage and trigger configuration\n\nIntroduce RISC-V-specific `configure` parameter `-detect-misa`, which\ntemporarily enables all MISA extensions and transmits the target\ndescription.\n\nAdditionally, improve trigger configuration validation by calculating\ntdata1_ignore_mask based on whether execution modes are enabled.\nSome chips\u0027 trigger mode settings depend on the MISA execution modes\n(S/U/H). When these execution modes are not enabled, the corresponding\ntrigger configuration bits should be ignored during validation to avoid\nfalse configuration failures.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"4a606968be5f9ab0fdd0632ecb872e517937fd38":{"kind":"REWORK","_number":11,"created":"2026-05-27 14:44:26.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/11","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/11","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/11 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/11 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/11 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/11 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/11","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/11 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"b9e40161613fd880fc85fdb357365b70e646ff23","subject":"flash/stm32l4x: Fix flash size address for STM32WBA5"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"Zane Leung","email":"zhen.liang@spacemit.com","date":"2026-05-27 14:39:25.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage and trigger configuration","message":"target/riscv: fix misa register extension usage and trigger configuration\n\nIntroduce RISC-V-specific `configure` parameter `-detect-misa`, which\ntemporarily enables all MISA extensions and transmits the target\ndescription.\n\nAdditionally, improve trigger configuration validation by calculating\ntdata1_ignore_mask based on whether execution modes are enabled.\nSome chips\u0027 trigger mode settings depend on the MISA execution modes\n(S/U/H). When these execution modes are not enabled, the corresponding\ntrigger configuration bits should be ignored during validation to avoid\nfalse configuration failures.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"a1c058dd658f5a0201df5e9155819dcace9ccbad":{"kind":"REWORK","_number":10,"created":"2026-05-27 09:52:47.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/10","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/10","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/10 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/10 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/10 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/10 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/10","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/10 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"b9e40161613fd880fc85fdb357365b70e646ff23","subject":"flash/stm32l4x: Fix flash size address for STM32WBA5"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"Zane Leung","email":"zhen.liang@spacemit.com","date":"2026-05-27 09:50:44.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage and trigger configuration","message":"target/riscv: fix misa register extension usage and trigger configuration\n\nIntroduce RISC-V-specific `configure` parameter `-detect-misa`, which\ntemporarily enables all MISA extensions and transmits the target\ndescription.\n\nAdditionally, improve trigger configuration validation by calculating\ntdata1_ignore_mask based on whether execution modes are enabled.\nSome chips\u0027 trigger mode settings depend on the MISA execution modes\n(S/U/H). When these execution modes are not enabled, the corresponding\ntrigger configuration bits should be ignored during validation to avoid\nfalse configuration failures.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}},"fa5b376ae4a0c1cbd83e97d2d461fdc39cfdbb8a":{"kind":"REWORK","_number":12,"created":"2026-05-28 08:42:59.000000000","uploader":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"ref":"refs/changes/25/9225/12","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/25/9225/12","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/12 \u0026\u0026 git checkout -b change-9225 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/12 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/12 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/12 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/25/9225/12","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/25/9225/12 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"b9e40161613fd880fc85fdb357365b70e646ff23","subject":"flash/stm32l4x: Fix flash size address for STM32WBA5"}],"author":{"name":"liangzhen","email":"zhen.liang@spacemit.com","date":"2025-11-27 07:59:17.000000000","tz":480},"committer":{"name":"Zane Leung","email":"zhen.liang@spacemit.com","date":"2026-05-28 08:41:54.000000000","tz":480},"subject":"target/riscv: fix misa register extension usage and trigger configuration","message":"target/riscv: fix misa register extension usage and trigger configuration\n\nIntroduce RISC-V-specific `configure` parameter `-detect-misa`, which\ntemporarily enables all MISA extensions and transmits the target\ndescription.\n\nAdditionally, improve trigger configuration validation by calculating\ntdata1_ignore_mask based on whether execution modes are enabled.\nSome chips\u0027 trigger mode settings depend on the MISA execution modes\n(S/U/H). When these execution modes are not enabled, the corresponding\ntrigger configuration bits should be ignored during validation to avoid\nfalse configuration failures.\n\nsee https://github.com/riscv-collab/riscv-openocd/issues/1298\n\nChange-Id: I83d321046edb6df2c24711a8b47a6abd140f2947\nSigned-off-by: liangzhen \u003czhen.liang@spacemit.com\u003e\n"}}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"NOT_READY","labels":[{"label":"Verified","status":"OK","applied_by":{"_account_id":1000014,"name":"jenkins","username":"jenkins","tags":["SERVICE_USER"]}},{"label":"Code-Review","status":"NEED"}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[]}},{"name":"Code-Review","status":"UNSATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":false,"status":"FAIL","passing_atoms":[],"failing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"]}}]}