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Code-Review-1\n\n(1 comment)","accounts_in_message":[],"_revision_number":4},{"id":"f123b4c7f19ca023e93aabe59d9e4339a3a46d85","author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"real_author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"date":"2025-12-13 17:34:33.000000000","message":"Patch Set 4:\n\n(1 comment)","accounts_in_message":[],"_revision_number":4},{"id":"330b04e1d000d65adce62446dab2db4c4f39292a","tag":"autogenerated:gerrit:abandon","author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"real_author":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"date":"2025-12-16 19:26:47.000000000","message":"Abandoned\n\nNot the right approach. Fixed by https://review.openocd.org/c/openocd/+/9316/ instead.","accounts_in_message":[],"_revision_number":4}],"current_revision":"d905ff9ab5cf161351222d981c910cfe8dd54fc3","revisions":{"d66254b75776c445133d3d301e962b60ac840876":{"kind":"TRIVIAL_REBASE","_number":2,"created":"2025-12-11 23:35:19.000000000","uploader":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"ref":"refs/changes/13/9313/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/13/9313/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/2 \u0026\u0026 git checkout -b change-9313 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/13/9313/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"aa9ff8dc5ec60c46134f57a2f858149bb083036e","subject":"target/esirisc_trace: drop macro BIT_MASK() conflicting with bits.h"}],"author":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-11 23:25:28.000000000","tz":-300},"committer":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-11 23:35:01.000000000","tz":-300},"subject":"target/riscv: don\u0027t finish reset until allunavail clears","message":"target/riscv: don\u0027t finish reset until allunavail clears\n\nThis used to be our behavior, but it regressed in commit 1c168242e9f5\n(\"target/riscv: simplify reset\"), which was intended purely as a code\ncleanup. On some chips, like the GD32VF103, anyhavereset/allhavereset\nassert before anyunavail/allunavail deassert, causing us to leave this\nroutine before the reset finishes.\n\nThat behavior is arguably a violation of the debug spec, which says that\nhavereset should be set \"when harts have been reset\". But the spec also\nsays that the system coming out of reset is \"reported by allunavail,\nanyunavail\", which makes me believe it\u0027s more correct to check only\nthose bits.\n\nThis change restores the previous behavior, where we use the value of\nhavereset to decide whether to set ackhavereset only after allunavail\nhas deasserted.\n\nFixes: 5754aebc4945 (\"target: riscv: Sync with the RISC-V fork\")\nSigned-off-by: Thomas Hebb \u003ctommyhebb@gmail.com\u003e\nChange-Id: Ie3b5fa48fedf240d89c61010995c0044d2b62804\n"}},"269e827fa95d13edf554d9f087d37a6de3d34ba1":{"kind":"REWORK","_number":3,"created":"2025-12-12 22:32:56.000000000","uploader":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"ref":"refs/changes/13/9313/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/13/9313/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/3 \u0026\u0026 git checkout -b change-9313 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/13/9313/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"5479c58d23771c31d6f034a63b3f01b83ed5129a","subject":"tcl/target/stm32l4, tcl/target/stm32w*: Fix clock configuration"}],"author":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-11 23:25:28.000000000","tz":-300},"committer":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-12 22:31:48.000000000","tz":-300},"subject":"target/riscv: fix incorrect reset completion condition","message":"target/riscv: fix incorrect reset completion condition\n\nPrior to riscv-openocd commit[1] 1c168242e9f5 (\"target/riscv: simplify\nreset\"), we waited for allunavail to deassert after issuing a reset,\nthen we checked allhavereset once to decide whether to set ackhavereset.\n\nSince that commit, we stop waiting either when allunavail deasserts or\nwhen allhavereset asserts. This is wrong. The RISC-V Debug Specification\n1.0 says that \"while [a] reset is on-going, harts are either in the\nrunning state ... or in the unavailable state\", meaning allunavail is\nnot guaranteed to be asserted at all! We should stop waiting only when\nboth conditions are met.\n\nWe could in theory remove the allunavail check entirely, since the Debug\nSpecification 1.0 says that \"once a hart’s reset is complete, havereset\nbecomes set\". However, that wording was less clear in the 0.13 spec and\nat least one real chip (GD32VF103) asserts havereset before deasserting\nunavail. Since we can\u0027t do anything with an unavailable hart anyway, it\nseems harmless to keep the allunavail check to accommodate noncompliant\nimplementations.\n\n[1] https://github.com/riscv-collab/riscv-openocd/commit/1c168242e9f5993aec7024998529e2b2ed53098a\n[2] https://github.com/riscv/riscv-debug-spec/releases/download/1.0/riscv-debug-specification.pdf\n\nFixes: 5754aebc4945 (\"target: riscv: Sync with the RISC-V fork\")\nSigned-off-by: Thomas Hebb \u003ctommyhebb@gmail.com\u003e\nChange-Id: Ie3b5fa48fedf240d89c61010995c0044d2b62804\n"}},"0d7f3a3e59ad54509274a84f4d3f52966d227840":{"kind":"REWORK","_number":1,"created":"2025-12-11 23:34:13.000000000","uploader":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"ref":"refs/changes/13/9313/1","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/13/9313/1","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/1 \u0026\u0026 git checkout -b change-9313 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/13/9313/1","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"eed1f454e230e3ca954136ce0a8599d5ee316d7c","subject":"tcl/target/gd32vf103: copy a few minor settings from riscv-openocd"}],"author":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-11 23:25:28.000000000","tz":-300},"committer":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-11 23:26:48.000000000","tz":-300},"subject":"target/riscv: don\u0027t finish reset until allunavail clears","message":"target/riscv: don\u0027t finish reset until allunavail clears\n\nThis used to be our behavior, but it regressed in commit 1c168242e9f5\n(\"target/riscv: simplify reset\"), which was intended purely as a code\ncleanup. On some chips, like the GD32VF103, anyhavereset/allhavereset\nassert before anyunavail/allunavail deassert, causing us to leave this\nroutine before the reset finishes.\n\nThat behavior is arguably a violation of the debug spec, which says that\nhavereset should be set \"when harts have been reset\". But the spec also\nsays that the system coming out of reset is \"reported by allunavail,\nanyunavail\", which makes me believe it\u0027s more correct to check only\nthose bits.\n\nThis change restores the previous behavior, where we use the value of\nhavereset to decide whether to set ackhavereset only after allunavail\nhas deasserted.\n\nFixes: 5754aebc4945 (\"target: riscv: Sync with the RISC-V fork\")\nSigned-off-by: Thomas Hebb \u003ctommyhebb@gmail.com\u003e\nChange-Id: Ie3b5fa48fedf240d89c61010995c0044d2b62804\n"}},"d905ff9ab5cf161351222d981c910cfe8dd54fc3":{"kind":"NO_CODE_CHANGE","_number":4,"created":"2025-12-12 23:01:38.000000000","uploader":{"_account_id":1001983,"name":"Tom Hebb","email":"tommyhebb@gmail.com","username":"tchebb"},"ref":"refs/changes/13/9313/4","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/13/9313/4","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/4 \u0026\u0026 git checkout -b change-9313 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/13/9313/4","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/13/9313/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"5479c58d23771c31d6f034a63b3f01b83ed5129a","subject":"tcl/target/stm32l4, tcl/target/stm32w*: Fix clock configuration"}],"author":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-11 23:25:28.000000000","tz":-300},"committer":{"name":"Thomas Hebb","email":"tommyhebb@gmail.com","date":"2025-12-12 23:01:05.000000000","tz":-300},"subject":"target/riscv: correct reset completion condition","message":"target/riscv: correct reset completion condition\n\nPrior to riscv-openocd commit [1] (\"target/riscv: simplify reset\"), we\nwaited for allunavail to deassert after issuing a reset, then we checked\nallhavereset once to decide whether to set ackhavereset.\n\nSince that commit, we stop waiting either when allunavail deasserts or\nwhen allhavereset asserts. This is wrong. The RISC-V Debug Specification\n1.0 says that \"while [a] reset is on-going, harts are either in the\nrunning state ... or in the unavailable state\", meaning allunavail is\nnot guaranteed to be asserted at all! We should stop waiting only when\nboth conditions are met.\n\nWe could in theory remove the allunavail check entirely, since the Debug\nSpecification 1.0 says that \"once a hart’s reset is complete, havereset\nbecomes set\". However, that wording was less clear in the 0.13 spec and\nat least one real chip (GD32VF103) asserts havereset before deasserting\nunavail. Since we can\u0027t do anything with an unavailable hart anyway, it\nseems harmless to keep the allunavail check to accommodate noncompliant\nimplementations.\n\nLink: https://github.com/riscv-collab/riscv-openocd/commit/1c168242e9f5 [1]\nFixes: 5754aebc4945 (\"target: riscv: Sync with the RISC-V fork\")\nSigned-off-by: Thomas Hebb \u003ctommyhebb@gmail.com\u003e\nChange-Id: Ie3b5fa48fedf240d89c61010995c0044d2b62804\n"}}},"requirements":[],"submit_records":[],"submit_requirements":[]}