)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1002047,"name":"Evgeniy Naydanov","email":"eugnay@gmail.com","username":"en-sc"},"change_message_id":"778635748090f7d3591476897b8c98dccdf5c17b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"8dc055cb_b3e4b1a4","updated":"2025-12-12 12:27:17.000000000","message":"Please note, I am unable to test this since I don\u0027t have the hardware.","commit_id":"199359b57854d5d83cc24a1fb153a2c1a16afc45"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"cf1a51a0c6c37f72e82317148b7801014a05e7a5","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"09e9897c_60d7b8be","in_reply_to":"8dc055cb_b3e4b1a4","updated":"2025-12-12 17:52:35.000000000","message":"Thanks for providing solution so quickly!\nSorry, I had to rebase your patch to ensure smooth merge.\n\nTested on GD32VF103.\nWith the delay added to `reset-assert` event in the following\n9316: tcl/target/gd32vf103: adjust reset workaround to new riscv target | https://review.openocd.org/c/openocd/+/9316\nworks in both `reset_config none` and `reset_config srst_only`","commit_id":"199359b57854d5d83cc24a1fb153a2c1a16afc45"}]}