)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"836572e2635e0b9b6741858ba3d19e36092dbcaa","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"233e914f_4ea02011","updated":"2026-01-21 20:40:37.000000000","message":"Thanks for the patch, Nguyen! Can you disclose the actual device you are using? I would like the test it on the same or similar target device.","commit_id":"31834643f49893d7c9b18acf28e45d587bd98f27"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"9be581db9dae85b815695ff491c7c89a836fb544","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"195e26e7_4a2a5382","in_reply_to":"0c10854f_b7aeb9fb","updated":"2026-01-24 16:44:24.000000000","message":"Thanks for pointing that out. I have updated the rtt_channel struct to use uint64_t. Please let me know if you find any further problems.","commit_id":"31834643f49893d7c9b18acf28e45d587bd98f27"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"7f932dc98b653741f44b3e57dc85589f1fa831a3","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":2,"id":"17c64087_b749db9c","in_reply_to":"195e26e7_4a2a5382","updated":"2026-01-30 01:09:26.000000000","message":"Done","commit_id":"31834643f49893d7c9b18acf28e45d587bd98f27"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"612b97661a3aee7f01348a412eb07daf22d85482","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"5762f251_b39a961f","in_reply_to":"233e914f_4ea02011","updated":"2026-01-22 02:21:15.000000000","message":"The actual target I am using is a custom FPGA implementation of a RISC-V 64-bit core running Zephyr RTOS. I also applied the patch from https://review.openocd.org/c/openocd/+/8234 to enable RTT support for RISC-V on my build.\n\nHowever, I think this issue is not specific to my hardware. It is strictly an architectural mismatch caused by the LP64 data model (8-byte pointers) used in 64-bit RISC-V, whereas OpenOCD currently hardcodes ILP32 (32-bit) offsets.\n\nI have verified this by building the Zephyr RTT sample for both `qemu_riscv32` and `qemu_riscv64` and inspecting the `SEGGER_RTT_BUFFER_UP` struct layout using GDB. The offset mismatch for `RdOff` (which causes the corruption) is evident:\n\n1. On 32-bit (qemu_riscv32) - RdOff is at offset 16 (0x10):\n```\n(gdb) ptype /o SEGGER_RTT_BUFFER_UP\ntype \u003d struct {\n/* 0      |      4 */    const char *sName;\n/* 4      |      4 */    char *pBuffer;\n/* 8      |      4 */    unsigned int SizeOfBuffer;\n/* 12      |      4 */    unsigned int WrOff;\n/* 16      |      4 */    volatile unsigned int RdOff;\n/* 20      |      4 */    unsigned int Flags;\n                              /* total size (bytes):   24 */\n                            }\n```\n\n2. On 64-bit (qemu_riscv64, and also my FPGA) - RdOff is at offset 24 (0x18):\n```\n(gdb) ptype /o SEGGER_RTT_BUFFER_UP\ntype \u003d struct {\n/* 0      |      8 */    const char *sName;\n/* 8      |      8 */    char *pBuffer;\n/* 16      |      4 */    unsigned int SizeOfBuffer;\n/* 20      |      4 */    unsigned int WrOff;\n/* 24      |      4 */    volatile unsigned int RdOff;\n/* 28      |      4 */    unsigned int Flags;\n                              /* total size (bytes):   32 */\n                            }\n```\n\nSince this is a standard alignment issue, I think it should be able to reproduced on any standard 64-bit RISC-V target, but I dont have another one here, so it would be great if you verify it for me.\n\nPlease let me know if you need any further information.","commit_id":"31834643f49893d7c9b18acf28e45d587bd98f27"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"ebb2620de03f62482db06d7a6676d2a427ba954d","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":2,"id":"0c10854f_b7aeb9fb","in_reply_to":"5762f251_b39a961f","updated":"2026-01-23 08:34:52.000000000","message":"I understand your point of view. I only asked about your target because I need a board for testing. I found a board — I just need some time to get firmware with RTT running on it.\n\nAnyway, one problem with your patch is that you still read only 32-bit addresses, right? I assume that this works in your case because you do not exceed the 32-bit address space.","commit_id":"31834643f49893d7c9b18acf28e45d587bd98f27"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"07bb5f2397117d1c9221724bbcd92fa8c25ba99b","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":5,"id":"ab9cb8e2_8efd5c75","updated":"2026-04-09 17:30:34.000000000","message":"The patch works as expected, thanks! Tested with the spike simulator and a RV64 target.","commit_id":"52c5e2e853ad2b816a378f3744e7118f49c561d8"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"929885d437df3349cae2242d9afb0829676e6dcb","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"57a51395_444a374e","updated":"2026-05-10 10:22:01.000000000","message":"@Antonio, let\u0027s merge this before v1.0 release, please.","commit_id":"6126ba705c37e1cda2625447bd2ff9c5529b322e"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"3177a3bb0dcf75f05202840587e715286bb47bcd","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"115676d1_bd61c5cc","updated":"2026-04-10 07:29:53.000000000","message":"Thanks for your comments. I\u0027ve updated the patch.","commit_id":"6126ba705c37e1cda2625447bd2ff9c5529b322e"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"06d66c0dc6b19f93b6f5c2c9b9bc59de60998a2b","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":7,"id":"2e6579f7_812c707d","updated":"2026-05-12 08:26:49.000000000","message":"Thanks.\nQuestion about AArch64. At least Cortex-A35 can be configured for booting in EL3 64 bit while some other ELx (x\u003c3) is 32 bits.\nWe already have issues with GDB that is unable to handle this change while stepping through different EL, e.g. due to exceptions/interrupts.\nHow is it supposed to work for RTT?","commit_id":"6ad83300fbd03f46abcfb5eac96debacc329a0e0"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"10fa110b05f80f45b46d1476466b49b8bc36212e","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":7,"id":"b8503390_a68a89b8","in_reply_to":"2e6579f7_812c707d","updated":"2026-05-12 09:32:50.000000000","message":"Good question. I\u0027m not very familiar with Cortex-A cores, and especially not with these kinds of \"details\". According to SEGGER, their RTT implementation supports Cortex-A, but they don\u0027t provide any information regarding different exception levels [1].\n\nPlease correct me if I’m wrong: if my RTT code runs at EL1 in AArch32 mode on a Cortex-A35, it should be sufficient to configure OpenOCD to use 32-bit RTT. Even if the core switches to AArch64 state during exceptions, this should not interfere with the OpenOCD RTT code, so everything should still work as expected, right?\n\nIf so, I will add this feature to my TODO list for RTTv2, which will also include multi-target support and other improvements. In the meantime, let\u0027s merge the current \"basic\" 64-bit support from this patch as is.\n\n[1] https://kb.segger.com/RTT#Cortex-A_specifics","commit_id":"6ad83300fbd03f46abcfb5eac96debacc329a0e0"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0284337bad37951e2c57ffe60f1cb049bb6b4293","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"6b1ef345_296e01e4","in_reply_to":"b8503390_a68a89b8","updated":"2026-05-17 20:59:21.000000000","message":"You are right, RTT target side is run with a certain configuration (32 vs 64 bit) and does not change during the execution.\nNevertheless, checking the current state of the CPU (32 vs 64) could be not the same as the RTT execution.\n\nI was also thinking, by changing EL or by changing application at EL0 (case OS in EL1 and applications at EL0), the MMU changes the memory map of the CPU.\nThe doc from Segger does not mention MMU, but say that on Cortex-A RTT requires memory access through direct MEM-AP (e.g. AXI), not through the CPU. And this means memory access through physical addressing, bypassing the MMU.\nSo no issue linked with MMU.\nBut I have not checked if the RTT implementation in OpenOCD uses physical addresses for the buffers, nor if the access for Cortex-A are through the AXI AP.\n\nAgree. Let\u0027s merge this and further improvements will follow","commit_id":"6ad83300fbd03f46abcfb5eac96debacc329a0e0"}],"src/rtt/rtt.h":[{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"156b96da78357fe1c3bd74f647f976a8abebb360","unresolved":true,"context_lines":[{"line_number":47,"context_line":"\t/** Channel structure address on the target. */"},{"line_number":48,"context_line":"\ttarget_addr_t address;"},{"line_number":49,"context_line":"\t/** Channel name address on the target. */"},{"line_number":50,"context_line":"\tuint64_t name_addr;"},{"line_number":51,"context_line":"\t/** Buffer address on the target. */"},{"line_number":52,"context_line":"\tuint64_t buffer_addr;"},{"line_number":53,"context_line":"\t/** Channel buffer size in bytes. */"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"02eb3d19_616401c1","line":50,"updated":"2026-01-26 20:32:05.000000000","message":"This should be `target_addr_t`.","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"99bed3deb43e6324ff562dc8c529fabac5e18fbc","unresolved":false,"context_lines":[{"line_number":47,"context_line":"\t/** Channel structure address on the target. */"},{"line_number":48,"context_line":"\ttarget_addr_t address;"},{"line_number":49,"context_line":"\t/** Channel name address on the target. */"},{"line_number":50,"context_line":"\tuint64_t name_addr;"},{"line_number":51,"context_line":"\t/** Buffer address on the target. */"},{"line_number":52,"context_line":"\tuint64_t buffer_addr;"},{"line_number":53,"context_line":"\t/** Channel buffer size in bytes. */"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"a6755ec9_482a276c","line":50,"in_reply_to":"02eb3d19_616401c1","updated":"2026-01-27 17:09:43.000000000","message":"Done","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"156b96da78357fe1c3bd74f647f976a8abebb360","unresolved":true,"context_lines":[{"line_number":49,"context_line":"\t/** Channel name address on the target. */"},{"line_number":50,"context_line":"\tuint64_t name_addr;"},{"line_number":51,"context_line":"\t/** Buffer address on the target. */"},{"line_number":52,"context_line":"\tuint64_t buffer_addr;"},{"line_number":53,"context_line":"\t/** Channel buffer size in bytes. */"},{"line_number":54,"context_line":"\tuint32_t size;"},{"line_number":55,"context_line":"\t/**  Write position within the buffer in bytes. */"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"aec69e16_6604b7ad","line":52,"updated":"2026-01-26 20:32:05.000000000","message":"This also `target_addr_t`.","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"99bed3deb43e6324ff562dc8c529fabac5e18fbc","unresolved":false,"context_lines":[{"line_number":49,"context_line":"\t/** Channel name address on the target. */"},{"line_number":50,"context_line":"\tuint64_t name_addr;"},{"line_number":51,"context_line":"\t/** Buffer address on the target. */"},{"line_number":52,"context_line":"\tuint64_t buffer_addr;"},{"line_number":53,"context_line":"\t/** Channel buffer size in bytes. */"},{"line_number":54,"context_line":"\tuint32_t size;"},{"line_number":55,"context_line":"\t/**  Write position within the buffer in bytes. */"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"3236dad4_a40aeab1","line":52,"in_reply_to":"aec69e16_6604b7ad","updated":"2026-01-27 17:09:43.000000000","message":"Done","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"156b96da78357fe1c3bd74f647f976a8abebb360","unresolved":true,"context_lines":[{"line_number":53,"context_line":"\t/** Channel buffer size in bytes. */"},{"line_number":54,"context_line":"\tuint32_t size;"},{"line_number":55,"context_line":"\t/**  Write position within the buffer in bytes. */"},{"line_number":56,"context_line":"\tuint64_t write_pos;"},{"line_number":57,"context_line":"\t/** Read position within the buffer in bytes. */"},{"line_number":58,"context_line":"\tuint64_t read_pos;"},{"line_number":59,"context_line":"\t/**"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"6f83e827_22c14d8e","line":56,"updated":"2026-01-26 20:32:05.000000000","message":"Why are you using 64 bits here now? As you already mentioned, the read and write offset is 4 bytes on 32 and 64-bit targets.","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"99bed3deb43e6324ff562dc8c529fabac5e18fbc","unresolved":false,"context_lines":[{"line_number":53,"context_line":"\t/** Channel buffer size in bytes. */"},{"line_number":54,"context_line":"\tuint32_t size;"},{"line_number":55,"context_line":"\t/**  Write position within the buffer in bytes. */"},{"line_number":56,"context_line":"\tuint64_t write_pos;"},{"line_number":57,"context_line":"\t/** Read position within the buffer in bytes. */"},{"line_number":58,"context_line":"\tuint64_t read_pos;"},{"line_number":59,"context_line":"\t/**"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"4e0e27e0_d38a81da","line":56,"in_reply_to":"6f83e827_22c14d8e","updated":"2026-01-27 17:09:43.000000000","message":"My mistake, I missed that while editing. I\u0027ve reverted it back to `uint32_t` now. Thanks!","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"}],"src/target/rtt.c":[{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"156b96da78357fe1c3bd74f647f976a8abebb360","unresolved":true,"context_lines":[{"line_number":75,"context_line":"\t\treturn ret;"},{"line_number":76,"context_line":""},{"line_number":77,"context_line":"\tchannel-\u003eaddress \u003d address;"},{"line_number":78,"context_line":"\tchannel-\u003ename_addr \u003d target_buffer_get_u32(target, buf + 0);"},{"line_number":79,"context_line":"\tchannel-\u003ebuffer_addr \u003d target_buffer_get_u32(target, buf + params-\u003ebuffer_addr_offset);"},{"line_number":80,"context_line":"\tchannel-\u003esize \u003d target_buffer_get_u32(target, buf + params-\u003esize_offset);"},{"line_number":81,"context_line":"\tchannel-\u003ewrite_pos \u003d target_buffer_get_u32(target, buf + params-\u003ewrite_pos_offset);"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"f3f80c56_dbdb7a3b","line":78,"updated":"2026-01-26 20:32:05.000000000","message":"You still read only 32 bit from the channel struct on the target. This should be `target_buffer_get_u64()`, depending on the target address bits.","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"99bed3deb43e6324ff562dc8c529fabac5e18fbc","unresolved":false,"context_lines":[{"line_number":75,"context_line":"\t\treturn ret;"},{"line_number":76,"context_line":""},{"line_number":77,"context_line":"\tchannel-\u003eaddress \u003d address;"},{"line_number":78,"context_line":"\tchannel-\u003ename_addr \u003d target_buffer_get_u32(target, buf + 0);"},{"line_number":79,"context_line":"\tchannel-\u003ebuffer_addr \u003d target_buffer_get_u32(target, buf + params-\u003ebuffer_addr_offset);"},{"line_number":80,"context_line":"\tchannel-\u003esize \u003d target_buffer_get_u32(target, buf + params-\u003esize_offset);"},{"line_number":81,"context_line":"\tchannel-\u003ewrite_pos \u003d target_buffer_get_u32(target, buf + params-\u003ewrite_pos_offset);"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"d0cd04b1_c5c26a2a","line":78,"in_reply_to":"f3f80c56_dbdb7a3b","updated":"2026-01-27 17:09:43.000000000","message":"Done","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"156b96da78357fe1c3bd74f647f976a8abebb360","unresolved":true,"context_lines":[{"line_number":76,"context_line":""},{"line_number":77,"context_line":"\tchannel-\u003eaddress \u003d address;"},{"line_number":78,"context_line":"\tchannel-\u003ename_addr \u003d target_buffer_get_u32(target, buf + 0);"},{"line_number":79,"context_line":"\tchannel-\u003ebuffer_addr \u003d target_buffer_get_u32(target, buf + params-\u003ebuffer_addr_offset);"},{"line_number":80,"context_line":"\tchannel-\u003esize \u003d target_buffer_get_u32(target, buf + params-\u003esize_offset);"},{"line_number":81,"context_line":"\tchannel-\u003ewrite_pos \u003d target_buffer_get_u32(target, buf + params-\u003ewrite_pos_offset);"},{"line_number":82,"context_line":"\tchannel-\u003eread_pos \u003d target_buffer_get_u32(target, buf + params-\u003eread_pos_offset);"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"c2d70434_9dcf91ac","line":79,"updated":"2026-01-26 20:32:05.000000000","message":"Same here.","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"99bed3deb43e6324ff562dc8c529fabac5e18fbc","unresolved":false,"context_lines":[{"line_number":76,"context_line":""},{"line_number":77,"context_line":"\tchannel-\u003eaddress \u003d address;"},{"line_number":78,"context_line":"\tchannel-\u003ename_addr \u003d target_buffer_get_u32(target, buf + 0);"},{"line_number":79,"context_line":"\tchannel-\u003ebuffer_addr \u003d target_buffer_get_u32(target, buf + params-\u003ebuffer_addr_offset);"},{"line_number":80,"context_line":"\tchannel-\u003esize \u003d target_buffer_get_u32(target, buf + params-\u003esize_offset);"},{"line_number":81,"context_line":"\tchannel-\u003ewrite_pos \u003d target_buffer_get_u32(target, buf + params-\u003ewrite_pos_offset);"},{"line_number":82,"context_line":"\tchannel-\u003eread_pos \u003d target_buffer_get_u32(target, buf + params-\u003eread_pos_offset);"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"5dd0b59e_6f11a529","line":79,"in_reply_to":"c2d70434_9dcf91ac","updated":"2026-01-27 17:09:43.000000000","message":"Done","commit_id":"3580d027b8edc9d5789a49e63e37d5a10019bafb"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"07bb5f2397117d1c9221724bbcd92fa8c25ba99b","unresolved":true,"context_lines":[{"line_number":18,"context_line":""},{"line_number":19,"context_line":"#include \"target.h\""},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"/** Offsets for RTT control block parameters. */"},{"line_number":22,"context_line":"struct rtt_control_params {"},{"line_number":23,"context_line":"\tuint32_t channel_size;"},{"line_number":24,"context_line":"\tuint32_t buffer_addr_offset;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"43e6d9b9_66ba693e","line":21,"updated":"2026-04-09 17:30:34.000000000","message":"Use `//` for single-line comments, also below.","commit_id":"52c5e2e853ad2b816a378f3744e7118f49c561d8"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"3177a3bb0dcf75f05202840587e715286bb47bcd","unresolved":false,"context_lines":[{"line_number":18,"context_line":""},{"line_number":19,"context_line":"#include \"target.h\""},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"/** Offsets for RTT control block parameters. */"},{"line_number":22,"context_line":"struct rtt_control_params {"},{"line_number":23,"context_line":"\tuint32_t channel_size;"},{"line_number":24,"context_line":"\tuint32_t buffer_addr_offset;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"e437e9cd_67b8aa17","line":21,"in_reply_to":"43e6d9b9_66ba693e","updated":"2026-04-10 07:29:53.000000000","message":"Done","commit_id":"52c5e2e853ad2b816a378f3744e7118f49c561d8"},{"author":{"_account_id":1000853,"name":"zapb","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"07bb5f2397117d1c9221724bbcd92fa8c25ba99b","unresolved":true,"context_lines":[{"line_number":135,"context_line":"{"},{"line_number":136,"context_line":"\tint ret;"},{"line_number":137,"context_line":"\tuint32_t len;"},{"line_number":138,"context_line":"\tconst struct rtt_control_params *params \u003d get_rtt_params(target);"},{"line_number":139,"context_line":""},{"line_number":140,"context_line":"\tif (!*length)"},{"line_number":141,"context_line":"\t\treturn ERROR_OK;"}],"source_content_type":"text/x-csrc","patch_set":5,"id":"9b1ce5c2_6f256ad4","line":138,"updated":"2026-04-09 17:30:34.000000000","message":"Move this directly before you use `params`.","commit_id":"52c5e2e853ad2b816a378f3744e7118f49c561d8"},{"author":{"_account_id":1002489,"name":"Nguyen Huy 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Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"929885d437df3349cae2242d9afb0829676e6dcb","unresolved":true,"context_lines":[{"line_number":20,"context_line":""},{"line_number":21,"context_line":"// Offsets for RTT control block parameters."},{"line_number":22,"context_line":"struct rtt_control_params {"},{"line_number":23,"context_line":"\tuint32_t channel_size;"},{"line_number":24,"context_line":"\tuint32_t buffer_addr_offset;"},{"line_number":25,"context_line":"\tuint32_t size_offset;"},{"line_number":26,"context_line":"\tuint32_t write_pos_offset;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"00ee4436_fa73bb2a","line":23,"updated":"2026-05-10 10:22:01.000000000","message":"All these variables should be `unsigned int` rather than `uint32_t` as they are not target-specific.","commit_id":"6126ba705c37e1cda2625447bd2ff9c5529b322e"},{"author":{"_account_id":1002489,"name":"Nguyen Huy Hoang","email":"huyhoang3082001@gmail.com","username":"hhoang308"},"change_message_id":"79524f857b00bc33d9d17064a1160fa93806b4d1","unresolved":false,"context_lines":[{"line_number":20,"context_line":""},{"line_number":21,"context_line":"// Offsets for RTT control block parameters."},{"line_number":22,"context_line":"struct rtt_control_params {"},{"line_number":23,"context_line":"\tuint32_t channel_size;"},{"line_number":24,"context_line":"\tuint32_t buffer_addr_offset;"},{"line_number":25,"context_line":"\tuint32_t size_offset;"},{"line_number":26,"context_line":"\tuint32_t write_pos_offset;"}],"source_content_type":"text/x-csrc","patch_set":6,"id":"360f3bf2_bb41ef85","line":23,"in_reply_to":"00ee4436_fa73bb2a","updated":"2026-05-11 17:25:36.000000000","message":"I understand, I\u0027ve just modified it.","commit_id":"6126ba705c37e1cda2625447bd2ff9c5529b322e"}]}