)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"3785ee9971c66150303e1721e3ef1fc752418437","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"2a0b9634_4bd4a88c","updated":"2026-01-25 15:39:27.000000000","message":"Jérôme, thanks for the patch.\n\nI\u0027m not sure if you\u0027re aware of the older and not yet finished Silabs Series 2 support patch:\n6173: WIP: support EFM32 series 2 devices | https://review.openocd.org/c/openocd/+/6173\n\nThe mentioned patch re-uses Series 0 and 1 flash driver code so this one should do so as well. It\u0027s hard to believe that a person with silabs.com mail address didn\u0027t have the opportunity to test on Series 0/1. Hopefully you may cooperate with the OpenOCD community on regression testing. I added couple of them as a reviewers.","commit_id":"fd3f8d869bfbd06d382ce92b545b04f126a40139"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"72566c7e89256a73fce6c181a780258461441d46","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"763233c1_85d35921","updated":"2026-01-29 09:28:32.000000000","message":"Nice, thanks! Don\u0027t hesitate to ask if something is not clear.","commit_id":"fd3f8d869bfbd06d382ce92b545b04f126a40139"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"4e6e94f09cbb5afc00413cabe647c1fa4cf91b87","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"1ee02ba2_35796c9c","updated":"2026-01-28 14:29:20.000000000","message":"Thanks for the patch, Jérôme!\n\nIt\u0027s great that we\u0027re receiving contributions directly from Silicon Labs. As Tomas already mentioned, we need to make a few changes before the patch can be merged. Do you plan to take the necessary steps for upstreaming? If not, please let me know and I\u0027ll take care of it. Would be nice if we could merge before 1.0 release. I have access to many EFM32 devices (series 0, 1, 2) for (regression) testing. So far, I\u0027ve already identified a few minor bugs, but other than that, the patch works on my series 2 devices.","commit_id":"fd3f8d869bfbd06d382ce92b545b04f126a40139"},{"author":{"_account_id":1002493,"name":"Jérôme Pouiller","email":"jerome.pouiller@silabs.com","username":"jerome-pouiller"},"change_message_id":"6b3446c6de4778b8dd6842eeab15a8a23f8d4e1f","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"b429d413_1e623d5b","in_reply_to":"1ee02ba2_35796c9c","updated":"2026-01-28 15:53:41.000000000","message":"I am going to introduce `struct efm32_msc_offsets` as Karl Palsson did in his patch. Then, I need a patch the bytecode depending if the target is Series 0/1 or Series 2. I don\u0027t know yet what is the best way to do this.","commit_id":"fd3f8d869bfbd06d382ce92b545b04f126a40139"},{"author":{"_account_id":1002493,"name":"Jérôme Pouiller","email":"jerome.pouiller@silabs.com","username":"jerome-pouiller"},"change_message_id":"6b3446c6de4778b8dd6842eeab15a8a23f8d4e1f","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"3f629814_79fc36ee","in_reply_to":"2a0b9634_4bd4a88c","updated":"2026-01-28 15:53:41.000000000","message":"I am going to check what I can do. Give me one or two weeks.","commit_id":"fd3f8d869bfbd06d382ce92b545b04f126a40139"}],"src/flash/nor/efr32-series2.c":[{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"72566c7e89256a73fce6c181a780258461441d46","unresolved":true,"context_lines":[{"line_number":1154,"context_line":"\t\tmsc_clken \u003d EFR32_CMU_REG_CLKEN1_MSC_MSK_16;"},{"line_number":1155,"context_line":"\t\tLOG_WARNING(\"Don\u0027t know EFR/EFM Gx family number, can\u0027t set MSC register. Use default values..\");"},{"line_number":1156,"context_line":"\t}"},{"line_number":1157,"context_line":"\tret \u003d target_write_u32(bank-\u003etarget,"},{"line_number":1158,"context_line":"\t\t\t       EFR32_CMU_REGBASE_NS + EFR32_CMU_REG_CLKEN1_SET,"},{"line_number":1159,"context_line":"\t\t\t       msc_clken);"},{"line_number":1160,"context_line":"\tif (ret !\u003d ERROR_OK) {"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"dee18f8e_072e9637","line":1157,"updated":"2026-01-29 09:28:32.000000000","message":"You must also activate the MSC clock before performing a write or erase operation. Otherwise, these operations will fail as soon as you reset the target *after* probing.","commit_id":"fd3f8d869bfbd06d382ce92b545b04f126a40139"},{"author":{"_account_id":1000853,"name":"Marc Schink","display_name":"Marc Schink","email":"dev@zapb.de","username":"zapb"},"change_message_id":"72566c7e89256a73fce6c181a780258461441d46","unresolved":true,"context_lines":[{"line_number":1182,"context_line":"\t\tbank-\u003esectors[i].offset \u003d i * efr32_mcu_info-\u003epage_size;"},{"line_number":1183,"context_line":"\t\tbank-\u003esectors[i].size \u003d efr32_mcu_info-\u003epage_size;"},{"line_number":1184,"context_line":"\t\tbank-\u003esectors[i].is_erased \u003d -1;"},{"line_number":1185,"context_line":"\t\tbank-\u003esectors[i].is_protected \u003d 1;"},{"line_number":1186,"context_line":"\t}"},{"line_number":1187,"context_line":""},{"line_number":1188,"context_line":"\tefr32_info-\u003eprobed[bank_index] \u003d true;"}],"source_content_type":"text/x-csrc","patch_set":1,"id":"5d3151bc_12fd4b62","line":1185,"updated":"2026-01-29 09:28:32.000000000","message":"This should be `-1`, I think that\u0027s also wrong in the efm32 driver.","commit_id":"fd3f8d869bfbd06d382ce92b545b04f126a40139"}]}