)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"76f032cf2c428a51e8d676dccb85b771ff351bfc","unresolved":false,"context_lines":[{"line_number":1,"context_line":"Parent:     c67b6ba6 (target: rename struct \u0027arm_reg\u0027 as \u0027arm_reg_t\u0027)"},{"line_number":2,"context_line":"Author:     JC Delaunay \u003cjean-christophe.delaunay@synacktiv.com\u003e"},{"line_number":3,"context_line":"AuthorDate: 2026-03-05 17:09:38 +0100"},{"line_number":4,"context_line":"Commit:     JC Delaunay \u003cjean-christophe.delaunay@synacktiv.com\u003e"},{"line_number":5,"context_line":"CommitDate: 2026-03-09 16:40:05 +0100"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"be5d6a77_70c648eb","line":2,"updated":"2026-03-10 10:24:05.000000000","message":"Hi JC, thanks for this patch and for you interest for OpenOCD.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"76f032cf2c428a51e8d676dccb85b771ff351bfc","unresolved":true,"context_lines":[{"line_number":12,"context_line":"\tsrc/target/cortex_a.h"},{"line_number":13,"context_line":"\tsrc/target/target.h"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"This commit adds watchpoints support for Cortex A/R targets."},{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"01978367_36bb2011","line":15,"updated":"2026-03-10 10:24:05.000000000","message":"I disagree with this sentence.\nWatchpoints are already supported by OpenOCD on Cortex A/R, while some feature is still missing.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1002499,"name":"Jean-Christophe Delaunay","display_name":"Jiss","email":"jean-christophe.delaunay@synacktiv.com","username":"Jissynacktiv","status":"Synacktiv"},"change_message_id":"68db310757ec027eecbb60879c3e544fe63e7dfe","unresolved":true,"context_lines":[{"line_number":12,"context_line":"\tsrc/target/cortex_a.h"},{"line_number":13,"context_line":"\tsrc/target/target.h"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"This commit adds watchpoints support for Cortex A/R targets."},{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"c5f5adfe_71d0b777","line":15,"in_reply_to":"01978367_36bb2011","updated":"2026-03-11 08:54:24.000000000","message":"That is true. I only took `gdb` case into account, my bad.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1002499,"name":"Jean-Christophe Delaunay","display_name":"Jiss","email":"jean-christophe.delaunay@synacktiv.com","username":"Jissynacktiv","status":"Synacktiv"},"change_message_id":"afa9043920529f42c297cd747115e8ec606e9818","unresolved":false,"context_lines":[{"line_number":12,"context_line":"\tsrc/target/cortex_a.h"},{"line_number":13,"context_line":"\tsrc/target/target.h"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"This commit adds watchpoints support for Cortex A/R targets."},{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"aad33528_e9c7087e","line":15,"in_reply_to":"c5f5adfe_71d0b777","updated":"2026-03-11 09:16:05.000000000","message":"Done","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"76f032cf2c428a51e8d676dccb85b771ff351bfc","unresolved":true,"context_lines":[{"line_number":13,"context_line":"\tsrc/target/target.h"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"This commit adds watchpoints support for Cortex A/R targets."},{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"9332672f_77aa6b28","line":18,"range":{"start_line":16,"start_character":0,"end_line":18,"end_character":11},"updated":"2026-03-10 10:24:05.000000000","message":"This is an \u0027optional\u0027 requirement for GDB, as the replies watch/rwatch/awatch are not compulsory. See\nhttps://www.sourceware.org/gdb/current/onlinedocs/gdb.html/Stop-Reply-Packets.html\n\nAnd when only one watchpoint is set, we already have a trivial fallback to send the reply to GDB. See implementation in `watchpoint_hit()`.\n\nI often use OpenOCD stand-alone, with no GDB. Mainly for reverse engineering, when I have no symbols, or I only have a stripped elf/bin file, GDB issues dangerous memory accesses to try to understand the context. Doing so, GDB can crash a secure embedded platform on illegal memory accesses. In such use cases I don\u0027t need OpenOCD to feed any reply to GDB and current implementation is already ok. \n\nSaid that, I consider excessive your approach to completely remove watchpoint support when capstone is not present!\nWatchpoint should always be supported, only `struct target_type::hit_watchpoint` should be populated on Cortex-A/R when capstone is present.\n\nIf only the function `cortex_a_hit_watchpoint()` needs capstone, probably makes sense to move it in a separate file that is compiled only when capstone is present. This could reduce the amount of `#if HAVE_CAPSTONE` in the code. To be verified.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"1a21cb51563328cbab7494dc5992f45f0c85d37d","unresolved":true,"context_lines":[{"line_number":13,"context_line":"\tsrc/target/target.h"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"This commit adds watchpoints support for Cortex A/R targets."},{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"18ac33a6_f4cb49b8","line":18,"range":{"start_line":16,"start_character":0,"end_line":18,"end_character":11},"in_reply_to":"3af1073e_9062e4ec","updated":"2026-03-11 13:44:01.000000000","message":"For the separate file, it\u0027s just a wish, don\u0027t know if worth to do it.\nFeel free to put your new code under `#if HAVE_CAPSTONE` in the same file `cortex_a.c`. It could be moved later, if really needed.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1002499,"name":"Jean-Christophe Delaunay","display_name":"Jiss","email":"jean-christophe.delaunay@synacktiv.com","username":"Jissynacktiv","status":"Synacktiv"},"change_message_id":"a9e1272d1dc4f45b040d6f8d7416928e08a03632","unresolved":true,"context_lines":[{"line_number":13,"context_line":"\tsrc/target/target.h"},{"line_number":14,"context_line":""},{"line_number":15,"context_line":"This commit adds watchpoints support for Cortex A/R targets."},{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"3af1073e_9062e4ec","line":18,"range":{"start_line":16,"start_character":0,"end_line":18,"end_character":11},"in_reply_to":"9332672f_77aa6b28","updated":"2026-03-11 09:22:30.000000000","message":"Once again, that is very true, I only considered `gdb` usecase, my bad. I will make the changes you mentionned:\n- restore watchpoint support even if openocd is not built with capstone support\n- create a separate file compiled when capstone is present","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"76f032cf2c428a51e8d676dccb85b771ff351bfc","unresolved":true,"context_lines":[{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"d962875c_fc8d51df","line":22,"range":{"start_line":19,"start_character":0,"end_line":22,"end_character":13},"updated":"2026-03-10 10:24:05.000000000","message":"Indeed!\nI also noticed it and I considered capstone as the way to go. But since it\u0027s optional, addressing such implementation was quite low in my priority list.\n\nLatest ARM DDI 0406C.d\nhttps://developer.arm.com/documentation/ddi0406/latest/\nin chapter C5.2.2 \"Effect of entering Debug state on CP15 registers and the DBGWFAR\" is quite confusing.\nI decrypt that WFAR is only useful on v7 Debug for \"asynchronous\" watchpoint, where the offset `-4` or `-8` should be applied.\nFor \"synchronous\" watchpoints and for v7.1 Debug, only the PC should/could be used.\nYour code instead only uses WFAR and always applies the offset.\n\nDo you have access to a Cortex-A/R that implements \"asynchronous\" watchpoints? My Cortex-A7 only generates \"synchronous\" ones. I need to find some other device for wider tests.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1002499,"name":"Jean-Christophe Delaunay","display_name":"Jiss","email":"jean-christophe.delaunay@synacktiv.com","username":"Jissynacktiv","status":"Synacktiv"},"change_message_id":"afa9043920529f42c297cd747115e8ec606e9818","unresolved":true,"context_lines":[{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"19d4d014_518596df","line":22,"range":{"start_line":19,"start_character":0,"end_line":22,"end_character":13},"in_reply_to":"0b3b122c_b02fc688","updated":"2026-03-11 09:16:05.000000000","message":"This is very strange, I based my implementation on `DDI 0460D r1p2` (https://developer.arm.com/documentation/ddi0460/d/Debug/Debug-exception/Effect-of-debug-exceptions-on-CP15-registers-and-DBGWFAR) where there asynchronous vs. synchronous is barely mentionned.\nThe target I made my tests on is a `Cortex R` and implementation required the `-4`/`-8` offsets for it to work as intended.\nCould you provide me the SoC version where you are seeing the \u0027synchronous\u0027 watchpoint? (or at least its family so that I can buy a devboard to test on my side).\nI will add the two statements to my tests to have a better understanding as this is also confusing to me.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"1a21cb51563328cbab7494dc5992f45f0c85d37d","unresolved":true,"context_lines":[{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"f87bb589_4758b4b4","line":22,"range":{"start_line":19,"start_character":0,"end_line":22,"end_character":13},"in_reply_to":"19d4d014_518596df","updated":"2026-03-11 13:44:01.000000000","message":"DDI 0460D is for Cortex-R5. Is this you are working on? What is the SoC part number?\n\nI think I can find around some very old Cortex-R4, I will check for it! The relevant chapter is similar as what you pointed above\nhttps://developer.arm.com/documentation/ddi0363/g/Debug/Debug-exception/Effect-of-debug-exceptions-on-CP15-registers-and-DBGWFAR\n\nI\u0027m currently using Cortex-A7 based STM32MP135 and STM32MP157.\n\nBut I believe we can also work in parallel, each on his SoC.\nWhen I started checking this WFAR story I made some crap patch to try to get the value from that register. Let me dig in my archeological git branches and I will return shortly.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"11e0addc12efb62c14c50864a728367b5fb9ca0c","unresolved":true,"context_lines":[{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"0b3b122c_b02fc688","line":22,"range":{"start_line":19,"start_character":0,"end_line":22,"end_character":13},"in_reply_to":"d962875c_fc8d51df","updated":"2026-03-10 10:55:46.000000000","message":"On this specific point I have tried to query ChatGPT to know if any available Cortex-A/R need this.\nThe answer is that all ARM standard cores only implement \"synchronous\" watchpoints, so no need for debugger to address \"asynchronous\" watchpoints! ARM proposes the asynchronous watchpoints as a feature for custom out-of-order or deeply pipelined implementations, where it might be difficult or costly to maintain full precision for data watchpoints.\n\nI asked also for some reference of the statement above, but it replies that it\u0027s extracted from the context, it\u0027s not stated directly from ARM.\nAns also every TRM of Cortex-A/R cores report that \"Watchpoint exceptions are precise with respect to the instruction stream\" that it consider as a synonym of \"synchronous\".\n\nI don\u0027t know how much reliable this answer is, but surely my Cortex-A7 only triggers synchronous exceptions.\nFYI, to discriminate v7 Debug from V7.1 Debug\n`if (((dpm-\u003edidr \u003e\u003e 16) \u0026 0xf) \u003c\u003d 4)`\nand for sync vs async (see DDI 0406C.d Table C11-22 \"Meaning of Method of Debug Entry values\")\n`if (DSCR_ENTRY(cortex_a-\u003ecpudbg_dscr) \u003d\u003d DSCR_ENTRY_PRECISE_WATCHPT)`","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"79edc9a6a1e960a27df728ca7677c8da2e7e5a04","unresolved":true,"context_lines":[{"line_number":16,"context_line":"Previous work on this subject implemented many structures and mechanisms"},{"line_number":17,"context_line":"but lacked the main part: how to associate a trigger with a specific"},{"line_number":18,"context_line":"watchpoint."},{"line_number":19,"context_line":"Indeed, Cortex A/R ref. manual states that on a watchpoint debug event,"},{"line_number":20,"context_line":"DFAR and IFAR hold \"Unpredictable value\". WFAR is set to the instruction"},{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"0775c05d_fa5e8c47","line":22,"range":{"start_line":19,"start_character":0,"end_line":22,"end_character":13},"in_reply_to":"f87bb589_4758b4b4","updated":"2026-05-01 17:08:02.000000000","message":"Today I received a newsletter from ARM advertising that their website now includes an AI based chat to query a \"virtual FAE\".\nSo I promptly asked which cores ARMv7-A/R implement sync vs async watchpoints.\nThe AI found that only the TRM of Cortex-R8 specifically report sync watchpoints. All the other TRM miss this info, so no way to get the cores\u0027s list.\nAs every AI, it gives a reasonable reply on which core could have sync vs async, but without factual information I cannot trust it.\nSo, supporting both cases is definitively needed.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"76f032cf2c428a51e8d676dccb85b771ff351bfc","unresolved":true,"context_lines":[{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."},{"line_number":26,"context_line":"Currently, LDR/STR variants are handled, along with LDM/STM and STRD/LDRD"},{"line_number":27,"context_line":"ones."},{"line_number":28,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"db26b360_7d457b10","line":25,"range":{"start_line":24,"start_character":33,"end_line":25,"end_character":64},"updated":"2026-03-10 10:24:05.000000000","message":"Frankly speaking, I would not rely on the code in `arm_disassembler.c`. While it\u0027s supposed to be functional, it was there for old arm cores and did not received much attention since ages. It could probably be dropped in the future.\nDo you think it could be simpler to only use capstone? I have not dig in the different implementations yet","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"1a21cb51563328cbab7494dc5992f45f0c85d37d","unresolved":true,"context_lines":[{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."},{"line_number":26,"context_line":"Currently, LDR/STR variants are handled, along with LDM/STM and STRD/LDRD"},{"line_number":27,"context_line":"ones."},{"line_number":28,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"4c3e3cbd_2c2f1f57","line":25,"range":{"start_line":24,"start_character":33,"end_line":25,"end_character":64},"in_reply_to":"d1d013ba_3af98330","updated":"2026-03-11 13:44:01.000000000","message":"I think that the capstone version is due to the default for the OS running Jenkins. I can ask for the version.\nWe unfortunately need to support the few versions for external libs, depending on what the Linux/BSD distros package. No idea how this should be handled for Windows.\nUnuntu 24 is still at v4.0.2\nhttps://repology.org/project/capstone/versions\n\nAnd capstone git has already tagged 6.0.0-Alpha7!\n\nI see the delta 4.0.2 vs 5.0.7 in `enum arm_insn`. Some reordering plus 39 new entries. But none of the new entries looks involved in memory operations, apart from ARM_INS_VLSTM and ARM_INS_VLLDM, that are probably not in any Cortex-A/R.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1002499,"name":"Jean-Christophe Delaunay","display_name":"Jiss","email":"jean-christophe.delaunay@synacktiv.com","username":"Jissynacktiv","status":"Synacktiv"},"change_message_id":"a00720e412cac020484ab98cbea45433b13e589a","unresolved":true,"context_lines":[{"line_number":21,"context_line":"which triggered the exception but there is no direct way to identify the"},{"line_number":22,"context_line":"related data."},{"line_number":23,"context_line":"To address this problem this commit computes the data manipulated by the"},{"line_number":24,"context_line":"faulty instruction. It relies on existing code for arm mode"},{"line_number":25,"context_line":"(arm_disassembler.c) and on the capstone library for thumb2 mode."},{"line_number":26,"context_line":"Currently, LDR/STR variants are handled, along with LDM/STM and STRD/LDRD"},{"line_number":27,"context_line":"ones."},{"line_number":28,"context_line":""}],"source_content_type":"text/x-gerrit-commit-message","patch_set":16,"id":"d1d013ba_3af98330","line":25,"range":{"start_line":24,"start_character":33,"end_line":25,"end_character":64},"in_reply_to":"db26b360_7d457b10","updated":"2026-03-11 08:52:06.000000000","message":"I think it would be less confusing to use capstone for both arm and thumb2 mode. I\u0027m a bit skeptical regarding capstone implementation though. Indeed, depending on capstone version (`4` or `5`), at least one structure (`enum arm_insn`) is different. I hope other things won\u0027t change in upcoming releases if we decide to use it fully. (On a sidenote, Capstone version is not `5` on `Jenkis`, which caused me a lot of trouble to debug. Should I create a separate issue?).","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5647ebc90cd9337961b93a0492e320e65b10a412","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":16,"id":"e0f67ba1_c0dee1fe","updated":"2026-03-11 16:52:23.000000000","message":"I have just pushed https://review.openocd.org/c/openocd/+/9505\nIt is an extract from some set of dirty patches I had locally to play with watchpoints.\nAs you can see, OpenOCD already saves the address of the instruction; no need to replicate it in `cortex_a_hit_watchpoint()` but just use `armv7a-\u003edpm.wp_addr`.\n\nWith this, you can go ahead working on your Cortex-R5, while I can test on Cortex-A7.","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"ca180f2e36e93ebf62e5c553807ac65b5f0c0063","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":16,"id":"4f0b8d6b_e25cfc11","updated":"2026-03-13 09:53:24.000000000","message":"I just found an old Cortex-R4 device in the archeology dept :-)\n\nIt is reported as v7 debug interface (DBGDIDR \u003d 0x77040013, \u003d\u003e Version, bits[19:16] \u003d 0b0100 \"ARMv7, v7 Debug architecture, with only the baseline CP14 registers implemented.\" )\n\nIt only hits synchronous watchpoints (DBGDSCR \u003d 0x0308612b, \u003d\u003e MOE, bits[5:2] \u003d 0b1010 \"Synchronous watchpoint debug event\").\n\nSo no luck to get a device using asynchronous watchpoints.\n\nWhat is the part number of the device you are using?","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"7cf710262dfa7726348c144e8c7f3d53abc67ca6","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":16,"id":"9da5f814_e80c6336","updated":"2026-05-01 19:34:34.000000000","message":"Jean Christophe,\nwhat happens on your Cortex-R4 if you have an assembly sequence \"load\" + \"jump\" and the watchpoint hits the load?\nArm reports that PC-8 or PC-4 is the instruction that hits the watchpoint, but the \"jump\" breaks the execution flow, changing the PC!\nAre we still able to catch the memory ld/st instruction?","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"},{"author":{"_account_id":1002499,"name":"Jean-Christophe Delaunay","display_name":"Jiss","email":"jean-christophe.delaunay@synacktiv.com","username":"Jissynacktiv","status":"Synacktiv"},"change_message_id":"a88102bb0750e563e1d8922246b607dfb60f6fce","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":16,"id":"728ea804_03936c29","updated":"2026-05-25 14:37:54.000000000","message":"Sorry, I was out for a long time. Let me dig into the codebase to refresh my memory and answer that afterwards","commit_id":"bdff6ee5c1fdc88816c20a30fe0b5eaeeecd5004"}]}