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algorithm for AM13E230X.\n\n**Patch order**: This is patch 1/3. Apply 9526 → 9527 → 9525.\n\n**Register addresses verified against datasheet (SPRSPC3)**:\n- NVMNW_BASE \u003d 0x40042000 (Table 7-1) ✓ matches FLASH_CONTROL_BASE\n- GSC_BASE \u003d 0x40046000 (Table 7-1) ✓ matches GSC_BASE\n\n**flash.h**: All FCTL register offsets from 0x40042000+0x1100 base look consistent.\nFCTL_STATCMD_CMDINPROGRESS\u003d0x4, CMDDONE\u003d0x1, CMDPASS\u003d0x2 bit assignments match standard NVMNW layout.\n\n**flash.c**: DSB/ISB around CMDEXEC write matches SDK\u0027s DL_FlashCTL_executeCommand requirement. Comment correctly explains why memory barriers are needed on Cortex-M33 write buffer.\n\nGSC semaphore logic in flash_request_gsc_semaphore(): reading FLSEMSTAT immediately after writing FLSEMREQ without __DSB — on Cortex-M33, APB peripheral write→read ordering is guaranteed by the architecture without explicit barriers. OK.\n\nCMDDATAINDEX \u003d (addr \u003e\u003e 4) \u0026 3 selects which 16-byte word within a 64-byte flash line. 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