)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"10e83d36_fa7bb00b","updated":"2026-06-24 10:32:47.000000000","message":"Hello liangzhen,\n\nthank you for preparing this patch.\n\nGiven the patch size, I have only managed a very brief review and am sending my initial comments and concerns.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"f886fdc9_9869e51f","updated":"2026-06-25 08:10:56.000000000","message":"Hello liangzhen,\nthank you for your replies. I have posted my reactions on all the threads.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"1906855107bb078faebf497e39a984afb2a9f14d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":3,"id":"26106fd9_8872461d","updated":"2026-06-23 14:17:44.000000000","message":"I like this rework, even if I\u0027m not able to fully review it.\nLet\u0027s wait for more feedback from risc-v experts.\nAlso, added Tomas as reviewer to get feedback wrt his work for DAP based risc-v debug.\nPer coding style, new code should use the `//` comment style for single line comments, but since this patch involves plenty of code move, maybe it\u0027s easier to keep it as it is.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"c8704de6_265c2ba1","updated":"2026-06-29 11:36:04.000000000","message":"@Jan Thank you for your suggestion, I have completed other changes except for the suggestions for `-dm-num` and `riscv-dtm`.","commit_id":"7dfa6620faf59b7ec07c39330a5e8f9a99682bf6"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0e8a4a4787bdd5dd0cbabb5487e44ab49f033440","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"2ef00e9e_40230651","updated":"2026-06-29 12:40:26.000000000","message":"I\u0027m checking if this can be easily split in few separate patches to simplify the review","commit_id":"210738f6d65e1f941889ab062c95a3b9e2b02a75"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c5fa49d85b0e626a084cdcea6a9250861865c671","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"188704b8_759ccdf4","updated":"2026-07-17 13:48:14.000000000","message":"Looks very interesting to me.","commit_id":"210738f6d65e1f941889ab062c95a3b9e2b02a75"}],"doc/openocd.texi":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":5067,"context_line":"@section DTM declaration (RISC-V targets)"},{"line_number":5068,"context_line":"@cindex DTM declaration"},{"line_number":5069,"context_line":""},{"line_number":5070,"context_line":"RISC-V Debug Transport Module (DTM) is no longer implicitly created"},{"line_number":5071,"context_line":"together with the target. It must be explicitly declared using the"},{"line_number":5072,"context_line":"@command{dtm create} command. For all RISC-V targets with DTM, the"},{"line_number":5073,"context_line":"option \"@option{-dtm} @var{dtm_name}\" has to be used instead of"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"9e6c16a1_3934aa73","line":5070,"updated":"2026-06-24 10:32:47.000000000","message":"I would recommend to present the information in a different order:\n\n- First describe the current state (how the DTM must be declared, etc.) without mentioning that it used to be different in the past.\n- Only then describe how to port old configuration files - what has changed. It may be helpful to also show a snippet from a Tcl file before vs after.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":5067,"context_line":"@section DTM declaration (RISC-V targets)"},{"line_number":5068,"context_line":"@cindex DTM declaration"},{"line_number":5069,"context_line":""},{"line_number":5070,"context_line":"RISC-V Debug Transport Module (DTM) is no longer implicitly created"},{"line_number":5071,"context_line":"together with the target. It must be explicitly declared using the"},{"line_number":5072,"context_line":"@command{dtm create} command. For all RISC-V targets with DTM, the"},{"line_number":5073,"context_line":"option \"@option{-dtm} @var{dtm_name}\" has to be used instead of"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"f0a3ac17_f13aa7c3","line":5070,"in_reply_to":"81eae369_f8151a75","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":5067,"context_line":"@section DTM declaration (RISC-V targets)"},{"line_number":5068,"context_line":"@cindex DTM declaration"},{"line_number":5069,"context_line":""},{"line_number":5070,"context_line":"RISC-V Debug Transport Module (DTM) is no longer implicitly created"},{"line_number":5071,"context_line":"together with the target. It must be explicitly declared using the"},{"line_number":5072,"context_line":"@command{dtm create} command. For all RISC-V targets with DTM, the"},{"line_number":5073,"context_line":"option \"@option{-dtm} @var{dtm_name}\" has to be used instead of"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"aa0230c8_56a1207e","line":5070,"in_reply_to":"9e6c16a1_3934aa73","updated":"2026-06-24 16:34:55.000000000","message":"Here I wrote this with reference to the DAP documentation. I\u0027m not very good at writing this, but I think it should be enough.\n\n\u003e Only then describe how to port old configuration files - what has changed. It may be helpful to also show a snippet from a Tcl file before vs after.\n\nI think it\u0027s enough to add a description of how the current RISC-V target is created in the @{section} `Target Configuration` . like:\n\n```\n--- a/doc/openocd.texi\n+++ b/doc/openocd.texi\n@@ -5353,6 +5353,14 @@ MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}\n MyTarget configure -event reset-init @{ myboard_reinit @}\n @end example\n\n+@example\n+dtm create mychip.dtm -chain-position mychip.cpu\n+target create MyTarget riscv -dtm mychip.dtm\n+MyTarget configure -work-area-phys 0x08000 -work-area-size 8096\n+MyTarget configure -event reset-deassert-pre @{ jtag_rclk 5 @}\n+MyTarget configure -event reset-init @{ myboard_reinit @}\n+@end example\n+\n You should specify a working area if you can; typically it uses some\n on-chip SRAM.\n Such a working area can speed up many things, including bulk\n\n```\n\nWhat do you think?","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":5067,"context_line":"@section DTM declaration (RISC-V targets)"},{"line_number":5068,"context_line":"@cindex DTM declaration"},{"line_number":5069,"context_line":""},{"line_number":5070,"context_line":"RISC-V Debug Transport Module (DTM) is no longer implicitly created"},{"line_number":5071,"context_line":"together with the target. It must be explicitly declared using the"},{"line_number":5072,"context_line":"@command{dtm create} command. For all RISC-V targets with DTM, the"},{"line_number":5073,"context_line":"option \"@option{-dtm} @var{dtm_name}\" has to be used instead of"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"81eae369_f8151a75","line":5070,"in_reply_to":"aa0230c8_56a1207e","updated":"2026-06-25 08:10:56.000000000","message":"I have added a concrete suggestion how the paragraph can be reworded - hope that helps to improve the doc further.\n\n\u003e I think it\u0027s enough to (...)\n\nSince the patch in its current form is backward incompatible, I suggest to approach this differently - not ask oneself \"what is enough\" but instead be proactive and think about \"what can I do to help users\".\n\nRemember, not all RISC-V users have good knowledge of OpenOCD, TCL and the configuration file internals. \n\n```\n@anchor{dtmdeclaration}\n@section DTM declaration (RISC-V targets)\n@cindex DTM declaration\n\nIn order to communicate with RISC-V targets, a RISC-V Debug Transport\nModule (DTM) must be explicitly created via @command{dtm create}.\nEach RISC-V target then has to be associated with its DTM via \nthe option \"@option{-dtm} @var{dtm_name}\".\n\nNote: Older versions of OpenOCD did not use standalone instances \nof RISC-V DTMs - the DTMs had been created implicitly. This is no\nlonger happening, and such configuration files need to be updated\nto the new approach, as shown below:\n\n@example\n# Old syntax for RISC-V target creation:\n\ntarget create my_cpu riscv -chain-position riscv_cpu.tap\n\n# New syntax:\n\nriscv_dtm create my_dtm -chain-position riscv_cpu.tap\ntarget create my_cpu riscv -dtm my_dtm\n@end example\n\n```","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":5101,"context_line":""},{"line_number":5102,"context_line":"When utilizing version 0.11 of the RISC-V Debug Specification,"},{"line_number":5103,"context_line":"@option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL"},{"line_number":5104,"context_line":"and DBUS registers, respectively."},{"line_number":5105,"context_line":"@end deffn"},{"line_number":5106,"context_line":""},{"line_number":5107,"context_line":"@deffn {Config Command} {dtm use_bscan_tunnel} width [type]"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"4a529a57_cd3eaf3e","line":5104,"updated":"2026-06-24 10:32:47.000000000","message":"Did I understand this paragraph correctly, please?\n\n```\nNote that when working with legacy hardware that implements \nversion 0.11 of the RISC-V Debug Specification, @option{dtmcs}\nrefers to DTMCONTROL JTAG IR and @option{dmi} refers to the DBUS\nJTAG IR.\n```","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":5101,"context_line":""},{"line_number":5102,"context_line":"When utilizing version 0.11 of the RISC-V Debug Specification,"},{"line_number":5103,"context_line":"@option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL"},{"line_number":5104,"context_line":"and DBUS registers, respectively."},{"line_number":5105,"context_line":"@end deffn"},{"line_number":5106,"context_line":""},{"line_number":5107,"context_line":"@deffn {Config Command} {dtm use_bscan_tunnel} width [type]"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"b6cc2dd4_85d498ce","line":5104,"in_reply_to":"4a529a57_cd3eaf3e","updated":"2026-06-24 16:34:55.000000000","message":"I think so.\nThe original description is like this, it’s just been migrated to the DTM declaration.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":5101,"context_line":""},{"line_number":5102,"context_line":"When utilizing version 0.11 of the RISC-V Debug Specification,"},{"line_number":5103,"context_line":"@option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL"},{"line_number":5104,"context_line":"and DBUS registers, respectively."},{"line_number":5105,"context_line":"@end deffn"},{"line_number":5106,"context_line":""},{"line_number":5107,"context_line":"@deffn {Config Command} {dtm use_bscan_tunnel} width [type]"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"ac1032af_10618466","line":5104,"in_reply_to":"637331b8_7ce110c9","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":5101,"context_line":""},{"line_number":5102,"context_line":"When utilizing version 0.11 of the RISC-V Debug Specification,"},{"line_number":5103,"context_line":"@option{dtmcs} and @option{dmi} set the IR values for the DTMCONTROL"},{"line_number":5104,"context_line":"and DBUS registers, respectively."},{"line_number":5105,"context_line":"@end deffn"},{"line_number":5106,"context_line":""},{"line_number":5107,"context_line":"@deffn {Config Command} {dtm use_bscan_tunnel} width [type]"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"637331b8_7ce110c9","line":5104,"in_reply_to":"b6cc2dd4_85d498ce","updated":"2026-06-25 08:10:56.000000000","message":"If that is correct understanding, please consider rewording the paragraph to make it very clear to readers (you can take the text from my comment and further adjust it, if needed).","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":5427,"context_line":"@item @code{-dtm} @var{dtm_name} -- names the DTM used to access"},{"line_number":5428,"context_line":"this target. @xref{dtmdeclaration,,DTM declaration}, on how to"},{"line_number":5429,"context_line":"create and manage DTM instances."},{"line_number":5430,"context_line":""},{"line_number":5431,"context_line":"@item @code{-endian} (@option{big}|@option{little}) -- specifies"},{"line_number":5432,"context_line":"whether the CPU uses big or little endian conventions"},{"line_number":5433,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"3a01a072_f4a0deca","line":5430,"updated":"2026-06-24 10:32:47.000000000","message":"Would it make sense to say that this is for RISC-V only?\n\n```\n@item @code{-dtm} @var{dtm_name} -- Used for RISC-V architecture.\nNames the Debug Transport Module (DTMú used to access\nthis RISC-V target. @xref{dtmdeclaration,,DTM declaration}, on how to\ncreate and manage DTM instances.\n```","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":5427,"context_line":"@item @code{-dtm} @var{dtm_name} -- names the DTM used to access"},{"line_number":5428,"context_line":"this target. @xref{dtmdeclaration,,DTM declaration}, on how to"},{"line_number":5429,"context_line":"create and manage DTM instances."},{"line_number":5430,"context_line":""},{"line_number":5431,"context_line":"@item @code{-endian} (@option{big}|@option{little}) -- specifies"},{"line_number":5432,"context_line":"whether the CPU uses big or little endian conventions"},{"line_number":5433,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"ee1e663d_3091d072","line":5430,"in_reply_to":"12c9210a_fb7c6545","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":5427,"context_line":"@item @code{-dtm} @var{dtm_name} -- names the DTM used to access"},{"line_number":5428,"context_line":"this target. @xref{dtmdeclaration,,DTM declaration}, on how to"},{"line_number":5429,"context_line":"create and manage DTM instances."},{"line_number":5430,"context_line":""},{"line_number":5431,"context_line":"@item @code{-endian} (@option{big}|@option{little}) -- specifies"},{"line_number":5432,"context_line":"whether the CPU uses big or little endian conventions"},{"line_number":5433,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"e14b68bc_231ab781","line":5430,"in_reply_to":"3a01a072_f4a0deca","updated":"2026-06-24 16:34:55.000000000","message":"I think it\u0027s okay, I will make changes later.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":5427,"context_line":"@item @code{-dtm} @var{dtm_name} -- names the DTM used to access"},{"line_number":5428,"context_line":"this target. @xref{dtmdeclaration,,DTM declaration}, on how to"},{"line_number":5429,"context_line":"create and manage DTM instances."},{"line_number":5430,"context_line":""},{"line_number":5431,"context_line":"@item @code{-endian} (@option{big}|@option{little}) -- specifies"},{"line_number":5432,"context_line":"whether the CPU uses big or little endian conventions"},{"line_number":5433,"context_line":""}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"12c9210a_fb7c6545","line":5430,"in_reply_to":"e14b68bc_231ab781","updated":"2026-06-25 08:10:56.000000000","message":"Thanks.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":5480,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5481,"context_line":"to separate access ports of the same DAP."},{"line_number":5482,"context_line":""},{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"ac06697e_15c9bcde","line":5483,"updated":"2026-06-24 10:32:47.000000000","message":"As already discussed in [this Github thread](https://github.com/riscv-collab/riscv-openocd/issues/1147#issuecomment-4739138457), I would prefer to use debug module\u0027s base address instead of ordinal number of the debug module.\n\nThat is, I would prefer to not have `-dm-num` at all and instead keep using the existing `-dbgbase`.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"c61ab8d7b46ae8bf8b73c3bdca470d43a03e1b6a","unresolved":true,"context_lines":[{"line_number":5480,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5481,"context_line":"to separate access ports of the same DAP."},{"line_number":5482,"context_line":""},{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"d800cca4_26c85342","line":5483,"in_reply_to":"42db904e_8ce021fe","updated":"2026-07-20 05:43:45.000000000","message":"Hi Tomas,\n\nthank you for your feedback.\n\n\u003e It makes cfg file creation more difficult and may impose problems when a vendor changes DMI layout between hw versions or in a family of similar RV CPUs.\n\nAt the same time, -dbgbase makes the config files more explicit, and I do see a value in that, too. \n\nWhen the hardware changes this way, I would prefer to get notified about that change - instead of keep using the original configuration file which might have become outdated in other aspects, too.\n\nNevertheless, I don\u0027t feel strongly. Please proceed with whichever solution the majority of reviewers agree on.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"change_message_id":"c5fa49d85b0e626a084cdcea6a9250861865c671","unresolved":true,"context_lines":[{"line_number":5480,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5481,"context_line":"to separate access ports of the same DAP."},{"line_number":5482,"context_line":""},{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"42db904e_8ce021fe","line":5483,"in_reply_to":"6459713d_d0e5978f","updated":"2026-07-17 13:48:14.000000000","message":"Jan,\nI have read whole GitHub discussion https://github.com/riscv-collab/riscv-openocd/issues/1147#issuecomment-4739138457\nI would be cautious with explicit -dbgbase to be the only way to address a particular DM. It makes cfg file creation more difficult and also may impose problems when a vendor changes DMI layout between hw versions or in a family of similar RV CPUs. Such change would be transparent if the debugger uses -dm-num as an ordinal in the nextdm linked list.\n\nI see good analogy in Cortex-A / aarch64 - either define -dbgbase directly or let OpenOCD read ROM tables and look for the n-th core desc where n is defined by -coreid","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":5480,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5481,"context_line":"to separate access ports of the same DAP."},{"line_number":5482,"context_line":""},{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"cde8ac3e_09917a27","line":5483,"in_reply_to":"ac06697e_15c9bcde","updated":"2026-06-24 16:34:55.000000000","message":"The current config file still mainly uses `-dbgbase`, this patch didn’t change `-dbgbase` to `-dm-num`, and it also makes sense to optionally introduce `-dm-num`, right?\n1. Even if the user doesn\u0027t know dbgbase for now, they can still write the config file.\n2. We can use `@var{dtm_name} dmbase \u003cdm-num\u003e` to get dbgbase, so introducing `-dm-num` seems reasonable too, right?\n\n\u003e  I believe that the configuration file should use the identifiers designated by \u003e \u003e the RISC-V debug specification for that purpose - that is, debug module addresses \u003e　and hart numbers (not mhartid, not ordinal number of the debug module ...).\n\n3. I believe that RISC-V debug specification doesn’t strictly state that the debug module address is a unique identifier. \n\n\nRISC-V debug specification in (https://docs.riscv.org/reference/debug/v1.0/debug_module.html#dmi) say that: \"The bottom of the address space is used for the first (and usually only) DM. Extra space can be used for custom debug devices, other cores, additional DMs, etc. If there are additional DMs on this DMI, the base address of the next DM in the DMI address space is given in nextdm.“\n\nFor example, ”the first (and usually the only) DM“, and the ”next DM“, doesn\u0027t that already include the meaning of the number of the debug module?","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":5480,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5481,"context_line":"to separate access ports of the same DAP."},{"line_number":5482,"context_line":""},{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"6459713d_d0e5978f","line":5483,"in_reply_to":"cde8ac3e_09917a27","updated":"2026-06-25 08:10:56.000000000","message":"\u003e I believe that RISC-V debug specification doesn’t strictly state that the debug module address is a unique identifier. \n\nThe debug module\u0027s address is its unique identifier in principle.\n\nI would recommend to not introduce other ways how to identify debug modules - that is, not have different ways for doing the same thing, unless there is a very strong reason for it.\n\nIn another words, my preference would be to keep using `-dbgbase` as is, and not introduce `-dm-num`.\n\nAnyway, let\u0027s also wait for opinion of others.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5487,"context_line":"to separate access ports of the same DTM."},{"line_number":5488,"context_line":""},{"line_number":5489,"context_line":"@item @code{-dbgbase} @var{dbg_base_address} -- set the base address of the"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"00a55ebd_e4d9bbd3","line":5486,"updated":"2026-06-24 10:32:47.000000000","message":"I think a more accurate formulation would be: `Use this option with systems where multiple independent debug modules are connected to the debug bus of the same DTM.`","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5487,"context_line":"to separate access ports of the same DTM."},{"line_number":5488,"context_line":""},{"line_number":5489,"context_line":"@item @code{-dbgbase} @var{dbg_base_address} -- set the base address of the"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"2c4af0a5_328b52c4","line":5486,"in_reply_to":"00a55ebd_e4d9bbd3","updated":"2026-06-24 16:34:55.000000000","message":"I will make changes later.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5487,"context_line":"to separate access ports of the same DTM."},{"line_number":5488,"context_line":""},{"line_number":5489,"context_line":"@item @code{-dbgbase} @var{dbg_base_address} -- set the base address of the"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"c05996f3_47440ad2","line":5486,"in_reply_to":"2c4af0a5_328b52c4","updated":"2026-06-25 08:10:56.000000000","message":"Thanks.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":5483,"context_line":"@item @code{-dm-num} @var{dm_number} -- set RISC-V Debug Module for target."},{"line_number":5484,"context_line":"On version 0.13/1.0 of the RISC-V Debug Specification @var{dm_number} is the"},{"line_number":5485,"context_line":"numeric index of the DTM DM the target is connected to."},{"line_number":5486,"context_line":"Use this option with systems where multiple, independent cores are connected"},{"line_number":5487,"context_line":"to separate access ports of the same DTM."},{"line_number":5488,"context_line":""},{"line_number":5489,"context_line":"@item @code{-dbgbase} @var{dbg_base_address} -- set the base address of the"}],"source_content_type":"text/x-texinfo","patch_set":3,"id":"ad262bee_2e5fc82d","line":5486,"in_reply_to":"c05996f3_47440ad2","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"}],"src/openocd.c":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":148,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":149,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":150,"context_line":""},{"line_number":151,"context_line":"\tretval \u003d command_run_line(CMD_CTX, \"dtm init\");"},{"line_number":152,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":153,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":154,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"3e068325_7dc5a151","line":151,"updated":"2026-06-24 10:32:47.000000000","message":"Since this is RISC-V specific, would it make sense to use `riscv_dtm` instead of just `dtm` in all the commands and identifiers?","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":148,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":149,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":150,"context_line":""},{"line_number":151,"context_line":"\tretval \u003d command_run_line(CMD_CTX, \"dtm init\");"},{"line_number":152,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":153,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":154,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"8143230a_9b6fcb43","line":151,"in_reply_to":"3e068325_7dc5a151","updated":"2026-06-24 16:34:55.000000000","message":"I personally don’t like adding the riscv prefix when writing configs. It’s already described in the documentation, so let\u0027s keep it, OK?","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":148,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":149,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":150,"context_line":""},{"line_number":151,"context_line":"\tretval \u003d command_run_line(CMD_CTX, \"dtm init\");"},{"line_number":152,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":153,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":154,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"b4c31986_36259816","line":151,"in_reply_to":"8143230a_9b6fcb43","updated":"2026-06-25 08:10:56.000000000","message":"I strongly prefer to use `riscv_dtm` since the Debug Transport Module is a RISC-V specific concept.\n\nAlso as a reader of config files, I would prefer to read `riscv_dtm` which allow make me to look it up and understand the meaning of the command more clearly.\n\nAnyway, I would like to ask other reviewers for their opinion on the names.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"0e8a4a4787bdd5dd0cbabb5487e44ab49f033440","unresolved":true,"context_lines":[{"line_number":148,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":149,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":150,"context_line":""},{"line_number":151,"context_line":"\tretval \u003d command_run_line(CMD_CTX, \"dtm init\");"},{"line_number":152,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":153,"context_line":"\t\treturn ERROR_FAIL;"},{"line_number":154,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"ea2fa942_395d4d12","line":151,"in_reply_to":"b4c31986_36259816","updated":"2026-06-29 12:40:26.000000000","message":"DAP has been an ARM specification but we didn\u0027t called it `arm_dap`.\nI don\u0027t know if it exists an open source DAP implementation, but clearly there are open DTM implementations. If someone wants to implement a JTAG port to bus interface for his own project, I think it would be easier to reuse a DTM then a DAP.\n\nI see some trend in OpenOCD to split multi-word commands in independent words.\nSee https://review.openocd.org/c/openocd/+/6333\nIt would be awful to late modify this as `riscv dtm`\n\nSaid that, either `dtm` or `riscv_dtm` are both fine for me as they are not run-time commands but config ones, with a little preference for `dtm` alone.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"}],"src/target/riscv/batch.c":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":291,"context_line":"\tif (batch-\u003ewas_run)"},{"line_number":292,"context_line":"\t\tadd_idle_before_batch(batch, start_idx, delays);"},{"line_number":293,"context_line":""},{"line_number":294,"context_line":"\tLOG_DEBUG(\"%s: running batch of scans [%zu, %zu)\","},{"line_number":295,"context_line":"\t\triscv_dtm_name(batch-\u003edtm), start_idx, batch-\u003eused_scans);"},{"line_number":296,"context_line":""},{"line_number":297,"context_line":"\tunsigned int delay \u003d 0 /* to silence maybe-uninitialized */;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"06c2a6ac_d71171a4","line":294,"updated":"2026-06-24 10:32:47.000000000","message":"It looks like macros `LOG_RISCV_BATCH_DEBUG`, `LOG_RISCV_BATCH_WARNING` etc. can be created.\n\n(Or similar names: `LOG_RISCV_DTM_DEBUG` ...)","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":291,"context_line":"\tif (batch-\u003ewas_run)"},{"line_number":292,"context_line":"\t\tadd_idle_before_batch(batch, start_idx, delays);"},{"line_number":293,"context_line":""},{"line_number":294,"context_line":"\tLOG_DEBUG(\"%s: running batch of scans [%zu, %zu)\","},{"line_number":295,"context_line":"\t\triscv_dtm_name(batch-\u003edtm), start_idx, batch-\u003eused_scans);"},{"line_number":296,"context_line":""},{"line_number":297,"context_line":"\tunsigned int delay \u003d 0 /* to silence maybe-uninitialized */;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"40ed43b1_2d457ddf","line":294,"updated":"2026-06-24 10:32:47.000000000","message":"Please, can you make sure that the name of the target remains printed in the log - it is important for troubeshooting.\n\nI don\u0027t mind the exact form:\n- the target name can be printed for the whole batch,\n- or the target name can be printed for individual transactions in the batch,\n- or some other form.\n\nIn any case, the association between transactions and targets (where we know it) should remain in the log.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":291,"context_line":"\tif (batch-\u003ewas_run)"},{"line_number":292,"context_line":"\t\tadd_idle_before_batch(batch, start_idx, delays);"},{"line_number":293,"context_line":""},{"line_number":294,"context_line":"\tLOG_DEBUG(\"%s: running batch of scans [%zu, %zu)\","},{"line_number":295,"context_line":"\t\triscv_dtm_name(batch-\u003edtm), start_idx, batch-\u003eused_scans);"},{"line_number":296,"context_line":""},{"line_number":297,"context_line":"\tunsigned int delay \u003d 0 /* to silence maybe-uninitialized */;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"dec2ed24_c7d64e07","line":294,"in_reply_to":"06c2a6ac_d71171a4","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":291,"context_line":"\tif (batch-\u003ewas_run)"},{"line_number":292,"context_line":"\t\tadd_idle_before_batch(batch, start_idx, delays);"},{"line_number":293,"context_line":""},{"line_number":294,"context_line":"\tLOG_DEBUG(\"%s: running batch of scans [%zu, %zu)\","},{"line_number":295,"context_line":"\t\triscv_dtm_name(batch-\u003edtm), start_idx, batch-\u003eused_scans);"},{"line_number":296,"context_line":""},{"line_number":297,"context_line":"\tunsigned int delay \u003d 0 /* to silence maybe-uninitialized */;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"6698ac45_c3c4e76a","line":294,"in_reply_to":"40ed43b1_2d457ddf","updated":"2026-06-24 16:34:55.000000000","message":"To ensure that only the DTM is created, the DTM can use the dmi interface, but the target variable must be removed with the current changes. So we can\u0027t print out the target name here, but we can totally figure out which target it belongs to from the previous logs, right?","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":291,"context_line":"\tif (batch-\u003ewas_run)"},{"line_number":292,"context_line":"\t\tadd_idle_before_batch(batch, start_idx, delays);"},{"line_number":293,"context_line":""},{"line_number":294,"context_line":"\tLOG_DEBUG(\"%s: running batch of scans [%zu, %zu)\","},{"line_number":295,"context_line":"\t\triscv_dtm_name(batch-\u003edtm), start_idx, batch-\u003eused_scans);"},{"line_number":296,"context_line":""},{"line_number":297,"context_line":"\tunsigned int delay \u003d 0 /* to silence maybe-uninitialized */;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"3655c0b6_32d713f9","line":294,"in_reply_to":"423ec546_21046c5a","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":291,"context_line":"\tif (batch-\u003ewas_run)"},{"line_number":292,"context_line":"\t\tadd_idle_before_batch(batch, start_idx, delays);"},{"line_number":293,"context_line":""},{"line_number":294,"context_line":"\tLOG_DEBUG(\"%s: running batch of scans [%zu, %zu)\","},{"line_number":295,"context_line":"\t\triscv_dtm_name(batch-\u003edtm), start_idx, batch-\u003eused_scans);"},{"line_number":296,"context_line":""},{"line_number":297,"context_line":"\tunsigned int delay \u003d 0 /* to silence maybe-uninitialized */;"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"423ec546_21046c5a","line":294,"in_reply_to":"6698ac45_c3c4e76a","updated":"2026-06-25 08:10:56.000000000","message":"\u003e we can totally figure out which target it belongs to from the previous logs, right?\n\nThe detailed RISC-V log (`-d`) is already very verbose and complicated as is. \n\nSo while users can certainly decipher what target the transactions belong to, as you point out, I would prefer if they did not need to do that, and instead save the time and energy for the actual problem they are working on.\n\n\u003e the target variable must be removed with the current changes\n\nI can see that the target is passed to every call to `riscv_batch_add_dm_write()` and `riscv_batch_add_dm_read()`. \n\nSo you can record it as an optional piece of information for every transaction of the batch. And when printing the contents of the batch, you can also print the name of the target - for transactions were we know it.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"}],"src/target/riscv/riscv-013.c":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":232,"context_line":"\t * Values are incremented every time an access results in a busy"},{"line_number":233,"context_line":"\t * response."},{"line_number":234,"context_line":"\t */"},{"line_number":235,"context_line":"\tstruct riscv_scan_delays learned_delays;"},{"line_number":236,"context_line":""},{"line_number":237,"context_line":"\tstruct ac_cache ac_not_supported_cache;"},{"line_number":238,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"9f2f23d3_52bb86e9","side":"PARENT","line":235,"updated":"2026-06-24 10:32:47.000000000","message":"I am afraid that the delays are affected by both the DTM and the target (for instance, the performance of the memory access in the given hart).\n\nSo I believe the delays should stay at the target level, and not be moved to the DTM.","commit_id":"9c533894c2999a3c4c057f483b71c721ec21d2db"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":232,"context_line":"\t * Values are incremented every time an access results in a busy"},{"line_number":233,"context_line":"\t * response."},{"line_number":234,"context_line":"\t */"},{"line_number":235,"context_line":"\tstruct riscv_scan_delays learned_delays;"},{"line_number":236,"context_line":""},{"line_number":237,"context_line":"\tstruct ac_cache ac_not_supported_cache;"},{"line_number":238,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"fa116de8_30ef6841","side":"PARENT","line":235,"in_reply_to":"3bac99ab_248a97d0","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"9c533894c2999a3c4c057f483b71c721ec21d2db"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":232,"context_line":"\t * Values are incremented every time an access results in a busy"},{"line_number":233,"context_line":"\t * response."},{"line_number":234,"context_line":"\t */"},{"line_number":235,"context_line":"\tstruct riscv_scan_delays learned_delays;"},{"line_number":236,"context_line":""},{"line_number":237,"context_line":"\tstruct ac_cache ac_not_supported_cache;"},{"line_number":238,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"3bac99ab_248a97d0","side":"PARENT","line":235,"in_reply_to":"8b58a0b7_c4687d7b","updated":"2026-06-25 08:10:56.000000000","message":"The `struct riscv_scan_delays` as of now contains these 4 items:\n\n```\nstruct riscv_scan_delays {\n\tunsigned int base_delay;\n\tunsigned int ac_delay;\n\tunsigned int sb_read_delay;\n\tunsigned int sb_write_delay;\n};\n```\n\nEach of the delays is affected by the performance different components in the system:\n\n- `base_delay` - Base delay for all transactions. Most likely determined by the performance of the DTM (+ maybe DM).\n- `ac_delay` - Abstract command delay, determined likely by the performance of the DM + performance of the the hart.\n- `sb_read_delay`, `sb_write_delay` - Delays for system bus access. Determined probably by the performance of the DM and the actual memory.\n\nIn another words, other components of the system contribute to the delays - e.g. different harts and different DMs may need different delays.\n\nFor that reason, having just a single centralized set of delays inside the DTM  does not look correct.\n\nIMO, the safest course of action would be to keep the delays at each target, as it is now, and pass the delay values to the DTM as needed.","commit_id":"9c533894c2999a3c4c057f483b71c721ec21d2db"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":232,"context_line":"\t * Values are incremented every time an access results in a busy"},{"line_number":233,"context_line":"\t * response."},{"line_number":234,"context_line":"\t */"},{"line_number":235,"context_line":"\tstruct riscv_scan_delays learned_delays;"},{"line_number":236,"context_line":""},{"line_number":237,"context_line":"\tstruct ac_cache ac_not_supported_cache;"},{"line_number":238,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":3,"id":"8b58a0b7_c4687d7b","side":"PARENT","line":235,"in_reply_to":"9f2f23d3_52bb86e9","updated":"2026-06-24 16:34:55.000000000","message":"To ensure that only the DTM is created, the DTM can use the dmi interface, but the target variable must be removed with the current changes. I have limited understanding of this part of the batch code, and if the delays should stay at the target level, then we would need to create other dmi interfaces that rely only on the DTM, which seems a bit odd to me.","commit_id":"9c533894c2999a3c4c057f483b71c721ec21d2db"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"95c86fd9279a78b2bc92e30cc50fef7f7aacc2f9","unresolved":true,"context_lines":[{"line_number":2558,"context_line":"\t\t\tdtm-\u003eis_dtm_owns_learned_delays \u003d false;"},{"line_number":2559,"context_line":"\t\t}"},{"line_number":2560,"context_line":"\t\tRISCV013_INFO(info);"},{"line_number":2561,"context_line":"\t\tdtm-\u003elearned_delays \u003d \u0026info-\u003elearned_delays;"},{"line_number":2562,"context_line":"\t}"},{"line_number":2563,"context_line":"}"},{"line_number":2564,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":8,"id":"d625d245_7645ab71","line":2561,"updated":"2026-06-29 15:51:17.000000000","message":"I\u0027m looking for splitting this big patch in something more readable and maintanable. I just sent out the initial part for reference.\n\nThen, I got here!\nCan you please explain what\u0027s the logic behind this change on `learned_delays`? It\u0027s quite confusing.\n\nThe original code only has `riscv013_info_t::learned_delays`.\nThe new code does not move it, but adds a new `struct riscv_dtm::learned_delays` that is a pointer.\nThen you add some logic to either let the latter point to the original one, or to allocate it and keep track of the allocation through `is_dtm_owns_learned_delays`.\n\nIn `handle_dtm_create()` it is `calloc()` and then `free()` in `dtm_cleanup_all()`. Ok, symmetric.\nBut as soon as `batch_run()` is executed, it is `free()` and replaced by `riscv013_info_t::learned_delays`.\nAnd every following call to `batch_run()` runs again test for `free()` and assignment.\n\nPlease check my split in the https://review.openocd.org/c/openocd/+/9766","commit_id":"210738f6d65e1f941889ab062c95a3b9e2b02a75"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"179c4eb6a19e1183dd9c90b18b127f7c9ced1441","unresolved":true,"context_lines":[{"line_number":2558,"context_line":"\t\t\tdtm-\u003eis_dtm_owns_learned_delays \u003d false;"},{"line_number":2559,"context_line":"\t\t}"},{"line_number":2560,"context_line":"\t\tRISCV013_INFO(info);"},{"line_number":2561,"context_line":"\t\tdtm-\u003elearned_delays \u003d \u0026info-\u003elearned_delays;"},{"line_number":2562,"context_line":"\t}"},{"line_number":2563,"context_line":"}"},{"line_number":2564,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":8,"id":"a17c629b_10562cbb","line":2561,"in_reply_to":"1752b059_d8fc7b29","updated":"2026-07-01 08:40:11.000000000","message":"Thank you for splitting this patch into a series of smaller ones. 👍\n\nI will be able to get back to the review around Thursday next week.","commit_id":"210738f6d65e1f941889ab062c95a3b9e2b02a75"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"b712293828f771014e9145a028f2584815d78ce6","unresolved":true,"context_lines":[{"line_number":2558,"context_line":"\t\t\tdtm-\u003eis_dtm_owns_learned_delays \u003d false;"},{"line_number":2559,"context_line":"\t\t}"},{"line_number":2560,"context_line":"\t\tRISCV013_INFO(info);"},{"line_number":2561,"context_line":"\t\tdtm-\u003elearned_delays \u003d \u0026info-\u003elearned_delays;"},{"line_number":2562,"context_line":"\t}"},{"line_number":2563,"context_line":"}"},{"line_number":2564,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":8,"id":"1752b059_d8fc7b29","line":2561,"in_reply_to":"d625d245_7645ab71","updated":"2026-06-29 16:38:50.000000000","message":"please see Jan\u0027s comment:\n\n```\nThe struct riscv_scan_delays as of now contains these 4 items:\n\nstruct riscv_scan_delays {\n    unsigned int base_delay;\n    unsigned int ac_delay;\n    unsigned int sb_read_delay;\n    unsigned int sb_write_delay;\n};\n\nEach of the delays is affected by the performance different components in the system:\n\nbase_delay - Base delay for all transactions. Most likely determined by the performance of the DTM (+ maybe DM).\nac_delay - Abstract command delay, determined likely by the performance of the DM + performance of the the hart.\nsb_read_delay, sb_write_delay - Delays for system bus access. Determined probably by the performance of the DM and the actual memory.\nIn another words, other components of the system contribute to the delays - e.g. different harts and different DMs may need different delays.\n\nFor that reason, having just a single centralized set of delays inside the DTM does not look correct.\n\nIMO, the safest course of action would be to keep the delays at each target, as it is now, and pass the delay values to the DTM as needed.\n```\n\n1. In the case of only creating DTM, I need introduced `struct riscv_dtm::learned_delays` in the new code to use dmi function.\n\n2. In order to keep the `riscv013_info_t::learned_delays` at each target, as soon as batch_run() is executed, `batch_pass_scan_delays()` pass `riscv013_info_t::learned_delays` to `struct riscv_dtm::learned_delays`.\n\n3. `riscv_scan_increase_delay(dtm-\u003elearned_delays, delay_type)` needs to act on the `riscv013_info_t::learned_delays` at each target, so `struct riscv_dtm::learned_delays` is a pointer.\n\nThis is my solution. If any other good suggestions, please let me know.","commit_id":"210738f6d65e1f941889ab062c95a3b9e2b02a75"}],"src/target/riscv/riscv_dtm.c":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"1906855107bb078faebf497e39a984afb2a9f14d","unresolved":false,"context_lines":[{"line_number":128,"context_line":""},{"line_number":129,"context_line":"static struct scan_field _bscan_tunnel_data_register_select_dmi[] \u003d {"},{"line_number":130,"context_line":"\t\t{"},{"line_number":131,"context_line":"\t\t\t.num_bits \u003d 3,"},{"line_number":132,"context_line":"\t\t\t.out_value \u003d bscan_zero,"},{"line_number":133,"context_line":"\t\t\t.in_value \u003d NULL,"},{"line_number":134,"context_line":"\t\t},"}],"source_content_type":"text/x-csrc","patch_set":3,"id":"28c70e7c_4890d12c","line":131,"updated":"2026-06-23 14:17:44.000000000","message":"Odd indentation.\nBut two TABs where already in the original code. Let\u0027s keep it as is!","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"}],"tcl/board/sifive/e51-arty.cfg":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"5d04fb87_d8ee5d59","line":11,"updated":"2026-06-24 10:32:47.000000000","message":"1) Does it make sense to use the name `riscv_dtm`instead of just `dtm`?\n\n2) In the RISC-V debug spec, only the JTAG-based DTM is currently specified, but the spec leaves the door open for other types of DTMs (standardized or even custom DTMs). So you may consider adding a parameter `-dtm-type` to account for that. The only accepted value as of now would be `jtag` and that would allow other DTM types to be created in the future.\n\n```\nriscv_dtm create $_CHIPNAME.dtm -dtm-type jtag -chain-position $_CHIPNAME.cpu\n```","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"079929e660469aac49d05412c5407772978ee251","unresolved":true,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"970dbfd4_7e919d71","line":11,"updated":"2026-06-24 10:32:47.000000000","message":"The introduction of `dtm create` is backward incompatible, which concerns me. \n\nIt breaks all existing RISC-V configuration files, so users may become confused (or even upset).\n\n1) Should backward compatibility be preserved, at least for a single release? (But that would make the implementation more complicated.)\n\n2) Alternatively, could at least a clear message be printed to the users how to update their config files?\n\nWhat do you think?","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"63738c38_e7353e9a","line":11,"in_reply_to":"5d04fb87_d8ee5d59","updated":"2026-06-24 16:34:55.000000000","message":"1) It\u0027s already been explained.\n2) Introducing this option is fine, but since there is no related code at the moment, is it really necessary to introduce this extra configuration?","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"7c0b4fcf_ee0203a5","line":11,"in_reply_to":"63738c38_e7353e9a","updated":"2026-06-25 08:10:56.000000000","message":"1) I am sorry but I still maintain the opinion that `riscv_dtm` is clearer name than just `dtm` - for the users\u0027 benefit. But as mentioned in the other thread, I would like to ask for opinion of others.\n\n2) I believe the `-dtm-type` option is appropriate for two reasons:\n\n- i) The term \"DTM\" alone is an abstract concept that refers to an (abstract) bridge between an arbitrary interface and the DMI bus. Only when you say \"JTAG DTM\", you refer to an actual protocol / actual hardware device that is specified in the RISC-V debug spec.\n\n- ii) It is a good engineering practice to design protocols and interfaces from the start in such a way that they allow future extensions - in this case, adding different DTM types.","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"beef110c_ff3bc365","line":11,"in_reply_to":"7c0b4fcf_ee0203a5","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"06f1f68a09c46e8b37d7731b32c40fadabb0c58a","unresolved":true,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"e305e14d_02ab0a23","line":11,"in_reply_to":"970dbfd4_7e919d71","updated":"2026-06-24 16:34:55.000000000","message":"\u003e It breaks all existing RISC-V configuration files, so users may become confused 》 \u003e (or even upset).\n\nIt\u0027s just a small change for now, just introducing the DTM declaration. Considering RISC-V in DAP+AP based SoC. The RISC-V target configuration can be one of the following two situations:\n\nFor RISC-V in DTM:\n```\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id xxx\n\ndtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu\ntarget create $_CHIPNAME.cpu riscv -dtm $_CHIPNAME.dtm\n\n```\n\nFor RISC-V in DAP:\n\n```\njtag newtap $_CHIPNAME cpu -irlen 5 -expected-id xxx\n\ndap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu\n\ntarget create $_TARGETNAME riscv -dap $_CHIPNAME.dap\n```\n\nI think introducing a DTM instance is a good direction. Like target examine fail, it seems like I can\u0027t do more anything else right now, but actually we should be able to access the DM, we could use sysbus to access memory and get some information.\n\n\u003e 2) Alternatively, could at least a clear message be printed to the users how to \u003e \u003e update their config files?\n\nplease see:\n```\n\t\t} else if (target-\u003ehas_dtm) {\n\t\t\tif (!target-\u003edtm_configured) {\n\t\t\t\tcommand_print(CMD, \"-dtm ?name? required when creating target\");\n\t\t\t\tretval \u003d ERROR_COMMAND_ARGUMENT_INVALID;\n\t\t\t}\n```","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"d730f8aca63c0d64f94cd21cf990f369ee282c05","unresolved":true,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"f1596152_9a4cf0c4","line":11,"in_reply_to":"e305e14d_02ab0a23","updated":"2026-06-25 08:10:56.000000000","message":"\u003e I think introducing a DTM instance is a good direction. \n\nI agree and support this direction.\n\n\u003e It\u0027s just a small change for now, just introducing the DTM declaration.\n\nRegardless how small, the change is still backward incompatible and breaks all existing RISC-V configuration files for OpenOCD.\n\nMy recommendation is:\n\n1) Either update the patch so that backward compatibility is preserved (+ deprecation warning is shown).\n\n2) Or expand the above-mentioned error message so that it directly tells the users what to change in the configuration file - because users have this unfortunate tendency to to not read the documentation 😊.\n\nSomething like this:\n\n```\nHint: Update your configuration files as shown below. \nOld, unsupported syntax:\n  target create \u003ctarget_name\u003e -chain-position \u003cjtag_tap_name\u003e\nNew syntax:\n  riscv_dtm create \u003cdtm_name\u003e -chain-position \u003cjtag_tap_name\u003e\n  target create \u003ctarget_name\u003e riscv -dtm \u003cdtm_name\u003e\n```","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"},{"author":{"_account_id":1002315,"name":"liangzhen","email":"zhen.liang@spacemit.com","username":"liangzhen"},"change_message_id":"c432ddcb15aaeba7740324a2fb6f3fc47dc3eeb6","unresolved":false,"context_lines":[{"line_number":8,"context_line":"set _CHIPNAME riscv"},{"line_number":9,"context_line":"jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"dtm create $_CHIPNAME.dtm -chain-position $_CHIPNAME.cpu"},{"line_number":12,"context_line":""},{"line_number":13,"context_line":"set _TARGETNAME $_CHIPNAME.cpu"},{"line_number":14,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":3,"id":"0f0dc706_49b0dc7c","line":11,"in_reply_to":"f1596152_9a4cf0c4","updated":"2026-06-29 11:36:04.000000000","message":"Done","commit_id":"fe4cfa86f1921e5bedcbeca92997e36f4f89a698"}]}