)]}'
{"/COMMIT_MSG":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":true,"context_lines":[{"line_number":4,"context_line":"Commit:     lynch \u003clynch.wy@gmail.com\u003e"},{"line_number":5,"context_line":"CommitDate: 2026-10-06 09:19:20 +0800"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"adapter/ch347: release CH347F SRST during JTAG init"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Pin 8 strongly drives low after the adapter powers up, so a wired target"},{"line_number":10,"context_line":"stays in reset until the dedicated output is enabled and driven. Send"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"fd87bfbc_770d5b01","line":7,"range":{"start_line":7,"start_character":15,"end_line":7,"end_character":51},"updated":"2026-10-06 05:32:36.000000000","message":"Reword to something like *enable CH347F dedicated SRST output in JTAG mode*","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"02e30d4833883d62cf107a39c092ac2682ac71db","unresolved":false,"context_lines":[{"line_number":4,"context_line":"Commit:     lynch \u003clynch.wy@gmail.com\u003e"},{"line_number":5,"context_line":"CommitDate: 2026-10-06 09:19:20 +0800"},{"line_number":6,"context_line":""},{"line_number":7,"context_line":"adapter/ch347: release CH347F SRST during JTAG init"},{"line_number":8,"context_line":""},{"line_number":9,"context_line":"Pin 8 strongly drives low after the adapter powers up, so a wired target"},{"line_number":10,"context_line":"stays in reset until the dedicated output is enabled and driven. Send"}],"source_content_type":"text/x-gerrit-commit-message","patch_set":10,"id":"ec3c77d3_6f39e71c","line":7,"range":{"start_line":7,"start_character":15,"end_line":7,"end_character":51},"in_reply_to":"fd87bfbc_770d5b01","updated":"2026-10-11 07:14:43.000000000","message":"Done","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"}],"/PATCHSET_LEVEL":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"6b757d6d0b6e57d3f16ba54a6af99dfce00db633","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"6e3a341a_caa64bad","updated":"2026-08-24 14:51:07.000000000","message":"There is also recent\n9700: drivers/ch347: support SRST in SWD mode | https://review.openocd.org/c/openocd/+/9700\n\nPlease review Paulius\u0027 version, eventually make a compromise version. Thanks","commit_id":"c2177bd3bd7cd723dff2df62d129719cffb404c7"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"bd0e365c_cbac168a","in_reply_to":"6d0951d7_5cc7820f","updated":"2026-10-06 05:32:36.000000000","message":"Done","commit_id":"c2177bd3bd7cd723dff2df62d129719cffb404c7"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"62d0e9bef8e44f7f8c1948c95d55ada3d1f9d92a","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"6d0951d7_5cc7820f","in_reply_to":"6e3a341a_caa64bad","updated":"2026-08-25 02:50:58.000000000","message":"Thanks. I reviewed Paulius’ version and prepared a compromise implementation.\n\nThe combined change keeps the CH347F dedicated SRST output for JTAG mode, \nwhile using the otherwise unused TRST pin as a GPIO-driven SRST output in SWD mode. \nIt also includes chip-specific GPIO availability masks, configurable adapter gpio \nsrst selection/polarity, and avoids validating GPIO readback for SRST.\n\nPlease review the updated patchset.","commit_id":"c2177bd3bd7cd723dff2df62d129719cffb404c7"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"6795754bea5a98d8dda35fbb9c3894234a3bf29f","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":6,"id":"aef8f18b_d4b5d734","updated":"2026-09-18 05:42:36.000000000","message":"Paulius Zaleckas, could you check the latest patchset?","commit_id":"8c56a33123ba80adfb2b42bf232cdb44d0210884"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"85b91824c94879091fdb22de168c0a737811e1ac","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"f41f29ab_a4b830f4","updated":"2026-09-29 02:03:02.000000000","message":"Thanks for the review. The new patch set addresses the points below. Please take another look. \n1. ch347_srst_enable() now runs only after ch347.pack_size \u003d UNSET and ch347_init_pack_size(), so max_len is already set and the command is no longer dropped with \"Nothing to send!\".\n\nI kept the guard as chip_variant \u003d\u003d CH347F rather than !\u003d CH347T. OTHER_PRODUCT_ID is not documented as a CH347F, so it should not be sent 0xE2. Init still fails if the command cannot be transmitted. It no longer fails because of the returned byte; see (3).\nThis was tested on a CH347F (chip version 1.20). The adapter opens, PIN_SET returns 0x00, and a JTAG scan reads the expected IDCODE.\n\n2. The command is not in the CH347 datasheet. It comes from WCH\u0027s fork, commit 4fd5026aabb6 (\"feat: Add CH347F SRST configuration\"):\n\nhttps://github.com/WCHSoftGroup/ch347/commit/4fd5026aabb62b941317b5d156d0eeaef4c43108\n\nTheir packet is {0xe2, 0x08, 0x00, 0x00, 0x81, ...}. The command queue adds the command and the length, so we send only the eight payload bytes. WCH does not document those bytes either, and their close path does not undo PIN_SET. I have no evidence that it writes the EEPROM, so ch347_quit()\nonly restores the pin levels. This is noted above ch347_srst_enable().\n\n3. The returned byte is only logged with LOG_DEBUG. A transmit error is returned unchanged. A non-zero result no longer rejects init.\n\n4. Not changed, on purpose. PIN_SET is still sent for every CH347F, including SWD. WCH sends it for the chip rather than for one transport. The dedicated output is still driven only from the JTAG pin byte, and ch347_quit() does not send that byte in SWD. SWD SRST remains the GPIO on TRST. I\ncan gate the enable with !swd_mode if you would rather not repurpose the pin in SWD.\n\n5. The manual now names CH347F pin 8, \"JTAG interface system reset output\", next to TRST on pin 9, and notes that it is not shared with a GPIO.\n\n6. Pin 8 stays fixed active-low and push-pull. The driver warns once when reset_config is not srst_push_pull. The polarity limitation is documented both in ch347_reset() and in the manual. The SWD GPIO path is unchanged and still follows adapter gpio srst and the drive mode.\n\n7. Restoring TRST on close is now done for every variant, but only in JTAG mode. The dedicated SRST bit is merged only on the CH347F, through ch347_scratchpad_add_pin_byte(), so a CH347T pin byte still does not carry bit 6. SWD does not send a JTAG pin byte.\n\nThe nits are included as well: the pin-byte helper is no longer wrapped for line length, ch347_srst_enable() has a /** @brief */ block, CH347_CMD_PIN_SET sits with the other command defines, the ch347_cmd_calc_reads() comment mentions PIN_SET, and init_result is no longer preset to 1.","commit_id":"374d1c17d84a9a29e8aeb792451c6c2eec891811"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"5122d7939b82b264cb963895c4fda04aa2dd01fb","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":7,"id":"62dc6633_f0a0eefd","in_reply_to":"f41f29ab_a4b830f4","updated":"2026-09-29 02:14:51.000000000","message":"Thanks for the review. The new patch set addresses the points below. Please take another look.\n1. ch347_srst_enable() now runs only after ch347.pack_size \u003d UNSET and ch347_init_pack_size(), so max_len is already set and the command is no longer dropped with \"Nothing to send!\".\n\nI kept the guard as chip_variant \u003d\u003d CH347F rather than !\u003d CH347T. OTHER_PRODUCT_ID is not documented as a CH347F, so it should not be sent 0xE2. Init still fails if the command cannot be transmitted. It no longer fails because of the returned byte; see (3).This was tested on a CH347F (chip version 1.20). The adapter opens, PIN_SET returns 0x00, and a JTAG scan reads the\nexpected IDCODE.\n\n2. The command is not in the CH347 datasheet. It comes from WCH\u0027s fork, commit 4fd5026aabb6 (\"feat: Add CH347F SRST configuration\"):\n\nhttps://github.com/WCHSoftGroup/ch347/commit/4fd5026aabb62b941317b5d156d0eeaef4c43108\n\nTheir packet is {0xe2, 0x08, 0x00, 0x00, 0x81, ...}. The command queue adds the command and the length, so we send only the eight payload bytes. WCH does not document those bytes either, and their close path does not undo PIN_SET. I have no evidence that it writes the EEPROM, so ch347_quit()\nonly restores the pin levels. This is noted above ch347_srst_enable().\n\n3. The returned byte is only logged with LOG_DEBUG. A transmit error is returned unchanged. A non-zero result no longer rejects init.\n\n4. Not changed, on purpose. PIN_SET is still sent for every CH347F, including SWD. WCH sends it for the chip rather than for one transport. The dedicated output is still driven only from the JTAG pin byte, and ch347_quit() does not send that byte in SWD. SWD SRST remains the GPIO on TRST. I\ncan gate the enable with !swd_mode if you would rather not repurpose the pin in SWD.\n\n5. The manual now names CH347F pin 8, \"JTAG interface system reset output\", next to TRST on pin 9, and notes that it is not shared with a GPIO.\n\n6. Pin 8 stays fixed active-low and push-pull. The driver warns once when reset_config is not srst_push_pull. The polarity limitation is documented both in ch347_reset() and in the manual. The SWD GPIO path is unchanged and still follows adapter gpio srst and the drive mode.\n\n7. Restoring TRST on close is now done for every variant, but only in JTAG mode. The dedicated SRST bit is merged only on the CH347F, through ch347_scratchpad_add_pin_byte(), so a CH347T pin byte still does not carry bit 6. SWD does not send a JTAG pin byte.\n\nThe nits are included as well: the pin-byte helper is no longer wrapped for line length, ch347_srst_enable() has a /** @brief */ block, CH347_CMD_PIN_SET sits with the other command defines, the ch347_cmd_calc_reads() comment mentions PIN_SET, and init_result is no longer preset to 1.","commit_id":"374d1c17d84a9a29e8aeb792451c6c2eec891811"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"e9153391e70df24ecf96b96ea80caa0d77ba730e","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":8,"id":"f9ddfa1c_95b082c4","updated":"2026-10-01 08:37:19.000000000","message":"The detailed waveform plots have been sent to you via a separate email. Thanks again for your careful review.","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"02e30d4833883d62cf107a39c092ac2682ac71db","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":12,"id":"cade5f04_eb735f04","updated":"2026-10-11 07:14:43.000000000","message":"Thanks lynch!\nThanks Paulius for the reviews!","commit_id":"a8c8ad97179089085d17fce43f8520429baa30a1"}],"doc/openocd.texi":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":true,"context_lines":[{"line_number":2624,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} to select a different GPIO or"},{"line_number":2625,"context_line":"to change the polarity. On the CH347T, SRST is not available in JTAG mode,"},{"line_number":2626,"context_line":"where the pin carries TRST. On the CH347F, pin 8 is the JTAG interface"},{"line_number":2627,"context_line":"system reset output, next to TRST on pin 9. It is not shared with a GPIO."},{"line_number":2628,"context_line":"After the adapter powers up, pin 8 strongly drives low and holds a wired"},{"line_number":2629,"context_line":"target in reset. JTAG initialization therefore always enables this output"},{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"5e0aa5a2_7c8c4ad6","line":2627,"range":{"start_line":2627,"start_character":19,"end_line":2627,"end_character":42},"updated":"2026-10-06 05:32:36.000000000","message":"Remove","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"02e30d4833883d62cf107a39c092ac2682ac71db","unresolved":false,"context_lines":[{"line_number":2624,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} to select a different GPIO or"},{"line_number":2625,"context_line":"to change the polarity. On the CH347T, SRST is not available in JTAG mode,"},{"line_number":2626,"context_line":"where the pin carries TRST. On the CH347F, pin 8 is the JTAG interface"},{"line_number":2627,"context_line":"system reset output, next to TRST on pin 9. It is not shared with a GPIO."},{"line_number":2628,"context_line":"After the adapter powers up, pin 8 strongly drives low and holds a wired"},{"line_number":2629,"context_line":"target in reset. JTAG initialization therefore always enables this output"},{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"01c907d2_34744533","line":2627,"range":{"start_line":2627,"start_character":19,"end_line":2627,"end_character":42},"in_reply_to":"5e0aa5a2_7c8c4ad6","updated":"2026-10-11 07:14:43.000000000","message":"Done","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":true,"context_lines":[{"line_number":2627,"context_line":"system reset output, next to TRST on pin 9. It is not shared with a GPIO."},{"line_number":2628,"context_line":"After the adapter powers up, pin 8 strongly drives low and holds a wired"},{"line_number":2629,"context_line":"target in reset. JTAG initialization therefore always enables this output"},{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"},{"line_number":2631,"context_line":"SRST. The pin is left low only when @command{reset_config} sets both"},{"line_number":2632,"context_line":"@option{connect_assert_srst} and @option{srst_nogate}. SWD does not use"},{"line_number":2633,"context_line":"this output. Pin 8 is fixed active-low and push-pull: asserting"},{"line_number":2634,"context_line":"SRST drives it low and releasing it drives it high. The polarity of"},{"line_number":2635,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} does not apply to it, and it"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"eaa2fb5e_b753aad6","line":2632,"range":{"start_line":2630,"start_character":23,"end_line":2632,"end_character":53},"updated":"2026-10-06 05:32:36.000000000","message":"Remove. Too verbose","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"02e30d4833883d62cf107a39c092ac2682ac71db","unresolved":false,"context_lines":[{"line_number":2627,"context_line":"system reset output, next to TRST on pin 9. It is not shared with a GPIO."},{"line_number":2628,"context_line":"After the adapter powers up, pin 8 strongly drives low and holds a wired"},{"line_number":2629,"context_line":"target in reset. JTAG initialization therefore always enables this output"},{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"},{"line_number":2631,"context_line":"SRST. The pin is left low only when @command{reset_config} sets both"},{"line_number":2632,"context_line":"@option{connect_assert_srst} and @option{srst_nogate}. SWD does not use"},{"line_number":2633,"context_line":"this output. Pin 8 is fixed active-low and push-pull: asserting"},{"line_number":2634,"context_line":"SRST drives it low and releasing it drives it high. The polarity of"},{"line_number":2635,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} does not apply to it, and it"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"287c6a0c_210828fc","line":2632,"range":{"start_line":2630,"start_character":23,"end_line":2632,"end_character":53},"in_reply_to":"eaa2fb5e_b753aad6","updated":"2026-10-11 07:14:43.000000000","message":"Done","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":true,"context_lines":[{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"},{"line_number":2631,"context_line":"SRST. The pin is left low only when @command{reset_config} sets both"},{"line_number":2632,"context_line":"@option{connect_assert_srst} and @option{srst_nogate}. SWD does not use"},{"line_number":2633,"context_line":"this output. Pin 8 is fixed active-low and push-pull: asserting"},{"line_number":2634,"context_line":"SRST drives it low and releasing it drives it high. The polarity of"},{"line_number":2635,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} does not apply to it, and it"},{"line_number":2636,"context_line":"does not emulate the open-drain mode of"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"94972943_febdfc68","line":2633,"range":{"start_line":2633,"start_character":22,"end_line":2633,"end_character":27},"updated":"2026-10-06 05:32:36.000000000","message":"Remove","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"02e30d4833883d62cf107a39c092ac2682ac71db","unresolved":false,"context_lines":[{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"},{"line_number":2631,"context_line":"SRST. The pin is left low only when @command{reset_config} sets both"},{"line_number":2632,"context_line":"@option{connect_assert_srst} and @option{srst_nogate}. SWD does not use"},{"line_number":2633,"context_line":"this output. Pin 8 is fixed active-low and push-pull: asserting"},{"line_number":2634,"context_line":"SRST drives it low and releasing it drives it high. The polarity of"},{"line_number":2635,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} does not apply to it, and it"},{"line_number":2636,"context_line":"does not emulate the open-drain mode of"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"0eb77ceb_e759a9b3","line":2633,"range":{"start_line":2633,"start_character":22,"end_line":2633,"end_character":27},"in_reply_to":"94972943_febdfc68","updated":"2026-10-11 07:14:43.000000000","message":"Done","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":true,"context_lines":[{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"},{"line_number":2631,"context_line":"SRST. The pin is left low only when @command{reset_config} sets both"},{"line_number":2632,"context_line":"@option{connect_assert_srst} and @option{srst_nogate}. SWD does not use"},{"line_number":2633,"context_line":"this output. Pin 8 is fixed active-low and push-pull: asserting"},{"line_number":2634,"context_line":"SRST drives it low and releasing it drives it high. The polarity of"},{"line_number":2635,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} does not apply to it, and it"},{"line_number":2636,"context_line":"does not emulate the open-drain mode of"},{"line_number":2637,"context_line":"@ref{reset_config,,@command{reset_config}}. The driver warns once when SRST"},{"line_number":2638,"context_line":"is configured and that drive mode is not @code{srst_push_pull}."},{"line_number":2639,"context_line":""},{"line_number":2640,"context_line":"Not every GPIO can be used, because the GPIO\u0027s share their pins with the"},{"line_number":2641,"context_line":"interface signals. Only GPIO3 to GPIO6 are free on the CH347T, and GPIO0 to"},{"line_number":2642,"context_line":"GPIO3 on the CH347F, where GPIO4 to GPIO7 are TCK, TDO, TDI and TMS. Note that"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"74ae7bcb_eb4ec83a","line":2639,"range":{"start_line":2633,"start_character":54,"end_line":2639,"end_character":0},"updated":"2026-10-06 05:32:36.000000000","message":"Remove","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"02e30d4833883d62cf107a39c092ac2682ac71db","unresolved":false,"context_lines":[{"line_number":2630,"context_line":"and then drives it high, whether or not @command{reset_config} includes"},{"line_number":2631,"context_line":"SRST. The pin is left low only when @command{reset_config} sets both"},{"line_number":2632,"context_line":"@option{connect_assert_srst} and @option{srst_nogate}. SWD does not use"},{"line_number":2633,"context_line":"this output. Pin 8 is fixed active-low and push-pull: asserting"},{"line_number":2634,"context_line":"SRST drives it low and releasing it drives it high. The polarity of"},{"line_number":2635,"context_line":"@ref{adapter gpio, @command{adapter gpio srst}} does not apply to it, and it"},{"line_number":2636,"context_line":"does not emulate the open-drain mode of"},{"line_number":2637,"context_line":"@ref{reset_config,,@command{reset_config}}. The driver warns once when SRST"},{"line_number":2638,"context_line":"is configured and that drive mode is not @code{srst_push_pull}."},{"line_number":2639,"context_line":""},{"line_number":2640,"context_line":"Not every GPIO can be used, because the GPIO\u0027s share their pins with the"},{"line_number":2641,"context_line":"interface signals. Only GPIO3 to GPIO6 are free on the CH347T, and GPIO0 to"},{"line_number":2642,"context_line":"GPIO3 on the CH347F, where GPIO4 to GPIO7 are TCK, TDO, TDI and TMS. Note that"}],"source_content_type":"text/x-texinfo","patch_set":10,"id":"bbbcd73e_26666c3a","line":2639,"range":{"start_line":2633,"start_character":54,"end_line":2639,"end_character":0},"in_reply_to":"74ae7bcb_eb4ec83a","updated":"2026-10-11 07:14:43.000000000","message":"Done","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"}],"src/jtag/drivers/ch347.c":[{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"52b1dd4cded4de4cf772334e0be457ca68efc63c","unresolved":true,"context_lines":[{"line_number":76,"context_line":"#define GPIO_CNT\t8 // the CH347 has 8 GPIO\u0027s"},{"line_number":77,"context_line":"/* mask which GPIO\u0027s are available in mode 3 of the CH347T: only GPIO3 (Pin11 / SCL),"},{"line_number":78,"context_line":"\tGPIO4 (Pin15 / ACT), GPIO5 (Pin9 / TRST) and GPIO6 (Pin2 / CTS1) are possible */"},{"line_number":79,"context_line":"#define CH347T_USABLE_GPIOS\t0x78"},{"line_number":80,"context_line":"/* On the CH347F GPIO4 to GPIO7 share their pins with TCK, TDO, TDI and TMS."},{"line_number":81,"context_line":"\tGPIO4 and GPIO7 are also SWDCLK and SWDIO, so only GPIO0 to GPIO3 are free."},{"line_number":82,"context_line":"\tGPIO3 is TRST, which is not a SWD signal. */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"a497ca0f_35e870e1","line":79,"updated":"2026-09-01 14:33:31.000000000","message":"What is source for choosing usable pins?\nOn CH347T I tested also GPIO7 (RTS1) and GPIO1 (TDO, not used for SWD) and haven\u0027t seen any problem. Of course if UART1 is active then RTS is not a good choice. Seems me that only GPIO0 (TCK) and GPIO2 (TMS/SWD) cannot be used as they break SWD and I agree with exclusion of GPIO7 (RTS1). Did I miss something?","commit_id":"a6b6602e3702b21108f843d74ce7983bfb3c02c6"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"7d0e6ebae2fb77f9839ece55c2a59f2cf2ffe2b6","unresolved":false,"context_lines":[{"line_number":76,"context_line":"#define GPIO_CNT\t8 // the CH347 has 8 GPIO\u0027s"},{"line_number":77,"context_line":"/* mask which GPIO\u0027s are available in mode 3 of the CH347T: only GPIO3 (Pin11 / SCL),"},{"line_number":78,"context_line":"\tGPIO4 (Pin15 / ACT), GPIO5 (Pin9 / TRST) and GPIO6 (Pin2 / CTS1) are possible */"},{"line_number":79,"context_line":"#define CH347T_USABLE_GPIOS\t0x78"},{"line_number":80,"context_line":"/* On the CH347F GPIO4 to GPIO7 share their pins with TCK, TDO, TDI and TMS."},{"line_number":81,"context_line":"\tGPIO4 and GPIO7 are also SWDCLK and SWDIO, so only GPIO0 to GPIO3 are free."},{"line_number":82,"context_line":"\tGPIO3 is TRST, which is not a SWD signal. */"}],"source_content_type":"text/x-csrc","patch_set":2,"id":"59c141ef_4e276c63","line":79,"in_reply_to":"a497ca0f_35e870e1","updated":"2026-09-01 14:34:36.000000000","message":"Sorry, I want to write the comment to #9700","commit_id":"a6b6602e3702b21108f843d74ce7983bfb3c02c6"},{"author":{"_account_id":1002556,"name":"Paulius Zaleckas","display_name":"Paulius Zaleckas","email":"paulius.zaleckas@gmail.com","username":"pauliusz"},"change_message_id":"66df0a13330132cfbcdd381df59029b6dbc85664","unresolved":false,"context_lines":[{"line_number":1394,"context_line":"\t\treturn retval;"},{"line_number":1395,"context_line":""},{"line_number":1396,"context_line":"\tch347.trst_pin \u003d trst ? TRST_L : TRST_H;"},{"line_number":1397,"context_line":"\tif (ch347.chip_variant \u003d\u003d CH347F)"},{"line_number":1398,"context_line":"\t\tch347.srst_pin \u003d srst ? SRST_L : SRST_H;"},{"line_number":1399,"context_line":"\tretval \u003d ch347_scratchpad_add_pin_byte();"},{"line_number":1400,"context_line":"\tif (retval !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"36b0b022_bb801a2a","line":1397,"updated":"2026-09-01 18:11:18.000000000","message":"On a CH347T this silently accepts SRST in JTAG mode instead of refusing\nit. Master has\n\n\tif (srst) {\n\t\tLOG_ERROR(\"Asserting SRST not supported!\");\n\t\treturn ERROR_FAIL;\n\t}\n\nbefore this point, and the change removes it. What is left only sets\nsrst_pin for the CH347F, so for CH347T and for OTHER_PRODUCT_ID\nch347_reset() now returns ERROR_OK without doing anything.\n\nVerified on a CH347T in mode 3, chip version 5.44, JTAG transport with\n\u0027reset_config trst_and_srst\u0027:\n\n  with this change   \u0027adapter assert srst\u0027 prints nothing at all\n  with master/9700   Error: Asserting SRST not supported\n                     Error: TRST/SRST error\n\nThe scan chain survives either way, so the only user visible signal is\nthat message, and it is gone. Someone with a CH347T who writes\n\u0027reset_config srst_only\u0027 now gets a reset that quietly does nothing\ninstead of a diagnostic.\n\nCould the refusal be kept for the variants that have no dedicated SRST\noutput, something like\n\n\tif (ch347.chip_variant \u003d\u003d CH347F) {\n\t\tch347.srst_pin \u003d srst ? SRST_L : SRST_H;\n\t} else if (srst) {\n\t\tLOG_ERROR(\"Asserting SRST not supported!\");\n\t\treturn ERROR_FAIL;\n\t}","commit_id":"72b13cb2b952892ee942a4ac0affb86f03b61ded"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"7fbbfc9e5eabbe7dd92ac33ee2e95b421ba43967","unresolved":false,"context_lines":[{"line_number":1394,"context_line":"\t\treturn retval;"},{"line_number":1395,"context_line":""},{"line_number":1396,"context_line":"\tch347.trst_pin \u003d trst ? TRST_L : TRST_H;"},{"line_number":1397,"context_line":"\tif (ch347.chip_variant \u003d\u003d CH347F)"},{"line_number":1398,"context_line":"\t\tch347.srst_pin \u003d srst ? SRST_L : SRST_H;"},{"line_number":1399,"context_line":"\tretval \u003d ch347_scratchpad_add_pin_byte();"},{"line_number":1400,"context_line":"\tif (retval !\u003d ERROR_OK)"}],"source_content_type":"text/x-csrc","patch_set":4,"id":"acc911c0_a323e09a","line":1397,"in_reply_to":"36b0b022_bb801a2a","updated":"2026-09-05 02:36:18.000000000","message":"Thanks for the detailed testing and review.\nYou are right; this regression is caused by missing chip-variant checks. I update the patch to apply the SRST handling only to CH347F and preserve the refusal on unsupported variants.\nI will wait for 9700 to be merged, then rebase and resubmit this series without duplicating the SWD GPIO SRST implementation.","commit_id":"72b13cb2b952892ee942a4ac0affb86f03b61ded"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"38471225c6c3223458f53b0b268f3312e4d7d33a","unresolved":true,"context_lines":[{"line_number":2095,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2096,"context_line":"\t\t\t\treturn retval;"},{"line_number":2097,"context_line":""},{"line_number":2098,"context_line":"\t\t\tretval \u003d ch347_srst_enable();"},{"line_number":2099,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":2100,"context_line":"\t\t\t\tLOG_ERROR(\"CH347F dedicated SRST enable failed\");"},{"line_number":2101,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"a216bbd8_2e3ee262","line":2098,"updated":"2026-10-01 10:12:37.000000000","message":"It\u0027s a good idea to call `ch347_srst_enable()` optionally AFAIK we don\u0027t how to disable this mode and put SRST pin back to power on default Hi-Z. Don\u0027t you want to experiment with CH347_CMD_PIN_SET command payload? I would guess that sending 0x80 instead of 0x81 could work. It would be useful also for the simulated open-drain mode.\n\nHowever be aware that the `reset_config` command is accepted anytime during an OpenOCD session, so RESET_HAS_SRST may change from its initial state. If possible move `ch347_srst_enable()` to  `ch347_reset()`.","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"187f4a1ef8349692cc0ffcb5867e3cdfc46b9fa5","unresolved":true,"context_lines":[{"line_number":2095,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2096,"context_line":"\t\t\t\treturn retval;"},{"line_number":2097,"context_line":""},{"line_number":2098,"context_line":"\t\t\tretval \u003d ch347_srst_enable();"},{"line_number":2099,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":2100,"context_line":"\t\t\t\tLOG_ERROR(\"CH347F dedicated SRST enable failed\");"},{"line_number":2101,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"c850af10_3a67906f","line":2098,"in_reply_to":"0f2a7b6a_3474509d","updated":"2026-10-04 21:36:28.000000000","message":"I looked to wch github and noticed that dedicated SRST is handled with CH347_CMD_PIN_SET and CH347_CMD_JTAG_BIT_OP even in SWD mode. I tested it with our driver and with CH347F Chip version\u003d1.20, Firmware\u003d0x42 and yes, it worked. Moreover also CH347_CMD_GPIO is possible in JTAG mode. So we don\u0027t need to handle SRST in different ways according to selected JTAG or SWD transport.\n\nMy idea is to define a new GPIO 8 equal to the CH347F dedicated SRST pin and decide the type of handling by gpio setting:\n- gpio pin TRST, push-pull: use CH347_CMD_JTAG_BIT_OP for JTAG (and SWD which does not use it)\n- gpio pin SRST, push-pull: use CH347_CMD_JTAG_BIT_OP for both JTAG and SWD\n- any gpio pin but SRST, any drive mode: use CH347_CMD_GPIO\n\nTODO: test if CH347_CMD_JTAG_BIT_OP does not change SWCLK or SWDIO in SWD mode,\ntest on CH347T and other fw versions.","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":false,"context_lines":[{"line_number":2095,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2096,"context_line":"\t\t\t\treturn retval;"},{"line_number":2097,"context_line":""},{"line_number":2098,"context_line":"\t\t\tretval \u003d ch347_srst_enable();"},{"line_number":2099,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":2100,"context_line":"\t\t\t\tLOG_ERROR(\"CH347F dedicated SRST enable failed\");"},{"line_number":2101,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"450850f6_bc96581d","line":2098,"in_reply_to":"1e51ba67_c23d9ec3","updated":"2026-10-06 05:32:36.000000000","message":"\u003e The SWD path is unchanged in this patch.\n\nI agree to leave the unification of JTAG and SWD reset handling to next patch and merge this with working SRST support in JTAG only","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"d74885851d52b668426d5e4276f81d7c2a6bd01f","unresolved":true,"context_lines":[{"line_number":2095,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2096,"context_line":"\t\t\t\treturn retval;"},{"line_number":2097,"context_line":""},{"line_number":2098,"context_line":"\t\t\tretval \u003d ch347_srst_enable();"},{"line_number":2099,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":2100,"context_line":"\t\t\t\tLOG_ERROR(\"CH347F dedicated SRST enable failed\");"},{"line_number":2101,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"0f2a7b6a_3474509d","line":2098,"in_reply_to":"3e2a45cd_8ab9b831","updated":"2026-10-02 10:23:08.000000000","message":"Sorry I pointed you wrong way! The comment\n`PIN_SET only switches pin 8 to a push-pull output`\nmisleaded me that I thought that pin 8 is in Hi-Z by default.\nUnfortunately it\u0027s not, pin 8 strongly drives to low after adapter power up.\nSimilarly as TCK, TMS and TDO drive to low although they should have weak pull down (TCK) or weak pull up (TMS and TDO) until JTAG mode is activated. This is very bad HW design again.\n\nSo there is no point in optionally enabling dedicated SRST mode.\nWe have to unconditionally enable this mode at JTAG init to unlock the target from a potential SRST forced by adapter power up. We should do this regardless of `RESET_HAS_SRST`.\n\nOnly if both RESET_CNCT_UNDER_SRST and RESET_SRST_NO_GATING are set we should force SRST low at init if possible. See also\n9926: jtag/adapter: honour connect_assert_srst in gpio init | https://review.openocd.org/c/openocd/+/9926\n\nI played with PIN_SET payload. `cmd_data[1] \u003d 0x80` really switches the dedicated SRST mode off, but the pin probably is not tristate capable at all, so the pin keeps the last state. No point in switching off the mode until we know how to control the pin in SWD.","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"527b7e62b3a6c11f2c18a3c5bb962d42d6443b36","unresolved":true,"context_lines":[{"line_number":2095,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2096,"context_line":"\t\t\t\treturn retval;"},{"line_number":2097,"context_line":""},{"line_number":2098,"context_line":"\t\t\tretval \u003d ch347_srst_enable();"},{"line_number":2099,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":2100,"context_line":"\t\t\t\tLOG_ERROR(\"CH347F dedicated SRST enable failed\");"},{"line_number":2101,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"3e2a45cd_8ab9b831","line":2098,"in_reply_to":"a216bbd8_2e3ee262","updated":"2026-10-02 06:55:10.000000000","message":"Thanks for the review.\nThe second one is fixed in this version. The first one still needs a bench measurement, so that behavior is unchanged.\n\n2）reset_config can change after init\nPIN_SET is now sent at most once, from ch347_dedicated_srst_ensure():\n• ch347_init() calls it when SRST is already configured, so pin 8 is driven high before the first reset. \n• ch347_reset() calls it only when the current configuration has SRST and the pin is not enabled yet. A later reset_config srst_only is picked up on the next reset.\n• If the pin is already enabled, ch347_reset() only changes the level. It does not send PIN_SET again.","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"b4181c8b9701b7947a13fc25fe4ff94f2d5541c3","unresolved":true,"context_lines":[{"line_number":2095,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2096,"context_line":"\t\t\t\treturn retval;"},{"line_number":2097,"context_line":""},{"line_number":2098,"context_line":"\t\t\tretval \u003d ch347_srst_enable();"},{"line_number":2099,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":2100,"context_line":"\t\t\t\tLOG_ERROR(\"CH347F dedicated SRST enable failed\");"},{"line_number":2101,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"1e51ba67_c23d9ec3","line":2098,"in_reply_to":"b8f8f4cc_b649232d","updated":"2026-10-06 01:26:58.000000000","message":"Thank you for the correction. Pin 8 is not Hi-Z after power-up; it strongly drives low and can hold the target in reset. The comment that suggested otherwise was misleading, and it has been removed.\n\nThis update follows the WCH sequence on every CH347F JTAG init, whether or not reset_config includes SRST. PIN_SET is sent with cmd_data[1] \u003d 0x81, and the following JTAG pin byte drives pin 8 high so the target is released. The pin is left low only when both connect_assert_srst and srst_nogate are set.\n\ncmd_data[1] \u003d 0x80 is not sent. Turning the dedicated mode off does not tristate the pin, so it would only keep the last level. The SWD path is unchanged in this patch.","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"8559bda120e15ef832d66038a9a07d4b58d2fd25","unresolved":true,"context_lines":[{"line_number":2095,"context_line":"\t\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2096,"context_line":"\t\t\t\treturn retval;"},{"line_number":2097,"context_line":""},{"line_number":2098,"context_line":"\t\t\tretval \u003d ch347_srst_enable();"},{"line_number":2099,"context_line":"\t\t\tif (retval !\u003d ERROR_OK) {"},{"line_number":2100,"context_line":"\t\t\t\tLOG_ERROR(\"CH347F dedicated SRST enable failed\");"},{"line_number":2101,"context_line":"\t\t\t\treturn retval;"}],"source_content_type":"text/x-csrc","patch_set":8,"id":"b8f8f4cc_b649232d","line":2098,"in_reply_to":"c850af10_3a67906f","updated":"2026-10-05 07:58:20.000000000","message":"\u003e TODO: test if CH347_CMD_JTAG_BIT_OP does not change SWCLK or SWDIO in SWD mode,\n\nIt does. To avoid an unwanted pulse we need to init pin levels differently for SWD - according to SWD idle levels:\n```\nch347.tck_pin \u003d TCK_H;\nch347.tms_pin \u003d TMS_L;\n```","commit_id":"b6a6cddffbd10011e0a34dc717749ef81c369a14"},{"author":{"_account_id":1002556,"name":"Paulius Zaleckas","display_name":"Paulius Zaleckas","email":"paulius.zaleckas@gmail.com","username":"pauliusz"},"change_message_id":"54caf089f1593f7d1b7e25ab2f300e969628bc44","unresolved":true,"context_lines":[{"line_number":1804,"context_line":"\t/* TRST is a common JTAG pin, so restore it on every variant. The"},{"line_number":1805,"context_line":"\t * dedicated SRST bit is merged only after PIN_SET has enabled it."},{"line_number":1806,"context_line":"\t * SWD does not send a JTAG pin byte: its SRST is a GPIO. */"},{"line_number":1807,"context_line":"\tif (!swd_mode) {"},{"line_number":1808,"context_line":"\t\tch347.trst_pin \u003d TRST_H;"},{"line_number":1809,"context_line":"\t\tif (ch347_dedicated_srst_enabled)"},{"line_number":1810,"context_line":"\t\t\tch347.srst_pin \u003d SRST_H;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"77a9c23d_e5962c86","line":1807,"updated":"2026-10-06 19:12:30.000000000","message":"This goes beyond the CH347F SRST change: on quit in JTAG mode it now sends an extra JTAG_BIT_OP pin byte that drives TRST high on every variant, including the CH347T. That is a behaviour change for adapters that do not have the dedicated SRST at all.\n\nPlease either move the TRST restore into a separate patch, or keep only the CH347F SRST part here and explain in the commit message why quit has to touch the pins.","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"951db0cc587cb4aff4f2b55dfb22308634849046","unresolved":true,"context_lines":[{"line_number":1804,"context_line":"\t/* TRST is a common JTAG pin, so restore it on every variant. The"},{"line_number":1805,"context_line":"\t * dedicated SRST bit is merged only after PIN_SET has enabled it."},{"line_number":1806,"context_line":"\t * SWD does not send a JTAG pin byte: its SRST is a GPIO. */"},{"line_number":1807,"context_line":"\tif (!swd_mode) {"},{"line_number":1808,"context_line":"\t\tch347.trst_pin \u003d TRST_H;"},{"line_number":1809,"context_line":"\t\tif (ch347_dedicated_srst_enabled)"},{"line_number":1810,"context_line":"\t\t\tch347.srst_pin \u003d SRST_H;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"9a004b72_daaaa727","line":1807,"in_reply_to":"77a9c23d_e5962c86","updated":"2026-10-06 20:55:50.000000000","message":"Both resets are normally kept inactive so most of adapter drivers simply do not care about deinitialisation. It has an advantage that user is able to keep reset asserted over openocd restart.\n\nThe adapter GPIO infrastructure provides a configurable exit state, implemented only in parport. Note that by default the pin is not changed when the driver terminates its operation.\nSome other bitbang drivers unconditionally restore GPIO state saved before init, this is not possible here.\n\nI would propose to drop this part to keep compatibility between JTAG/SWD modes and later implement configurable exit state.","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"6c6d03a5dd64c1a016866f9afb60503e1644385b","unresolved":true,"context_lines":[{"line_number":1804,"context_line":"\t/* TRST is a common JTAG pin, so restore it on every variant. The"},{"line_number":1805,"context_line":"\t * dedicated SRST bit is merged only after PIN_SET has enabled it."},{"line_number":1806,"context_line":"\t * SWD does not send a JTAG pin byte: its SRST is a GPIO. */"},{"line_number":1807,"context_line":"\tif (!swd_mode) {"},{"line_number":1808,"context_line":"\t\tch347.trst_pin \u003d TRST_H;"},{"line_number":1809,"context_line":"\t\tif (ch347_dedicated_srst_enabled)"},{"line_number":1810,"context_line":"\t\t\tch347.srst_pin \u003d SRST_H;"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"f71762eb_76b64233","line":1807,"in_reply_to":"9a004b72_daaaa727","updated":"2026-10-08 10:58:28.000000000","message":"Thanks for the review.\nI dropped the pin byte from ch347_quit(), so this patch no longer changes the pins on exit. I will submit a separate patch to handle the exit state.\nThe other points are in the new patch set as well.","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"076aa4f52db015263a2c79b937160ba3199248ef","unresolved":true,"context_lines":[{"line_number":2147,"context_line":"\t\t * dedicated SRST output once and release it, even when reset_config"},{"line_number":2148,"context_line":"\t\t * does not include SRST. Leave it asserted only for connect_assert_srst"},{"line_number":2149,"context_line":"\t\t * together with srst_nogate. SWD reset stays on the TRST GPIO. */"},{"line_number":2150,"context_line":"\t\tretval \u003d ch347_dedicated_srst_ensure();"},{"line_number":2151,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2152,"context_line":"\t\t\treturn retval;"},{"line_number":2153,"context_line":"\t\ttap_set_state(TAP_RESET);"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"1a64656b_e4789ea7","line":2150,"range":{"start_line":2150,"start_character":11,"end_line":2150,"end_character":40},"updated":"2026-10-06 05:32:36.000000000","message":"Here is the only caller of `ch347_dedicated_srst_ensure()` and some tests in `ch347_dedicated_srst_ensure()` are now useless. Please drop `ch347_dedicated_srst_ensure()` and move its body here.","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"tomas.vanek.oocd@gmail.com","username":"vanekt"},"change_message_id":"02e30d4833883d62cf107a39c092ac2682ac71db","unresolved":false,"context_lines":[{"line_number":2147,"context_line":"\t\t * dedicated SRST output once and release it, even when reset_config"},{"line_number":2148,"context_line":"\t\t * does not include SRST. Leave it asserted only for connect_assert_srst"},{"line_number":2149,"context_line":"\t\t * together with srst_nogate. SWD reset stays on the TRST GPIO. */"},{"line_number":2150,"context_line":"\t\tretval \u003d ch347_dedicated_srst_ensure();"},{"line_number":2151,"context_line":"\t\tif (retval !\u003d ERROR_OK)"},{"line_number":2152,"context_line":"\t\t\treturn retval;"},{"line_number":2153,"context_line":"\t\ttap_set_state(TAP_RESET);"}],"source_content_type":"text/x-csrc","patch_set":10,"id":"cb2f9514_09504183","line":2150,"range":{"start_line":2150,"start_character":11,"end_line":2150,"end_character":40},"in_reply_to":"1a64656b_e4789ea7","updated":"2026-10-11 07:14:43.000000000","message":"Done","commit_id":"749e477f5eb09855891fdaa7298b0576896d26a0"},{"author":{"_account_id":1002556,"name":"Paulius Zaleckas","display_name":"Paulius Zaleckas","email":"paulius.zaleckas@gmail.com","username":"pauliusz"},"change_message_id":"5caa9284dc3662f7625e76c87c7060b812e9faf2","unresolved":false,"context_lines":[{"line_number":1042,"context_line":"\tif (retval \u003d\u003d ERROR_OK)"},{"line_number":1043,"context_line":"\t\tretval \u003d ch347_cmd_transmit_queue();"},{"line_number":1044,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1045,"context_line":"\t\tch347_dedicated_srst_enabled \u003d false;"},{"line_number":1046,"context_line":"\treturn retval;"},{"line_number":1047,"context_line":"}"},{"line_number":1048,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":11,"id":"74b9c9e6_1aad8e55","line":1045,"updated":"2026-10-08 11:19:56.000000000","message":"Nit: with ch347_dedicated_srst_ensure() gone, a failed enable makes ch347_init() fail and init is never called again, so this clear (and the \"later init can retry\" / \"next init retries both commands\" comments at lines 1012 and 1037) no longer serves a purpose and could be dropped.","commit_id":"9f5d61bf479758eb9af6b949dd2f5b8d58457d0f"},{"author":{"_account_id":1002556,"name":"Paulius Zaleckas","display_name":"Paulius Zaleckas","email":"paulius.zaleckas@gmail.com","username":"pauliusz"},"change_message_id":"5caa9284dc3662f7625e76c87c7060b812e9faf2","unresolved":false,"context_lines":[{"line_number":1494,"context_line":" *"},{"line_number":1495,"context_line":" * @param trst 1 to assert TRST, 0 to deassert TRST."},{"line_number":1496,"context_line":" * @param srst 1 to assert SRST, 0 to deassert SRST."},{"line_number":1497,"context_line":" * @return ERROR_FAIL for asserting SRST in JTAG mode when the dedicated"},{"line_number":1498,"context_line":" * output cannot be enabled. ERROR_OK for TRST in JTAG mode, SRST on an enabled"},{"line_number":1499,"context_line":" * CH347F output, and SRST in SWD mode."},{"line_number":1500,"context_line":" */"}],"source_content_type":"text/x-csrc","patch_set":11,"id":"cfa6f221_a57d16a5","line":1497,"updated":"2026-10-08 11:19:56.000000000","message":"Nit: on a CH347F init fails if the enable fails, so in practice this is just \"asserting SRST in JTAG mode on CH347T\" (or another non-F variant).","commit_id":"9f5d61bf479758eb9af6b949dd2f5b8d58457d0f"},{"author":{"_account_id":1002556,"name":"Paulius Zaleckas","display_name":"Paulius Zaleckas","email":"paulius.zaleckas@gmail.com","username":"pauliusz"},"change_message_id":"5caa9284dc3662f7625e76c87c7060b812e9faf2","unresolved":false,"context_lines":[{"line_number":1804,"context_line":"\t}"},{"line_number":1805,"context_line":""},{"line_number":1806,"context_line":"\tuint8_t mode;"},{"line_number":1807,"context_line":"\tretval \u003d ch347_single_read_get_byte(0, \u0026mode);"},{"line_number":1808,"context_line":"\tif (retval !\u003d ERROR_OK)"},{"line_number":1809,"context_line":"\t\treturn retval;"},{"line_number":1810,"context_line":""}],"source_content_type":"text/x-csrc","patch_set":11,"id":"879058b8_65a4a4a7","line":1807,"in_reply_to":"f71762eb_76b64233","updated":"2026-10-08 11:19:56.000000000","message":"Done, thanks.","commit_id":"9f5d61bf479758eb9af6b949dd2f5b8d58457d0f"},{"author":{"_account_id":1002556,"name":"Paulius Zaleckas","display_name":"Paulius Zaleckas","email":"paulius.zaleckas@gmail.com","username":"pauliusz"},"change_message_id":"5caa9284dc3662f7625e76c87c7060b812e9faf2","unresolved":false,"context_lines":[{"line_number":2096,"context_line":""},{"line_number":2097,"context_line":"\tif (!swd_mode) {"},{"line_number":2098,"context_line":"\t\t/* Pin 8 drives strong low after adapter power-up. On CH347F, enable the"},{"line_number":2099,"context_line":"\t\t * dedicated SRST output once and release it, even when reset_config"},{"line_number":2100,"context_line":"\t\t * does not include SRST. Leave it asserted only for connect_assert_srst"},{"line_number":2101,"context_line":"\t\t * together with srst_nogate. */"},{"line_number":2102,"context_line":"\t\tif (ch347.chip_variant \u003d\u003d CH347F) {"}],"source_content_type":"text/x-csrc","patch_set":11,"id":"c2b12611_cabc67b2","line":2099,"updated":"2026-10-08 11:19:56.000000000","message":"Nit: \"once\" was meaningful with the old ensure() early return; it can go now.","commit_id":"9f5d61bf479758eb9af6b949dd2f5b8d58457d0f"},{"author":{"_account_id":1002563,"name":"lynch","display_name":"lynch","email":"lynch.wy@gmail.com","username":"lynchwy"},"change_message_id":"76abaee2dc89054e4ef51f5fdbd25cf186eb8eb5","unresolved":false,"context_lines":[{"line_number":2096,"context_line":""},{"line_number":2097,"context_line":"\tif (!swd_mode) {"},{"line_number":2098,"context_line":"\t\t/* Pin 8 drives strong low after adapter power-up. On CH347F, enable the"},{"line_number":2099,"context_line":"\t\t * dedicated SRST output once and release it, even when reset_config"},{"line_number":2100,"context_line":"\t\t * does not include SRST. Leave it asserted only for connect_assert_srst"},{"line_number":2101,"context_line":"\t\t * together with srst_nogate. */"},{"line_number":2102,"context_line":"\t\tif (ch347.chip_variant \u003d\u003d CH347F) {"}],"source_content_type":"text/x-csrc","patch_set":11,"id":"0ee81794_570ba799","line":2099,"in_reply_to":"c2b12611_cabc67b2","updated":"2026-10-10 09:54:11.000000000","message":"Thanks for the review.\nI applied the three nits in the new patch,Keep helping to review the code.","commit_id":"9f5d61bf479758eb9af6b949dd2f5b8d58457d0f"}]}