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FLASH_ERR_01 in mspm0_read_part_info\n\nMSPM0G devices have errata FLASH_ERR_01: accessing FACTORYREGION\n(0x41C40000) via any AHB bus master causes a hard fault when the flash\ncontroller is operating with 2 wait states. This occurs when MCLK is\nsourced from HSCLK (SYSPLL/HFXT), i.e. MCLK \u003e 32 MHz.\n\nThis affects OpenOCD reads (via DAP AHB-AP) in mspm0_read_part_info().\n\nFix this by checking SYSCTL_MCLKCFG before reading FACTORYREGION. If\nUSEHSCLK is set and FLASHWAIT \u003d\u003d 2, temporarily switch MCLK to SYSOSC\n(≤ 32 MHz), perform the reads (DID, TRACEID, USERID, SRAMFLASH), and\nthen restore the original MCLK configuration. Restoration is ensured for\nboth success and error paths.\n\nThe workaround is effectively a no-op on MSPM0L and MSPM0C devices,\nsince they do not reach the required clock conditions.\n\nAlso handle cases where FACTORYREGION reads fail during probe: if the\nmain flash size is zero, force a re-probe by clearing did.\n\nLink: https://www.ti.com/lit/er/slaz758d/slaz758d.pdf\nChange-Id: I100b02f009b3e200cb3a4482c4a26ffbdb8f5f3e\nReported-by: Michael Rodriguez \u003cMichael.Rodriguez@cranepi.com\u003e\nTested-by: Michael Rodriguez \u003cMichael.Rodriguez@cranepi.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\n"}},"0b3e390506d1dd0e3d8a0db2e3163fce71f6f131":{"kind":"REWORK","_number":3,"created":"2026-07-01 09:54:04.000000000","uploader":{"_account_id":1000687,"name":"Tomas Vanek","display_name":"Tomas Vanek","email":"vanekt@fbl.cz","username":"vanekt"},"ref":"refs/changes/26/9726/3","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/26/9726/3","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/3 \u0026\u0026 git checkout -b change-9726 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/26/9726/3","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4de89132f4b5e059d5421af3ec66196b6f855bd2","subject":"tcl/target/ti/mspm0: fix mspm0_board_reset DebugSS recovery"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2026-05-29 04:38:44.000000000","tz":-300},"committer":{"name":"Tomas Vanek","email":"vanekt@fbl.cz","date":"2026-07-01 09:54:04.000000000","tz":0},"subject":"flash/nor/mspm0: workaround FLASH_ERR_01 in mspm0_read_part_info","message":"flash/nor/mspm0: workaround FLASH_ERR_01 in mspm0_read_part_info\n\nMSPM0G devices have errata FLASH_ERR_01: accessing FACTORYREGION\n(0x41C40000) via any AHB bus master causes a hard fault when the flash\ncontroller is operating with 2 wait states. This occurs when MCLK is\nsourced from HSCLK (SYSPLL/HFXT), i.e. MCLK \u003e 32 MHz.\n\nThis affects OpenOCD reads (via DAP AHB-AP) in mspm0_read_part_info().\n\nFix this by checking SYSCTL_MCLKCFG before reading FACTORYREGION. If\nUSEHSCLK is set and FLASHWAIT \u003d\u003d 2, temporarily switch MCLK to SYSOSC\n(≤ 32 MHz), perform the reads (DID, TRACEID, USERID, SRAMFLASH), and\nthen restore the original MCLK configuration. Restoration is ensured for\nboth success and error paths.\n\nThe workaround is effectively a no-op on MSPM0L and MSPM0C devices,\nsince they do not reach the required clock conditions.\n\nAlso handle cases where FACTORYREGION reads fail during probe: if the\nmain flash size is zero, force a re-probe by clearing did.\n\nLink: https://www.ti.com/lit/er/slaz758d/slaz758d.pdf\nChange-Id: I100b02f009b3e200cb3a4482c4a26ffbdb8f5f3e\nReported-by: Michael Rodriguez \u003cMichael.Rodriguez@cranepi.com\u003e\nTested-by: Michael Rodriguez \u003cMichael.Rodriguez@cranepi.com\u003e\nSigned-off-by: Nishanth Menon \u003cnm@ti.com\u003e\nReviewed-on: https://review.openocd.org/c/openocd/+/9726\nTested-by: jenkins\nReviewed-by: Tomas Vanek \u003cvanekt@fbl.cz\u003e\n"}},"4e1a8ad5beeb157fa63f2d2aad60cfd60c2b84d3":{"kind":"REWORK","_number":2,"created":"2026-05-29 17:39:22.000000000","uploader":{"_account_id":1001678,"name":"Nishanth Menon","email":"nm@ti.com","username":"nmenon"},"ref":"refs/changes/26/9726/2","fetch":{"anonymous http":{"url":"https://review.openocd.org/openocd","ref":"refs/changes/26/9726/2","commands":{"Branch":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/2 \u0026\u0026 git checkout -b change-9726 FETCH_HEAD","Checkout":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.openocd.org/openocd refs/changes/26/9726/2","Reset To":"git fetch https://review.openocd.org/openocd refs/changes/26/9726/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"0be5a94827fa4e9e33ea040c5cd14840d31ecf58","subject":"tcl/target/ti/mspm0: fix mspm0_board_reset DebugSS recovery"}],"author":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2026-05-29 04:38:44.000000000","tz":-300},"committer":{"name":"Nishanth Menon","email":"nm@ti.com","date":"2026-05-29 17:39:06.000000000","tz":-300},"subject":"flash/nor/mspm0: workaround FLASH_ERR_01 in mspm0_read_part_info","message":"flash/nor/mspm0: workaround FLASH_ERR_01 in mspm0_read_part_info\n\nMSPM0G devices have errata FLASH_ERR_01: accessing FACTORYREGION\n(0x41C40000) via any AHB bus master causes a hard fault when the flash\ncontroller is operating with 2 wait states. This occurs when MCLK is\nsourced from HSCLK (SYSPLL/HFXT), i.e. MCLK \u003e 32 MHz.\n\nThis affects OpenOCD reads (via DAP AHB-AP) in mspm0_read_part_info().\n\nFix this by checking SYSCTL_MCLKCFG before reading FACTORYREGION. If\nUSEHSCLK is set and FLASHWAIT \u003d\u003d 2, temporarily switch MCLK to SYSOSC\n(≤ 32 MHz), perform the reads (DID, TRACEID, USERID, SRAMFLASH), and\nthen restore the original MCLK configuration. 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