)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"6507d063_592bb538","updated":"2026-06-06 21:45:00.000000000","message":"Thanks for this patch.\nApart from some minor typo, I see something strange on the reset that should be clarified.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"999ab0e3b728400ca3a4769460401dd39d5edd06","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":4,"id":"26c11e45_dc20f2eb","updated":"2026-06-17 07:16:19.000000000","message":"Thanks for your very helpful review. I was able to run the confirming tests on the Dahlia+Verdin board(s). With the newest corrects everything works under the most recent build snapshot from main.","commit_id":"dfc17b276ff9fbc4f7f5b537f25daba75c275c83"}],"tcl/board/toradex/dahlia-imx95.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":true,"context_lines":[{"line_number":1,"context_line":"# SPDX-License-Identifier: GPL-2.0-or-later"},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Configuration file for the Toradex Dahlia base board"},{"line_number":4,"context_line":"# with a Verdin IMX95 module inseted (IMX9596)."},{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":"# Could specify external adpater by:"},{"line_number":7,"context_line":"# openocd -f interface/jlink.cfg -f board/nxp/imx8ulp-evk.cfg"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"a52e5531_6135e283","line":4,"updated":"2026-06-06 21:45:00.000000000","message":"typo! s/inseted/inserted/ ???","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"0cdbae40335be112bb6224f1bb8d2768050a8696","unresolved":false,"context_lines":[{"line_number":1,"context_line":"# SPDX-License-Identifier: GPL-2.0-or-later"},{"line_number":2,"context_line":"#"},{"line_number":3,"context_line":"# Configuration file for the Toradex Dahlia base board"},{"line_number":4,"context_line":"# with a Verdin IMX95 module inseted (IMX9596)."},{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":"# Could specify external adpater by:"},{"line_number":7,"context_line":"# openocd -f interface/jlink.cfg -f board/nxp/imx8ulp-evk.cfg"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"4af8d42c_9aa536ca","line":4,"in_reply_to":"a52e5531_6135e283","updated":"2026-06-08 07:31:33.000000000","message":"Done","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":true,"context_lines":[{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":"# Could specify external adpater by:"},{"line_number":7,"context_line":"# openocd -f interface/jlink.cfg -f board/nxp/imx8ulp-evk.cfg"},{"line_number":8,"context_line":"# otherwise use FTDI-based JTAG adapte by default."},{"line_number":9,"context_line":"#"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"if { [adapter name] eq \"undefined\" } {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"4c5fb44b_d8291e85","line":8,"updated":"2026-06-06 21:45:00.000000000","message":"typo s/adapte/adapter/","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"0cdbae40335be112bb6224f1bb8d2768050a8696","unresolved":false,"context_lines":[{"line_number":5,"context_line":"#"},{"line_number":6,"context_line":"# Could specify external adpater by:"},{"line_number":7,"context_line":"# openocd -f interface/jlink.cfg -f board/nxp/imx8ulp-evk.cfg"},{"line_number":8,"context_line":"# otherwise use FTDI-based JTAG adapte by default."},{"line_number":9,"context_line":"#"},{"line_number":10,"context_line":""},{"line_number":11,"context_line":"if { [adapter name] eq \"undefined\" } {"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"41abcc31_62a1d729","line":8,"in_reply_to":"4c5fb44b_d8291e85","updated":"2026-06-08 07:31:33.000000000","message":"Done","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":true,"context_lines":[{"line_number":23,"context_line":"set CHIPNAME imx95"},{"line_number":24,"context_line":"set CHIPCORES 6"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# Reset the entire board"},{"line_number":27,"context_line":"# The iMX95 \"Verdin\" SoM doesn\u0027t connect the nTRST so we have to execute a full board reset"},{"line_number":28,"context_line":"proc init_reset {mode} {"},{"line_number":29,"context_line":"\t# Assert board reset"},{"line_number":30,"context_line":"\tadapter assert trst"},{"line_number":31,"context_line":"\tsleep 100"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"\t# Deassert board reset"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"bd906452_968c3515","line":30,"range":{"start_line":26,"start_character":2,"end_line":30,"end_character":20},"updated":"2026-06-06 21:45:00.000000000","message":"I\u0027m checking the datasheet of verdin board.\nhttps://docs.toradex.com/107809-dahlia-carrier-board-datasheet.pdf\nLooks like they use a standard 10 pin jtag connector, as in\nhttps://www.keil.com/support/man/docs/jlink/jlink_connectors.asp\nbut they got fun renaming the reset pin as `JTAG_1_TRST#`. In the datasheet\nhttps://www.mouser.com/pdfDocs/smarc_imx95_datasheet.pdf\nthe signal `JTAG_TRST#` is connected to the reset input.\n\nDon\u0027t know why they mislead users calling `TRST` a signal that is the `SRST` of the platform. Is `TRST` a mad way to say `Toradex ReSeT`?\n\nSince you have defined the TRST pin in the adapter script, this script you have to replace the standard `init_reset` procedure with a toggling of TRST!\nI suggest you rename the output of the adapter as SRST so you can drop this `init_reset`.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"78c86b6d68e726809aa571e1a47a4d1d971911bd","unresolved":true,"context_lines":[{"line_number":23,"context_line":"set CHIPNAME imx95"},{"line_number":24,"context_line":"set CHIPCORES 6"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# Reset the entire board"},{"line_number":27,"context_line":"# The iMX95 \"Verdin\" SoM doesn\u0027t connect the nTRST so we have to execute a full board reset"},{"line_number":28,"context_line":"proc init_reset {mode} {"},{"line_number":29,"context_line":"\t# Assert board reset"},{"line_number":30,"context_line":"\tadapter assert trst"},{"line_number":31,"context_line":"\tsleep 100"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"\t# Deassert board reset"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"ff6f606b_c237f6e5","line":30,"range":{"start_line":26,"start_character":2,"end_line":30,"end_character":20},"in_reply_to":"213a4427_5eb96243","updated":"2026-06-08 09:18:10.000000000","message":"Thanks for pointing to the right documentation.\n\nTo summarize (please confirm):\n- the board\u0027s signal capable of resetting the imx95 is named DBG_RESET;\n\n- the board has an additional signal named TRST, but this does not reach the imx95, so apparently useless;\n\n- OpenOCD cannot toggle the DBG_RESET through the onboard FTDI chip. This is a limitation of current OpenOCD that only drives one FTDI channel. The board has JTAG signals on channel 1/B while DBG_RESET is on channel 0/A;\n\n- OpenOCD can toggle the TRST through the onboard FTDI, as it\u0027s on the same JTAG channel 1/B;\n\n- the pin 10 of the JTAG connector for external adapters is connected to the board signal TRST, while most adapters in the market (e.g. JLink) use this pin for the SRST to reset the target.\n\nTo allow OpenOCD to reset the imx95, you have connected together the signals DBG_RESET and TRST. I expect you did it by soldering a wire, as in the schematics I don\u0027t see any possible jumper to achieve this.\nI agree, this is the simpler workaround. But this rework should be documented in this board file, otherwise there is no way for other users to re-use this file.\nAdding also detailed info on where the wire is soldered could be really useful.\n\nWith the workaround above, the signal TRST becomes de-facto the SRST signal used by OpenOCD and by the external adapter to reset the target.\nI still think that in the interface script we should call it nSRST, but adding a comment to explain that it is named TRST in the schematic, but it\u0027s used as SRST through the soldered wire.\nAnd this would drop the need of this init_reset proc.\nTo handle the delay below, add\n`adapter srst pulse_width 100`\n`adapter srst delay 7000`\n\nThe reason I\u0027m so strongly against overriding `init_reset` is that I would like to modify it in the future, together with a rework of the reset framework. Any board or target file that replaces init_reset (already 8 files upstream) is an issue for such rework.\n\nYou also wrote that you don\u0027t own the board anymore. How could any modification be tested?","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"0cdbae40335be112bb6224f1bb8d2768050a8696","unresolved":true,"context_lines":[{"line_number":23,"context_line":"set CHIPNAME imx95"},{"line_number":24,"context_line":"set CHIPCORES 6"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# Reset the entire board"},{"line_number":27,"context_line":"# The iMX95 \"Verdin\" SoM doesn\u0027t connect the nTRST so we have to execute a full board reset"},{"line_number":28,"context_line":"proc init_reset {mode} {"},{"line_number":29,"context_line":"\t# Assert board reset"},{"line_number":30,"context_line":"\tadapter assert trst"},{"line_number":31,"context_line":"\tsleep 100"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"\t# Deassert board reset"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"213a4427_5eb96243","line":30,"range":{"start_line":26,"start_character":2,"end_line":30,"end_character":20},"in_reply_to":"bd906452_968c3515","updated":"2026-06-08 07:31:33.000000000","message":"The Dahlia carrier board has two different reset signals: TRST and DBG_RESET \u003d CTRL_RESET_MICO\n\nTRST is connected to pin 10 of the JTAG connector, the card edge connector of the SoM, and BDBUS4 of the FTDI chip.\n\nDBG_RESET (ADBUS5 on the FTDI) is connected to CTRL_RESET_MICO which is connected to header X5 and and the SoM connector.\nhttps://docs.toradex.com/109850-dahlia-carrier-board-v1.1-pdf-schematics.zip\n\nOn the Verdin SoM board, however, TRST is not connected. See page 17 of\nhttps://docs.toradex.com/200007-verdin_imx95_datasheet.pdf\nCTRL_RESET_MICO is the only reset implemented.\n(Note: You linked the datasheet for the Smarc SoM which is a different SoM and not compatible with the Dahlia carrier board.)\n\nThe only way to issue a reset is by triggering CTRL_RESET_MICO. Since this signal is connected to a different port on the FTDI chip (port A, while the JTAG signals are on port B) and OpenOCD can\u0027t access both ports at the same time, the workaround is to install a link between TRST and CTRL_RESET_MICO. We then toggle the TRST line - since that is the one we have control over - to issue CTRL_RESET_MICO.\n\nYes, it is quite unintentional and complicated. Other carrier boards connect DBG_RESET to port B, giving us direct access to that signal and other SoMs connect JTAG_TRST. Only the combination of Dahlia with Verdin combines both problems. However, this is the combination they\u0027ll send if you order an IMX95 evaluation kit.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"999ab0e3b728400ca3a4769460401dd39d5edd06","unresolved":false,"context_lines":[{"line_number":23,"context_line":"set CHIPNAME imx95"},{"line_number":24,"context_line":"set CHIPCORES 6"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# Reset the entire board"},{"line_number":27,"context_line":"# The iMX95 \"Verdin\" SoM doesn\u0027t connect the nTRST so we have to execute a full board reset"},{"line_number":28,"context_line":"proc init_reset {mode} {"},{"line_number":29,"context_line":"\t# Assert board reset"},{"line_number":30,"context_line":"\tadapter assert trst"},{"line_number":31,"context_line":"\tsleep 100"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"\t# Deassert board reset"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"1ea66fc6_11f5482b","line":30,"range":{"start_line":26,"start_character":2,"end_line":30,"end_character":20},"in_reply_to":"eae1644c_7ec6137c","updated":"2026-06-17 07:16:19.000000000","message":"Okay, the colleague and I met. I tested the scripts on the board using a recent snapshot build from the github page. I just submitted any necessary adaptions (had to change -data to -ndata in the FTDI config, somehow I overlooked that earlier) and can now confirm it works as intended.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"1351ae1c9bf87f28260f07a633d2f4230a8bf2c1","unresolved":true,"context_lines":[{"line_number":23,"context_line":"set CHIPNAME imx95"},{"line_number":24,"context_line":"set CHIPCORES 6"},{"line_number":25,"context_line":""},{"line_number":26,"context_line":"# Reset the entire board"},{"line_number":27,"context_line":"# The iMX95 \"Verdin\" SoM doesn\u0027t connect the nTRST so we have to execute a full board reset"},{"line_number":28,"context_line":"proc init_reset {mode} {"},{"line_number":29,"context_line":"\t# Assert board reset"},{"line_number":30,"context_line":"\tadapter assert trst"},{"line_number":31,"context_line":"\tsleep 100"},{"line_number":32,"context_line":""},{"line_number":33,"context_line":"\t# Deassert board reset"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"eae1644c_7ec6137c","line":30,"range":{"start_line":26,"start_character":2,"end_line":30,"end_character":20},"in_reply_to":"ff6f606b_c237f6e5","updated":"2026-06-10 08:23:36.000000000","message":"Yes, I can confirm your understanding is correct.\n\nI reworked the files accordingly and included a detailed explanation. I also explain which pins should be connected for the workaround.\n\nAs for testing I\u0027ll see if I can get the board back for a day or two next week. Or I\u0027ll have a remote test session with the colleague who currently owns it. I\u0027ll report back when I had a chance to verify the files still work.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"}],"tcl/interface/ftdi/toradex-dahlia.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":true,"context_lines":[{"line_number":4,"context_line":"#"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"adapter driver ftdi"},{"line_number":7,"context_line":"ftdi vid_pid 0x0403 0x6011"},{"line_number":8,"context_line":"ftdi channel 1"},{"line_number":9,"context_line":""},{"line_number":10,"context_line":"ftdi layout_init 0x0098 0x009b"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"3b913be2_52f5d211","line":7,"updated":"2026-06-06 21:45:00.000000000","message":"This command has been deprecated few weeks ago. See\nhttps://review.openocd.org/c/openocd/+/9591\nPlease replace it with\n`adapter usb vid_pid 0x0403 0x6011`","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"0cdbae40335be112bb6224f1bb8d2768050a8696","unresolved":false,"context_lines":[{"line_number":4,"context_line":"#"},{"line_number":5,"context_line":""},{"line_number":6,"context_line":"adapter driver ftdi"},{"line_number":7,"context_line":"ftdi vid_pid 0x0403 0x6011"},{"line_number":8,"context_line":"ftdi channel 1"},{"line_number":9,"context_line":""},{"line_number":10,"context_line":"ftdi layout_init 0x0098 0x009b"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"c7d8972e_75b9e258","line":7,"in_reply_to":"3b913be2_52f5d211","updated":"2026-06-08 07:31:33.000000000","message":"Done","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":true,"context_lines":[{"line_number":13,"context_line":"#ftdi_layout_signal TDI -data 0x02 -noe 0x02"},{"line_number":14,"context_line":"#ftdi_layout_signal TDO -input 0x04"},{"line_number":15,"context_line":"#ftdi_layout_signal TMS -data 0x08 -noe 0x08"},{"line_number":16,"context_line":"ftdi layout_signal nTRST -data 0x0010"},{"line_number":17,"context_line":"ftdi layout_signal LED -data 0x0080"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"reset_config trst_only trst_push_pull"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"c77aa672_ec4b7325","line":16,"updated":"2026-06-06 21:45:00.000000000","message":"this should be `nSRST`, as I explained in another comment.\nAlso the `reset_config` below should be aligned","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"999ab0e3b728400ca3a4769460401dd39d5edd06","unresolved":false,"context_lines":[{"line_number":13,"context_line":"#ftdi_layout_signal TDI -data 0x02 -noe 0x02"},{"line_number":14,"context_line":"#ftdi_layout_signal TDO -input 0x04"},{"line_number":15,"context_line":"#ftdi_layout_signal TMS -data 0x08 -noe 0x08"},{"line_number":16,"context_line":"ftdi layout_signal nTRST -data 0x0010"},{"line_number":17,"context_line":"ftdi layout_signal LED -data 0x0080"},{"line_number":18,"context_line":""},{"line_number":19,"context_line":"reset_config trst_only trst_push_pull"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"5f95c0ea_18caf07a","line":16,"in_reply_to":"c77aa672_ec4b7325","updated":"2026-06-17 07:16:19.000000000","message":"Done","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":true,"context_lines":[{"line_number":19,"context_line":"reset_config trst_only trst_push_pull"},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"echo \"Info: Using FTDI adapter. Make sure J6 is open.\""},{"line_number":22,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"c3f78761_5387e7e0","line":22,"updated":"2026-06-06 21:45:00.000000000","message":"drop the extra empty line at the end of the file","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"0cdbae40335be112bb6224f1bb8d2768050a8696","unresolved":false,"context_lines":[{"line_number":19,"context_line":"reset_config trst_only trst_push_pull"},{"line_number":20,"context_line":""},{"line_number":21,"context_line":"echo \"Info: Using FTDI adapter. Make sure J6 is open.\""},{"line_number":22,"context_line":""}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"4243724a_2d8305e8","line":22,"in_reply_to":"c3f78761_5387e7e0","updated":"2026-06-08 07:31:33.000000000","message":"Done","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"}],"tcl/target/nxp/imx95.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"5cfc7e38e5ec247d25e44fcf81d4a4a1d1a47ffc","unresolved":true,"context_lines":[{"line_number":48,"context_line":"# note: could not test this"},{"line_number":49,"context_line":"#target create ${_CHIPNAME}.m33 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3"},{"line_number":50,"context_line":"# declare the auxiliary Cortex-M7 core on AP #?"},{"line_number":51,"context_line":"# note: I don\u0027t know which AP it is on."},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# AHB-AP for direct access to soc bus"},{"line_number":54,"context_line":"target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"1fbd83be_9ff65512","line":51,"updated":"2026-06-06 21:45:00.000000000","message":"You should be able to dump the debug ROM table, if the AP is clocked, by attaching on the telnet port of OpenOCD and running\n```\nimx95.dap info 0\nimx95.dap info 1\n...\n```\nand looking for the Cortex-M7.\nIf it is clocked, it should be accessible.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"0cdbae40335be112bb6224f1bb8d2768050a8696","unresolved":true,"context_lines":[{"line_number":48,"context_line":"# note: could not test this"},{"line_number":49,"context_line":"#target create ${_CHIPNAME}.m33 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3"},{"line_number":50,"context_line":"# declare the auxiliary Cortex-M7 core on AP #?"},{"line_number":51,"context_line":"# note: I don\u0027t know which AP it is on."},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# AHB-AP for direct access to soc bus"},{"line_number":54,"context_line":"target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"cdbca1a5_a8d2fb97","line":51,"in_reply_to":"1fbd83be_9ff65512","updated":"2026-06-08 07:31:33.000000000","message":"Thanks for letting me know. Unfortunately, I already had to give back the board, so I can\u0027t test it any more.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"},{"author":{"_account_id":1002526,"name":"Florian Huehn","display_name":"Florian Huehn","email":"florian.huehn@googlemail.com","username":"florianhuehn"},"change_message_id":"999ab0e3b728400ca3a4769460401dd39d5edd06","unresolved":false,"context_lines":[{"line_number":48,"context_line":"# note: could not test this"},{"line_number":49,"context_line":"#target create ${_CHIPNAME}.m33 cortex_m -dap ${_CHIPNAME}.dap -ap-num 3"},{"line_number":50,"context_line":"# declare the auxiliary Cortex-M7 core on AP #?"},{"line_number":51,"context_line":"# note: I don\u0027t know which AP it is on."},{"line_number":52,"context_line":""},{"line_number":53,"context_line":"# AHB-AP for direct access to soc bus"},{"line_number":54,"context_line":"target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 1"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"e85e4cba_279d746a","line":51,"in_reply_to":"cdbca1a5_a8d2fb97","updated":"2026-06-17 07:16:19.000000000","message":"I ran the above commands. The output is at https://pastebin.com/9TTNNGzr . I can\u0027t see any further cores.\n\nIs it possible that the access to the M33 core is locked down as it runs the SMU firmware and the whole thing is quite heavily security protected?\nThe M7 is likely down and powered off.\nI\u0027d like to leave this to someone else to figure out when and if they really do need the direct access to these cores.","commit_id":"8deff89bfa642dbb0b928a92f4dd4ae4d09ba337"}]}