)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1001667,"name":"Jan Matyas","email":"jan.matyas@codasip.com","username":"JanMatCodasip"},"change_message_id":"f22d1a93df098a91c044b3c5e38a95ce4f9e2406","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"55f6e7d6_8c8be7c9","updated":"2026-06-25 13:19:15.000000000","message":"**Building a RISC-V FreeRTOS demo that runs on Spike RISC-V ISA simulator:**\n\n1) Obtain RISC-V baremetal toolchain from:\nhttps://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/blog/2025/10/23/riscv-none-elf-gcc-v15-2-0-1-released/\n\n2) Clone the FreeRTOS repository from: \nhttps://github.com/FreeRTOS/FreeRTOS\n\n3) Go to this demo directory:\n`cd FreeRTOS/Demo/RISC-V-spike-htif_GCC`\n\n4) In order for the demo to work with the current OpenOCD and RISC-V\ntoolchain, you may need to apply my patch, published here:\nhttps://github.com/FreeRTOS/FreeRTOS/pull/1415\n\n5) Build the demo via this command:\n\n```\nPATH\u003d/YOUR/PATH/TO/xpack-riscv-none-elf-gcc-15.2.0-1/bin:$PATH \\\n  make CROSS\u003driscv-none-elf- DEBUG\u003d1 BASE_ADDRESS\u003d0x20000000\n```\n\nNote: The base address must be set to a value lower \nthan 0x8000_0000 due to this GDB bug:\nhttps://sourceware.org/bugzilla/show_bug.cgi?id\u003d34316\n\n6) Ensure that `build/RTOSDemo32.axf` file has been created.\n\n\n-\n\n---\n\n-\n\n\n**Launching the demo:**\n\n1) Obtain the Spike RISC-V ISA simulator by buiding it from source:\nhttps://github.com/riscv-software-src/riscv-isa-sim\n\n2) Launch the demo by:\n\n/YOUR/PATH/TO/bin/spike -p1 --isa rv32ima_zicsr \\\n  -m0x20000000:0x10000000 \\\n  --rbb-port 9824 \\\n  build/RTOSDemo32.axf\n\n3) Check that the demo program runs correctly - you should see these\nperiodic prints in the terminal:\n\n```\nHello FreeRTOS!\n0: Tx: send 1\n0: Rx: received 1\n0: Tx: send 2\n0: Rx: received 2\n...\n```\n\n-\n\n---\n\n-\n\n**Launching OpenOCD and GDB:**\n\n1) Ensure that Spike is running (per the previous instructions)\n\n2) Build OpenOCD from source from this patch\n\n3) Make sure that you have applied changes \nfrom https://github.com/FreeRTOS/FreeRTOS/pull/1415\nto the spike-1.cfg file, as instructed above.\n\n4) Launch OpenOCD by this command\n\n```\n/PATH/TO/YOUR/bin/openocd -f spike-1.cfg -d3 2\u003e\u00261 | tee log.txt\n```\n\n5) In another terminal, launch GDB by command:\n\n```\n/PATH/TO/YOUR/xpack-riscv-none-elf-gcc-15.2.0-1/bin/riscv-none-elf-gdb \\\n  PATH/TO/YOUR/build/RTOSDemo32.axf \\\n  -ex \"target extended-remote localhost:3333\" \\\n  -ex \"info threads\"\n```\n\n6) Observe that information about the threads have been printed:\n\n```\n  Id   Target Id                                            Frame \n* 1    Thread 537408240 \"IDLE\" (Name: IDLE, State: Running) prvIdleTask (pvParameters\u003d\u003coptimized out\u003e)\n    at \u003cSOME_PATH\u003e/FreeRTOS/Source/tasks.c:5836\n  2    Thread 537406064 \"Tx\" (Name: Tx)                     xTaskDelayUntil (\n    pxPreviousWakeTime\u003dpxPreviousWakeTime@entry\u003d0x20082a3c \u003cucHeap+8396\u003e, xTimeIncrement\u003d1, xTimeIncrement@entry\u003d10)\n    at \u003cSOME_PATH\u003e/FreeRTOS/Source/tasks.c:2464\n  3    Thread 537409008 \"Tmr Svc\" (Name: Tmr Svc)           prvProcessTimerOrBlockTask (xNextExpireTime\u003d1, \n    xListWasEmpty\u003d-1515870811)\n    at \u003cSOME_PATH\u003e/FreeRTOS/Source/timers.c:824\n  4    Thread 537401840 \"Rx\" (Name: Rx)                     xQueueReceive (xQueue\u003d0xa5a5a5a5, pvBuffer\u003d0x0, \n    pvBuffer@entry\u003d0x20081994 \u003cucHeap+4132\u003e, xTicksToWait\u003d\u003coptimized out\u003e, xTicksToWait@entry\u003d4294967295)\n    at \u003cSOME_PATH\u003e/FreeRTOS/Source/queue.c:1621\n\n```\n\n\n-\n\n---\n\n\n\n\n**TODOs:**\n\n- This is a crude prototype only, provided without guarantees. \nThere are almost certainly bugs. Everything should be double-checked.\n\n- This draft only contains RV32I register stackings. \nOther RISC-V stackings (e.g. RV64I, RV32I + F/D, ..., ...) need to\nbe implemented, too.\n\n- We should agree on a cleaner approach how to pick the register\nstackings depending on target type and target properties (like\nregister widths, implemented extensions, etc.) - a mechanism that\ncould be shared between ARM Cortex and RISC-V.\n\n- The above-mentioned GDB bug related to thread IDs should be fixed:\nhttps://sourceware.org/bugzilla/show_bug.cgi?id\u003d34316","commit_id":"733641b208cd2f5a9e07e4b5b0d62efd9e4ae93e"}]}