)]}'
{"/PATCHSET_LEVEL":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"e39cc971759acb677937c77f366d704ed7b93ee9","unresolved":true,"context_lines":[],"source_content_type":"","patch_set":1,"id":"214618f8_f5b0c1da","updated":"2026-07-07 17:08:55.000000000","message":"Hi Craig,\nthanks for your contribution to OpenOCD.\n\nI\u0027m a little confused by this new board script.\nFrom the website, the board has the FTDI device USB-to-JTAG to control a GoWIN FPGA, but the script does not include a command like\n`pld create ... gowin ...`\n\nI was even expecting to see inside something like:\n```\nadapter driver ftdi\n...\nset _CHIPNAME GW1NR-9C\n\nsource [find fpga/gowin_gw1n.cfg]\n```\n\nWhat is the use case and what is the full command line you use for OpenOCD?\n\nThe support for the GoWIN FPGA has been introduced after the tag v0.12.0. Maybe you are using an old version of OpenOCD that still doesn\u0027t have it.","commit_id":"7e6d61336341d223674f181866967236f832106b"},{"author":{"_account_id":1002540,"name":"BrisbaneSilicon","email":"support@brisbanesilicon.com.au","username":"BrisbaneSilicon"},"change_message_id":"24a8fe1e5c5e2c476a9b5e66f615a40df297d74d","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"da64eafa_2a51381e","in_reply_to":"214618f8_f5b0c1da","updated":"2026-07-09 02:45:57.000000000","message":"Hi Antonio,\n\nNo worries, happy to contribute to expanding OpenOCD.\n\nI was using the brs-100-gw1nr9.cfg file with OpenOCD 0.12.0, which was installed with \u0027sudo apt install openocd\u0027 - I removed that version and installed from source (sudo make install) and I was able to use the \u0027source [find fpga/gowin_gw1n.cfg]\u0027 line.\n\nIn resolving this review, I noticed I didn\u0027t follow the Patch Guidelines for adding support for new boards, specifically that the .cfg files should be in a \u003cvendor\u003e directory. I\u0027ve fixed that as well.\n\nThe new patch is here: https://review.openocd.org/c/openocd/+/9778\n\nCould you please review ?\n\nJust FYI, this is how I am using OpenOCD: https://github.com/BrisbaneSilicon/BRS-100-GW1NR9#openocd-setup\n\nThen I run \u0027fcapz --backend openocd --port 6666 --tap GW1NR-9C.tap probe\u0027, as per https://github.com/BrisbaneSilicon/BRS-100-GW1NR9#embedded-logic-analyzer to communicate with my ELA.\n\nI suppose once OpenOCD supports the BRS-100-GW1NR9 natively, I can stop providing a custom cfg file (https://github.com/BrisbaneSilicon/BRS-100-GW1NR9/blob/public/foreign/openocd/brs_100_gw1nr9.cfg) and instructions on how to use it...\n\nI suppose this patch can just be abandoned ?","commit_id":"7e6d61336341d223674f181866967236f832106b"},{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"893cd367b10a8505449c82c6dcd936d54515e8cb","unresolved":false,"context_lines":[],"source_content_type":"","patch_set":1,"id":"e2675857_3c4e089a","in_reply_to":"da64eafa_2a51381e","updated":"2026-07-09 11:54:29.000000000","message":"The patch 9778 is ok, I will wait for any eventual comment, then I will merge it in few days.\nYes, I think this can be abandoned","commit_id":"7e6d61336341d223674f181866967236f832106b"}],"tcl/board/brs_100_gw1nr9.cfg":[{"author":{"_account_id":1000021,"name":"Antonio Borneo","email":"borneo.antonio@gmail.com","username":"borneoa"},"change_message_id":"e39cc971759acb677937c77f366d704ed7b93ee9","unresolved":true,"context_lines":[{"line_number":15,"context_line":"set _IDCODE   0x1100481B"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"jtag newtap $_CHIPNAME tap -irlen 8 -expected-id $_IDCODE"},{"line_number":18,"context_line":"init"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"91e6c9c3_e94092f3","line":18,"updated":"2026-07-07 17:08:55.000000000","message":"The command `init` should not be in the board file; it is already run automatically by OpenOCD.\nAny reason for having it here?\nSame comment for the next patch in this series.","commit_id":"7e6d61336341d223674f181866967236f832106b"},{"author":{"_account_id":1002540,"name":"BrisbaneSilicon","email":"support@brisbanesilicon.com.au","username":"BrisbaneSilicon"},"change_message_id":"24a8fe1e5c5e2c476a9b5e66f615a40df297d74d","unresolved":false,"context_lines":[{"line_number":15,"context_line":"set _IDCODE   0x1100481B"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"jtag newtap $_CHIPNAME tap -irlen 8 -expected-id $_IDCODE"},{"line_number":18,"context_line":"init"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"9f7d0362_19965880","line":18,"in_reply_to":"91e6c9c3_e94092f3","updated":"2026-07-09 02:45:57.000000000","message":"Done","commit_id":"7e6d61336341d223674f181866967236f832106b"},{"author":{"_account_id":1002540,"name":"BrisbaneSilicon","email":"support@brisbanesilicon.com.au","username":"BrisbaneSilicon"},"change_message_id":"24a8fe1e5c5e2c476a9b5e66f615a40df297d74d","unresolved":false,"context_lines":[{"line_number":15,"context_line":"set _IDCODE   0x1100481B"},{"line_number":16,"context_line":""},{"line_number":17,"context_line":"jtag newtap $_CHIPNAME tap -irlen 8 -expected-id $_IDCODE"},{"line_number":18,"context_line":"init"}],"source_content_type":"text/x-ttcn-cfg","patch_set":1,"id":"e30a6c93_1730c0d0","line":18,"in_reply_to":"91e6c9c3_e94092f3","updated":"2026-07-09 02:45:57.000000000","message":"Done","commit_id":"7e6d61336341d223674f181866967236f832106b"}]}