1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
10 @title Open On-Chip Debugger (openocd)
11 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
12 @subtitle @value{UPDATED}
14 @vskip 0pt plus 1filll
19 @node Top, About, , (dir)
22 This is edition @value{EDITION} of the openocd manual for version
23 @value{VERSION}, @value{UPDATED}
26 * About:: About Openocd.
28 * Building:: Building Openocd
29 * Running:: Running Openocd
30 * Configuration:: Openocd Configuration.
31 * Commands:: Openocd Commands
32 * Sample Scripts:: Sample Target Scripts
33 * FAQ:: Frequently Asked Questions
34 * License:: GNU Free Documentation License
42 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
43 and boundary-scan testing for embedded target devices. The targets are interfaced
44 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
45 connection types in the future.
47 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
48 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
49 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
50 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
52 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
53 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
54 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
60 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
61 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
62 Others interested in improving the state of free and open debug and testing technology
63 are welcome to participate.
65 Other developers have contributed support for additional targets and flashes as well
66 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
70 @cindex building openocd
72 You can download the current SVN version with SVN client of your choice from the
73 following repositories:
75 (@uref{svn://svn.berlios.de/openocd/trunk})
79 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
81 Using the SVN command line client, you could use the following command to fetch the
82 latest version (make sure there is no (non-svn) directory called "openocd" in the
86 svn checkout svn://svn.berlios.de/openocd/trunk
89 Building the OpenOCD requires a recent version of the GNU autotools.
90 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
91 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
92 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
93 paths, resulting in obscure dependency errors (This is an observation I've gathered
94 from the logs of one user - correct me if I'm wrong).
96 You further need the appropriate driver files, if you want to build support for
97 a FTDI FT2232 based interface:
99 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
100 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
101 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
102 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
105 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
106 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
108 In general, the D2XX driver provides superior performance (several times as fast),
109 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
110 a kernel module, only a user space library.
112 To build OpenOCD (on both Linux and Cygwin), use the following commands:
116 Bootstrap generates the configure script, and prepares building on your system.
120 Configure generates the Makefiles used to build OpenOCD
124 Make builds the OpenOCD, and places the final executable in ./src/
126 The configure script takes several options, specifying which JTAG interfaces
133 --enable-parport_ppdev
135 --enable-amtjtagaccel
137 --enable-ft2232_ftd2xx
138 @footnote{Using the latest D2XX drivers from FTDI and following their installation
139 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
142 --enable-ft2232_libftdi
144 --with-ftd2xx=/path/to/d2xx/
147 If you want to access the parallel port using the PPDEV interface you have to specify
148 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
149 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
150 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
152 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
153 absolute path containing no spaces.
155 Linux users should copy the various parts of the D2XX package to the appropriate
156 locations, i.e. /usr/include, /usr/lib.
160 @cindex running openocd
161 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
162 Run with @option{--help} or @option{-h} to view the available command line arguments.
164 It reads its configuration by default from the file openocd.cfg located in the current
165 working directory. This may be overwritten with the @option{-f <configfile>} command line
168 To enable debug output (when reporting problems or working on OpenOCD itself), use
169 the @option{-d} command line switch. This sets the debug_level to "3", outputting
170 the most information, including debug messages. The default setting is "2", outputting
171 only informational messages, warnings and errors. You can also change this setting
172 from within a telnet or gdb session (@option{debug_level <n>}).
174 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
177 @chapter Configuration
178 @cindex configuration
179 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
180 by default from the file openocd.cfg in the current directory. A different configuration
181 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
183 The configuration file is used to specify on which ports the daemon listens for new
184 connections, the JTAG interface used to connect to the target, the layout of the JTAG
185 chain, the targets that should be debugged, and connected flashes.
187 @section Daemon configuration
190 @item @b{telnet_port} <@var{number}>
192 Port on which to listen for incoming telnet connections
193 @item @b{gdb_port} <@var{number}>
195 First port on which to listen for incoming GDB connections. The GDB port for the
196 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
197 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
198 @cindex daemon_startup
199 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
200 if it should just attach to the target.
203 @section JTAG interface configuration
206 @item @b{interface} <@var{name}>
208 Use the interface driver <@var{name}> to connect to the target. Currently supported
212 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
216 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
221 FTDI FT2232 based devices using either the open-source libftdi or the binary only
222 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
223 platform. The libftdi uses libusb, and should be portable to all systems that provide
228 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
233 @item @b{jtag_speed} <@var{number}>
235 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
236 speed. The actual effect of this option depends on the JTAG interface used.
238 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
240 The configuration of the reset signals available on the JTAG interface AND the target.
241 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
242 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
243 @samp{srst_only} or @samp{trst_and_srst}.
244 [@var{combination}] is an optional value specifying broken reset signal implementations.
245 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
246 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
247 that the system is reset together with the test logic (only hypothetical, I haven't
248 seen hardware with such a bug, and can be worked around).
250 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
251 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
252 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
253 (default) and @samp{srst_push_pull} for the system reset. These values only affect
254 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
256 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
258 Describes the devices that form the JTAG daisy chain, with the first device being
259 the one closest to TDO. The parameters are the length of the instruction register
260 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
261 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
262 The IDCODE instruction will in future be used to query devices for their JTAG
263 identification code. This line is the same for all ARM7 and ARM9 devices.
264 Other devices, like CPLDs, require different parameters. An example configuration
265 line for a Xilinx XC9500 CPLD would look like this:
267 jtag_device 8 0x01 0x0e3 0xfe
269 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
270 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
271 The IDCODE instruction is 0xfe.
273 @item @b{jtag_nsrst_delay} <@var{ms}>
274 @cindex jtag_nsrst_delay
275 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
276 starting new JTAG operations.
277 @item @b{jtag_ntrst_delay} <@var{ms}>
278 @cindex jtag_ntrst_delay
279 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
280 starting new JTAG operations.
282 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
283 or on-chip features) keep a reset line asserted for some time after the external reset
287 @section parport options
290 @item @b{parport_port} <@var{number}>
292 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
293 the @file{/dev/parport} device
295 When using PPDEV to access the parallel port, use the number of the parallel port:
296 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
297 you may encounter a problem.
298 @item @b{parport_cable} <@var{name}>
299 @cindex parport_cable
300 The layout of the parallel port cable used to connect to the target.
301 Currently supported cables are
305 Original Wiggler layout, also supported by several clones, such
306 as the Olimex ARM-JTAG
307 @item old_amt_wiggler
308 @cindex old_amt_wiggler
309 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
310 version available from the website uses the original Wiggler layout ('@var{wiggler}')
313 Describes the connection of the Amontec Chameleon's CPLD when operated in
314 configuration mode. This is only used to program the Chameleon itself, not
318 Xilinx Parallel cable III.
321 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
322 This is also the layout used by the HollyGates design
323 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
328 @item @b{parport_write_on_exit} <@var{on|off}>
329 @cindex parport_write_on_exit
330 This will configure the parallel driver to write a known value to the parallel
331 interface on exiting openocd
334 @section amt_jtagaccel options
336 @item @b{parport_port} <@var{number}>
338 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
339 @file{/dev/parport} device
341 @section ft2232 options
344 @item @b{ft2232_device_desc} <@var{description}>
345 @cindex ft2232_device_desc
346 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
347 default value is used. This setting is only valid if compiled with FTD2XX support.
348 @item @b{ft2232_layout} <@var{name}>
349 @cindex ft2232_layout
350 The layout of the FT2232 GPIO signals used to control output-enables and reset
351 signals. Valid layouts are
354 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
356 Amontec JTAGkey and JTAGkey-tiny
362 American Microsystems M5960
364 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
365 SRST signals on external connector
369 Hitex STM32 Performance Stick
372 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
373 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
374 default values are used. This command is not available on Windows.
375 @item @b{ft2232_latency} <@var{ms}>
376 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
377 ft2232_read() fails to return the expected number of bytes. This can be caused by
378 USB communication delays and has proved hard to reproduce and debug. Setting the
379 FT2232 latency timer to a larger value increases delays for short USB packages but it
380 also reduces the risk of timeouts before receiving the expected number of bytes.
381 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
384 @section ep93xx options
385 @cindex ep93xx options
386 Currently, there are no options available for the ep93xx interface.
389 @section Target configuration
392 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
395 Defines a target that should be debugged. Currently supported types are:
408 If you want to use a target board that is not on this list, see Adding a new
411 Endianess may be @option{little} or @option{big}.
413 The reset_mode specifies what should happen to the target when a reset occurs:
417 Immediately request a target halt after reset. This allows targets to be debugged
418 from the very first instruction. This is only possible with targets and JTAG
419 interfaces that correctly implement the reset signals.
422 Similar to @option{reset_halt}, but executes the script file defined to handle the
423 'reset' event for the target. Like @option{reset_halt} this only works with
424 correct reset implementations.
427 Simply let the target run after a reset.
430 Let the target run for some time (default: 1s), and then request halt.
433 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
434 to run for some time, then halted, and the @option{reset} event script is executed.
437 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
438 completely independent (like the LPC2000 series), or where the JTAG interface is
439 unavailable for some time during startup (like the STR7 series), you can't use
440 @option{reset_halt} or @option{reset_init}.
442 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
443 @cindex target_script
444 Event is either @var{reset} or @var{post_halt} or @var{pre_resume}.
445 TODO: describe exact semantic of events
446 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
447 @cindex run_and_halt_time
448 The amount of time the debugger should wait after releasing reset before it asserts
449 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
451 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
452 <@var{backup}|@var{nobackup}>
454 Specifies a working area for the debugger to use. This may be used to speed-up
455 downloads to target memory and flash operations, or to perform otherwise unavailable
456 operations (some coprocessor operations on ARM7/9 systems, for example). The last
457 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
458 a working_area that doesn't need to be backed up, as that slows down operation.
461 @subsection arm7tdmi options
462 @cindex arm7tdmi options
463 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
464 The arm7tdmi target definition requires at least one additional argument, specifying
465 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
466 The optional [@var{variant}] parameter has been removed in recent versions.
467 The correct feature set is determined at runtime.
469 @subsection arm720t options
470 @cindex arm720t options
471 ARM720t options are similar to ARM7TDMI options.
473 @subsection arm9tdmi options
474 @cindex arm9tdmi options
475 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
476 @option{arm920t}, @option{arm922t} and @option{arm940t}.
477 This enables the hardware single-stepping support found on these cores.
479 @subsection arm920t options
480 @cindex arm920t options
481 ARM920t options are similar to ARM9TDMI options.
483 @subsection arm966e options
484 @cindex arm966e options
485 ARM966e options are similar to ARM9TDMI options.
487 @subsection xscale options
488 @cindex xscale options
489 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
490 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
492 @section Flash configuration
493 @cindex Flash configuration
496 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
497 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
499 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
500 and <@var{bus_width}> bytes using the selected flash <driver>.
502 @item @b{flash autoerase} <@option{on}|@option{off}>
503 @cindex flash autoerase
504 auto erase flash banks prior to writing. Currently only works when using
505 @option{flash write_image} command. Default is @option{off}.
508 @subsection lpc2000 options
509 @cindex lpc2000 options
511 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
512 <@var{clock}> [@var{calc_checksum}]
513 LPC flashes don't require the chip and bus width to be specified. Additional
514 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
515 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
516 of the target this flash belongs to (first is 0), the frequency at which the core
517 is currently running (in kHz - must be an integral number), and the optional keyword
518 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
521 @subsection cfi options
524 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
526 CFI flashes require the number of the target they're connected to as an additional
527 argument. The CFI driver makes use of a working area (specified for the target)
528 to significantly speed up operation.
530 @subsection at91sam7 options
531 @cindex at91sam7 options
533 @b{flash bank at91sam7} 0 0 0 0 <@var{target#>}>
534 AT91SAM7 flashes only require the target#, all other values are looked up after
535 reading the chip-id and type.
537 @subsection str7 options
540 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
541 variant can be either STR71x, STR73x or STR75x.
543 @subsection str9 options
546 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
547 The str9 needs the flash controller to be configured prior to Flash programming, eg.
549 str9x flash_config 0 4 2 0 0x80000
551 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
553 @subsection str9 options (str9xpec driver)
555 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
556 Before using the flash commands the turbo mode will need enabling using str9xpec
557 @option{enable_turbo} <@var{num>.}
559 Only use this driver for locking/unlocking the device or configuring the option bytes.
560 Use the standard str9 driver for programming.
562 @subsection stellaris (LM3Sxxx) options
563 @cindex stellaris (LM3Sxxx) options
565 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
566 stellaris flash plugin only require the target#.
568 @subsection stm32x options
569 @cindex stm32x options
571 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
572 stm32x flash plugin only require the target#.
578 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
579 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
580 is available from both the telnet interface and a GDB session. To issue commands to the
581 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
582 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
588 @item @b{sleep} <@var{msec}>
590 Wait for n milliseconds before resuming. Useful in connection with script files
591 (@var{script} command and @var{target_script} configuration).
595 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
597 @item @b{debug_level} [@var{n}]
599 Display or adjust debug level to n<0-3>
601 @item @b{log_output} <@var{file}>
603 Redirect logging to <file> (default: stderr)
605 @item @b{script} <@var{file}>
607 Execute commands from <file>
611 @subsection Target state handling
613 @item @b{poll} [@option{on}|@option{off}]
615 Poll the target for its current state. If the target is in debug mode, architecture
616 specific information about the current state are printed. An optional parameter
617 allows continuous polling to be enabled and disabled.
621 Send a halt request to the target. The debugger signals the debug request,
622 and waits for the target to enter debug mode.
624 @item @b{resume} [@var{address}]
626 Resume the target at its current code position, or at an optional address.
628 @item @b{step} [@var{address}]
630 Single-step the target at its current code position, or at an optional address.
632 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
633 |@option{run_and_init}]
635 Do a hard-reset. The optional parameter specifies what should happen after the reset.
636 This optional parameter overwrites the setting specified in the configuration file,
637 making the new behaviour the default for the @option{reset} command.
644 Immediately halt the target (works only with certain configurations).
647 Immediately halt the target, and execute the reset script (works only with certain
650 @cindex reset run_and_halt
651 Let the target run for a certain amount of time, then request a halt.
653 @cindex reset run_and_init
654 Let the target run for a certain amount of time, then request a halt. Execute the
655 reset script once the target entered debug mode.
659 @subsection Memory access commands
660 These commands allow accesses of a specific size to the memory system:
662 @item @b{mdw} <@var{addr}> [@var{count}]
665 @item @b{mdh} <@var{addr}> [@var{count}]
667 display memory half-words
668 @item @b{mdb} <@var{addr}> [@var{count}]
671 @item @b{mww} <@var{addr}> <@var{value}>
674 @item @b{mwh} <@var{addr}> <@var{value}>
676 write memory half-word
677 @item @b{mwb} <@var{addr}> <@var{value}>
681 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
683 Load image <@var{file}> to target memory at <@var{address}>
684 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
686 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
687 (binary) <@var{file}>.
688 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
690 Verify <@var{file}> to target memory starting at <@var{address}>.
691 This will first attempt using a crc checksum, if this fails it will try a binary compare.
692 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
694 Load binary <@var{file}> to target memory at <@var{address}>
695 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
697 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
698 (binary) <@var{file}>.
701 @subsection Flash commands
702 @cindex Flash commands
704 @item @b{flash banks}
706 List configured flash banks
707 @item @b{flash info} <@var{num}>
709 Print info about flash bank <@option{num}>
710 @item @b{flash probe} <@var{num}>
712 Identify the flash, or validate the parameters of the configured flash. Operation
713 depends on the flash type.
714 @item @b{flash erase_check} <@var{num}>
715 @cindex flash erase_check
716 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
717 updates the erase state information displayed by @option{flash info}. That means you have
718 to issue an @option{erase_check} command after erasing or programming the device to get
720 @item @b{flash protect_check} <@var{num}>
721 @cindex flash protect_check
722 Check protection state of sectors in flash bank <num>.
724 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
726 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
727 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
728 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
729 the CFI driver). This command was replaced by the new command
730 @option{flash erase_sector} using the same syntax.
731 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
732 @cindex flash erase_sector
733 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
734 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
735 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
737 @item @b{flash erase_address} <@var{address}> <@var{length}>
738 @cindex flash erase_address
739 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
740 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
742 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
743 bytes from the beginning of the bank. This command was replaced by the new command
744 @option{flash write_binary} using the same syntax.
745 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
746 @cindex flash write_binary
747 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
748 <@option{offset}> bytes from the beginning of the bank.
749 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
750 @cindex flash write_image
751 Write the image <@var{file}> to the current target's flash bank(s). A relocation
752 [@var{offset}] can be specified and the file [@var{type}] can be specified
753 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
754 (ELF file) or @option{s19} (Motorola s19).
755 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
756 @cindex flash protect
757 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
758 <@var{last}> of @option{flash bank} <@var{num}>.
759 @item @b{flash auto_erase} <@var{on}|@var{off}>
760 @cindex flash auto_erase
761 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
762 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
766 @section Target Specific Commands
767 @cindex Target Specific Commands
769 @subsection AT91SAM7 specific commands
770 @cindex AT91SAM7 specific commands
771 The flash configuration is deduced from the chip identification register. The flash
772 controller handles erases automatically on a page (128/265 byte) basis so erase is
773 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
774 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
775 that can be erased separatly.Only an EraseAll command is supported by the controller
776 for each flash plane and this is called with
778 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
779 bulk erase flash planes first_plane to last_plane.
780 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
781 @cindex at91sam7 gpnvm
782 set or clear a gpnvm bit for the processor
785 @subsection STR9 specific commands
786 @cindex STR9 specific commands
787 These are flash specific commands when using the str9xpec driver.
789 @item @b{str9xpec enable_turbo} <@var{num}>
790 @cindex str9xpec enable_turbo
791 enable turbo mode, simply this will remove the str9 from the chain and talk
792 directly to the embedded flash controller.
793 @item @b{str9xpec disable_turbo} <@var{num}>
794 @cindex str9xpec disable_turbo
795 restore the str9 into jtag chain.
796 @item @b{str9xpec lock} <@var{num}>
797 @cindex str9xpec lock
798 lock str9 device. The str9 will only respond to an unlock command that will
800 @item @b{str9xpec unlock} <@var{num}>
801 @cindex str9xpec unlock
803 @item @b{str9xpec options_read} <@var{num}>
804 @cindex str9xpec options_read
805 read str9 option bytes.
806 @item @b{str9xpec options_write} <@var{num}>
807 @cindex str9xpec options_write
808 write str9 option bytes.
811 @subsection STR9 configuration
812 @cindex STR9 configuration
814 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
815 <@var{BBADR}> <@var{NBBADR}>
816 @cindex str9x flash_config
817 Configure str9 flash controller.
819 eg. str9x flash_config 0 4 2 0 0x80000
821 BBSR - Boot Bank Size register
822 NBBSR - Non Boot Bank Size register
823 BBADR - Boot Bank Start Address register
824 NBBADR - Boot Bank Start Address register
828 @subsection STR9 option byte configuration
829 @cindex STR9 option byte configuration
831 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
832 @cindex str9xpec options_cmap
833 configure str9 boot bank.
834 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
835 @cindex str9xpec options_lvdthd
836 configure str9 lvd threshold.
837 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
838 @cindex str9xpec options_lvdsel
839 configure str9 lvd source.
840 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
841 @cindex str9xpec options_lvdwarn
842 configure str9 lvd reset warning source.
845 @subsection STM32x specific commands
846 @cindex STM32x specific commands
848 These are flash specific commands when using the stm32x driver.
850 @item @b{stm32x lock} <@var{num}>
853 @item @b{stm32x unlock} <@var{num}>
854 @cindex stm32x unlock
856 @item @b{stm32x options_read} <@var{num}>
857 @cindex stm32x options_read
858 read stm32 option bytes.
859 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
860 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
861 @cindex stm32x options_write
862 write stm32 option bytes.
863 @item @b{stm32x mass_erase} <@var{num}>
864 @cindex stm32x mass_erase
865 mass erase flash memory.
869 @section Arcitecture Specific Commands
870 @cindex Arcitecture Specific Commands
872 @subsection ARMV4/5 specific commands
873 @cindex ARMV4/5 specific commands
875 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
876 or Intel XScale (XScale isn't supported yet).
878 @item @b{armv4_5 reg}
880 Display a list of all banked core registers, fetching the current value from every
881 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
883 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
884 @cindex armv4_5 core_mode
885 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
886 The target is resumed in the currently set @option{core_mode}.
889 @subsection ARM7/9 specific commands
890 @cindex ARM7/9 specific commands
892 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
893 ARM920t or ARM926EJ-S.
895 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
896 @cindex arm7_9 sw_bkpts
897 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
898 one of the watchpoint registers to implement software breakpoints. Disabling
899 SW Bkpts frees that register again.
900 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
901 @cindex arm7_9 force_hw_bkpts
902 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
903 breakpoints are turned into hardware breakpoints.
904 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
906 Enable use of the DBGRQ bit to force entry into debug mode. This should be
907 safe for all but ARM7TDMI--S cores (like Philips LPC).
908 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
909 @cindex arm7_9 fast_writes [DEPRECATED]
910 See @option{arm7_9 fast_memory_access} instead.
911 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
912 @cindex arm7_9 fast_memory_access
913 Allow the OpenOCD to read and write memory without checking completion of
914 the operation. This provides a huge speed increase, especially with USB JTAG
915 cables (FT2232), but might be unsafe if used with targets running at a very low
916 speed, like the 32kHz startup clock of an AT91RM9200.
917 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
918 @cindex arm7_9 dcc_downloads
919 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
920 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
921 unsafe, especially with targets running at a very low speed. This command was introduced
922 with OpenOCD rev. 60.
925 @subsection ARM920T specific commands
926 @cindex ARM920T specific commands
929 @item @b{arm920t cache_info}
930 @cindex arm920t cache_info
931 Print information about the caches found. This allows you to see if your target
932 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
933 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
934 @cindex arm920t md<bhw>_phys
935 Display memory at physical address addr.
936 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
937 @cindex arm920t mw<bhw>_phys
938 Write memory at physical address addr.
939 @item @b{arm920t read_cache} <@var{filename}>
940 @cindex arm920t read_cache
941 Dump the content of ICache and DCache to a file.
942 @item @b{arm920t read_mmu} <@var{filename}>
943 @cindex arm920t read_mmu
944 Dump the content of the ITLB and DTLB to a file.
945 @item @b{arm920t virt2phys} <@var{VA}>
946 @cindex arm920t virt2phys
947 Translate a virtual address to a physical address.
951 @section Debug commands
952 @cindex Debug commands
953 The following commands give direct access to the core, and are most likely
954 only useful while debugging the OpenOCD.
956 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
957 @cindex arm7_9 write_xpsr
958 Immediately write either the current program status register (CPSR) or the saved
959 program status register (SPSR), without changing the register cache (as displayed
960 by the @option{reg} and @option{armv4_5 reg} commands).
961 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
962 <@var{0=cpsr},@var{1=spsr}>
963 @cindex arm7_9 write_xpsr_im8
964 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
965 operation (similar to @option{write_xpsr}).
966 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
967 @cindex arm7_9 write_core_reg
968 Write a core register, without changing the register cache (as displayed by the
969 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
970 encoding of the [M4:M0] bits of the PSR.
974 @section JTAG commands
975 @cindex JTAG commands
979 Print current scan chain configuration.
982 Toggle reset lines <@var{trst}> <@var{srst}>.
983 @item @b{endstate} <@var{tap_state}>
985 Finish JTAG operations in <@var{tap_state}>.
986 @item @b{runtest} <@var{num_cycles}>
988 Move to Run-Test/Idle, and execute <@var{num_cycles}>
989 @item @b{statemove} [@var{tap_state}]
991 Move to current endstate or [@var{tap_state}]
994 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
997 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
998 @item @b{verify_ircapture}
999 @cindex verify_ircapture
1000 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1003 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1006 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1009 @node Sample Scripts
1010 @chapter Sample Scripts
1013 This page will collect some script examples for different CPUs.
1015 The configuration script can be divided in the following section:
1017 @item deamon configuration
1019 @item jtag scan chain
1020 @item target configuration
1021 @item flash configuration
1024 Detailed information about each section can be found at OpenOCD configuration
1026 @section OMAP5912 Flash Debug
1027 @cindex OMAP5912 Flash Debug
1028 The following two scripts was used with an wiggler PP and and a TI OMAP5912
1029 dual core processor (@uref{http://www.ti.com}) on a OMAP5912 OSK board
1030 (@uref{http://www.spectrumdigital.com}).
1031 @subsection Openocd config
1033 #daemon configuration
1040 parport_cable wiggler
1043 #use combined on interfaces or targets that can't set TRST/SRST separately
1044 reset_config trst_and_srst
1047 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1048 jtag_device 38 0x0 0x0 0x0
1049 jtag_device 4 0x1 0x0 0xe
1050 jtag_device 8 0x0 0x0 0x0
1052 #target configuration
1053 daemon_startup reset
1055 #target <type> <endianness> <reset mode> <chainpos> <variant>
1056 target arm926ejs little run_and_init 1 arm926ejs
1057 target_script 0 reset omap5912_osk.init
1058 run_and_halt_time 0 30
1060 # omap5912 lcd frame buffer as working area
1061 working_area 0 0x20000000 0x3e800 nobackup
1063 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1064 flash bank cfi 0x00000000 0x1000000 2 2 0
1067 @subsection Openocd init
1079 mww 0xfffec808 0x000000f5
1080 mww 0xfffec808 0x000000a0
1082 mww 0xfffeb048 0x0000aaaa
1084 mww 0xfffeb048 0x00005555
1093 @section STR71x Script
1094 @cindex STR71x Script
1095 The following script was used with an Amontec JTAGkey and a STR710 / STR711 cpu:
1097 #daemon configuration
1103 ft2232_device_desc "Amontec JTAGkey A"
1104 ft2232_layout jtagkey
1105 ft2232_vid_pid 0x0403 0xcff8
1108 #use combined on interfaces or targets that can't set TRST/SRST separately
1109 reset_config trst_and_srst srst_pulls_trst
1112 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1113 jtag_device 4 0x1 0xf 0xe
1115 #target configuration
1116 daemon_startup reset
1118 #target <type> <startup mode>
1119 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1120 target arm7tdmi little run_and_halt 0 arm7tdmi
1121 run_and_halt_time 0 30
1123 working_area 0 0x2000C000 0x4000 nobackup
1125 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1126 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1129 @section STR750 Script
1130 @cindex STR750 Script
1131 The following script was used with an Amontec JTAGkey and a STR750 cpu:
1133 #daemon configuration
1139 ft2232_device_desc "Amontec JTAGkey A"
1140 ft2232_layout jtagkey
1141 ft2232_vid_pid 0x0403 0xcff8
1144 #use combined on interfaces or targets that can't set TRST/SRST separately
1145 #reset_config trst_and_srst srst_pulls_trst
1146 reset_config trst_and_srst srst_pulls_trst
1149 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1150 jtag_device 4 0x1 0xf 0xe
1152 #jtag nTRST and nSRST delay
1153 jtag_nsrst_delay 500
1154 jtag_ntrst_delay 500
1156 #target configuration
1157 daemon_startup reset
1159 #target <type> <startup mode>
1160 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1161 target arm7tdmi little run_and_halt 0 arm7tdmi
1162 run_and_halt_time 0 30
1164 working_area 0 0x40000000 0x4000 nobackup
1166 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1167 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1170 @section STR912 Script
1171 @cindex STR912 Script
1172 The following script was used with an Amontec JTAGkey and a STR912 cpu:
1174 #daemon configuration
1180 ft2232_device_desc "Amontec JTAGkey A"
1181 ft2232_layout jtagkey
1184 #use combined on interfaces or targets that can't set TRST/SRST separately
1185 reset_config trst_and_srst
1188 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1189 jtag_device 8 0x1 0x1 0xfe
1190 jtag_device 4 0x1 0xf 0xe
1191 jtag_device 5 0x1 0x1 0x1e
1193 #target configuration
1194 daemon_startup reset
1196 #target <type> <startup mode>
1197 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1198 target arm966e little reset_halt 1 arm966e
1199 run_and_halt_time 0 30
1201 working_area 0 0x50000000 16384 nobackup
1203 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1204 flash bank str9x 0x00000000 0x00080000 0 0 0
1207 @section STR912 comstick
1208 @cindex STR912 comstick Script
1209 The following script was used with a Hitex STR9 Comstick:
1211 #daemon configuration
1217 ft2232_device_desc "STR9-comStick A"
1218 ft2232_layout comstick
1221 jtag_nsrst_delay 100
1222 jtag_ntrst_delay 100
1224 #use combined on interfaces or targets that can't set TRST/SRST separately
1225 reset_config trst_and_srst
1228 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1229 jtag_device 8 0x1 0x1 0xfe
1230 jtag_device 4 0x1 0xf 0xe
1231 jtag_device 5 0x1 0x1 0x1e
1233 #target configuration
1234 daemon_startup reset
1236 #target <type> <startup mode>
1237 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1238 target arm966e little reset_halt 1 arm966e
1239 run_and_halt_time 0 30
1241 working_area 0 0x50000000 16384 nobackup
1243 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1244 flash bank str9x 0x00000000 0x00080000 0 0 0
1247 @section STM32x Script
1248 @cindex STM32x Script
1249 The following script was used with an Amontec JTAGkey and a STM32x cpu:
1251 #daemon configuration
1257 ft2232_device_desc "Amontec JTAGkey A"
1258 ft2232_layout jtagkey
1261 jtag_nsrst_delay 100
1262 jtag_ntrst_delay 100
1264 #use combined on interfaces or targets that can't set TRST/SRST separately
1265 reset_config trst_and_srst
1268 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1269 jtag_device 4 0x1 0xf 0xe
1270 jtag_device 5 0x1 0x1 0x1e
1272 #target configuration
1273 daemon_startup reset
1275 #target <type> <startup mode>
1276 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1277 target cortex_m3 little run_and_halt 0
1278 run_and_halt_time 0 30
1280 working_area 0 0x20000000 16384 nobackup
1282 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1283 flash bank stm32x 0x08000000 0x00010000 0 0 0
1286 @section STM32x Performance Stick
1287 @cindex STM32x Performance Stick Script
1288 The following script was used with the Hitex STM32 Performance Stick
1290 #daemon configuration
1296 ft2232_device_desc "STM32-PerformanceStick A"
1297 ft2232_layout stm32stick
1300 jtag_nsrst_delay 100
1301 jtag_ntrst_delay 100
1303 #use combined on interfaces or targets that can't set TRST/SRST separately
1304 reset_config trst_and_srst
1307 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1308 jtag_device 4 0x1 0xf 0xe
1309 jtag_device 5 0x1 0x1 0x1e
1310 jtag_device 4 0x1 0xf 0xe
1312 #target configuration
1313 daemon_startup reset
1315 #target <type> <startup mode>
1316 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1317 target cortex_m3 little run_and_halt 0
1318 run_and_halt_time 0 30
1320 working_area 0 0x20000000 16384 nobackup
1322 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1323 flash bank stm32x 0x08000000 0x00010000 0 0 0
1326 @section LPC2129 Script
1327 @cindex LPC2129 Script
1328 The following script was used with an wiggler PP and a LPC-2129 cpu:
1330 #daemon configuration
1337 parport_cable wiggler
1340 #use combined on interfaces or targets that can't set TRST/SRST separately
1341 reset_config trst_and_srst srst_pulls_trst
1344 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1345 jtag_device 4 0x1 0xf 0xe
1347 #target configuration
1348 daemon_startup reset
1350 #target <type> <startup mode>
1351 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1352 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1353 run_and_halt_time 0 30
1355 working_area 0 0x40000000 0x4000 nobackup
1357 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1358 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1361 @section LPC2148 Script
1362 @cindex LPC2148 Script
1363 The following script was used with an Amontec JTAGkey and a LPC2148 cpu:
1365 #daemon configuration
1371 ft2232_device_desc "Amontec JTAGkey A"
1372 ft2232_layout jtagkey
1373 ft2232_vid_pid 0x0403 0xcff8
1376 #use combined on interfaces or targets that can't set TRST/SRST separately
1377 reset_config trst_and_srst srst_pulls_trst
1380 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1381 jtag_device 4 0x1 0xf 0xe
1383 #target configuration
1384 daemon_startup reset
1386 #target <type> <startup mode>
1387 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1388 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1389 run_and_halt_time 0 30
1391 working_area 0 0x40000000 0x8000 nobackup
1393 #flash configuration
1394 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1397 @section LPC2294 Script
1398 @cindex LPC2294 Script
1399 The following script was used with an Amontec JTAGkey and a LPC2294 cpu:
1401 #daemon configuration
1407 ft2232_device_desc "Amontec JTAGkey A"
1408 ft2232_layout jtagkey
1409 ft2232_vid_pid 0x0403 0xcff8
1412 #use combined on interfaces or targets that can't set TRST/SRST separately
1413 reset_config trst_and_srst srst_pulls_trst
1416 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1417 jtag_device 4 0x1 0xf 0xe
1419 #target configuration
1420 daemon_startup reset
1422 #target <type> <startup mode>
1423 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1424 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1425 run_and_halt_time 0 30
1427 working_area 0 0x40000000 0x4000 nobackup
1429 #flash configuration
1430 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1433 @section AT91R40008 Script
1434 @cindex AT91R40008 Script
1435 The following script was used with an Amontec JTAGkey and a AT91R40008 cpu:
1437 #daemon configuration
1443 ft2232_device_desc "Amontec JTAGkey A"
1444 ft2232_layout jtagkey
1445 ft2232_vid_pid 0x0403 0xcff8
1447 jtag_nsrst_delay 200
1448 jtag_ntrst_delay 200
1450 #use combined on interfaces or targets that can't set TRST/SRST separately
1451 reset_config srst_only srst_pulls_trst
1454 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1455 jtag_device 4 0x1 0xf 0xe
1457 #target configuration
1458 daemon_startup reset
1460 #target <type> <startup mode>
1461 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1462 target arm7tdmi little run_and_halt 0 arm7tdmi
1463 run_and_halt_time 0 30
1466 @section AT91SAM7s Script
1467 @cindex AT91SAM7s Script
1468 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 cpu:
1470 #daemon configuration
1476 ft2232_device_desc "Olimex OpenOCD JTAG A"
1477 ft2232_layout olimex-jtag
1478 ft2232_vid_pid 0x15BA 0x0003
1480 jtag_nsrst_delay 200
1481 jtag_ntrst_delay 200
1483 #use combined on interfaces or targets that can't set TRST/SRST separately
1484 reset_config srst_only srst_pulls_trst
1487 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1488 jtag_device 4 0x1 0xf 0xe
1490 #target configuration
1491 daemon_startup reset
1493 #target <type> <startup mode>
1494 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1495 target arm7tdmi little run_and_halt 0 arm7tdmi
1496 run_and_halt_time 0 30
1498 # flash-options AT91
1499 working_area 0 0x00200000 0x4000 nobackup
1500 flash bank at91sam7 0 0 0 0 0
1503 # erase command (telnet-interface) for complete flash:
1504 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1505 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1506 # set/clear NVM-Bits:
1507 # at91sam7 gpnvm <num> <bit> <set|clear>
1508 # disable locking from SAM-BA:
1509 # flash protect 0 0 1 off
1512 @section XSCALE IXP42x Script
1513 @cindex XSCALE IXP42x Script
1514 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x cpu:
1516 #daemon configuration
1522 ft2232_device_desc "Amontec JTAGkey A"
1523 ft2232_layout jtagkey
1524 ft2232_vid_pid 0x0403 0xcff8
1526 jtag_nsrst_delay 200
1527 jtag_ntrst_delay 200
1529 #use combined on interfaces or targets that can't set TRST/SRST separately
1530 reset_config srst_only srst_pulls_trst
1533 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1534 jtag_device 7 0x1 0x7f 0x7e
1536 #target configuration
1537 daemon_startup reset
1539 #target <type> <startup mode>
1540 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1541 target xscale big run_and_halt 0 IXP42x
1542 run_and_halt_time 0 30
1545 @section Cirrus Logic EP9301 Script
1546 @cindex Cirrus Logic EP9301 Script
1547 The following script was used with FT2232 based JTAG interfaces and a
1548 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1550 #daemon configuration
1558 #ft2232_device_desc "Olimex OpenOCD JTAG"
1559 #ft2232_layout olimex-jtag
1560 #ft2232_vid_pid 0x15ba 0x0003
1562 #Amontec JTAGkey (and JTAGkey-Tiny)
1563 #Serial is only necessary if more than one JTAGkey is connected
1564 ft2232_device_desc "Amontec JTAGkey A"
1565 #ft2232_serial AMTJKV31
1566 #ft2232_serial T1P3S2W8
1567 ft2232_layout jtagkey
1568 ft2232_vid_pid 0x0403 0xcff8
1570 #wiggler/parallel port interface
1573 #parport_cable wiggler
1576 reset_config trst_and_srst
1579 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1580 jtag_device 4 0x1 0xf 0xe
1582 jtag_nsrst_delay 100
1583 jtag_ntrst_delay 100
1585 #target configuration
1586 daemon_startup attach
1588 #target <type> <endianess> <reset mode>
1589 target arm920t little reset_halt 0
1590 working_area 0 0x80014000 0x1000 backup
1592 #flash configuration
1593 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1594 flash bank cfi 0x60000000 0x1000000 2 2 0
1597 @section Hilscher netX 100 / 500 Script
1598 @cindex Hilscher netX 100 / 500 Script
1599 The following script was used with an Amontec JTAGkey and a Hilscher
1602 #daemon configuration
1608 ft2232_device_desc "Amontec JTAGkey A"
1609 ft2232_layout jtagkey
1610 ft2232_vid_pid 0x0403 0xcff8
1613 #use combined on interfaces or targets that can't set TRST/SRST separately
1614 reset_config trst_and_srst
1617 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1618 jtag_device 4 0x1 0xf 0xe
1620 jtag_nsrst_delay 100
1621 jtag_ntrst_delay 100
1623 #target configuration
1624 daemon_startup reset
1626 #target <type> <endianness> <startup mode> <chainpos> <variant>
1627 target arm926ejs little run_and_halt 0 arm926ejs
1628 run_and_halt_time 0 500
1631 @section Marvell/Intel PXA270 Script
1632 @cindex Marvell/Intel PXA270 Script
1634 # config for Intel PXA270
1635 # not, as of 2007-06-22, openocd only works with the
1636 # libftd2xx library from ftdi. libftdi does not work.
1642 ft2232_layout olimex-jtag
1643 ft2232_vid_pid 0x15BA 0x0003
1644 ft2232_device_desc "Olimex OpenOCD JTAG"
1646 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1647 # the rest of the needed delays are built into the openocd program
1648 jtag_nsrst_delay 260
1649 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1650 # the rest of the needed delays are built into the openocd program
1653 #use combined on interfaces or targets that can't set TRST/SRST separately
1654 reset_config trst_and_srst separate
1657 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1658 jtag_device 7 0x1 0x7f 0x7e
1660 #target configuration
1661 daemon_startup reset
1663 target xscale little reset_halt 0 pxa27x
1665 # maps to PXA internal RAM. If you are using a PXA255
1666 # you must initialize SDRAM or leave this option off
1667 working_area 0 0x5c000000 0x10000 nobackup
1669 run_and_halt_time 0 30
1671 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1672 # works for P30 flash
1673 flash bank cfi 0x00000000 0x1000000 2 4 0
1680 @item OpenOCD complains about a missing cygwin1.dll
1682 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1683 claims to come with all the necessary dlls. When using Cygwin, try launching
1684 the OpenOCD from the Cygwin shell.
1686 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1687 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1688 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1690 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1691 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1692 software breakpoints consume one of the two available hardware breakpoints,
1693 and are therefor disabled by default. If your code is running from RAM, you
1694 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1695 your code resides in Flash, you can't use software breakpoints, but you can force
1696 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1698 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1699 and works sometimes fine.
1701 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1702 clock at the time you're programming the flash. If you've specified the crystal's
1703 frequency, make sure the PLL is disabled, if you've specified the full core speed
1704 (e.g. 60MHz), make sure the PLL is enabled.
1706 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1707 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1708 out while waiting for end of scan, rtck was disabled".
1710 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1711 settings in your PC Bios (ECP, EPP, and different versions of those).
1713 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1714 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1715 memory read caused data abort".
1717 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1718 beyond the last valid frame. It might be possible to prevent this by setting up
1719 a proper "initial" stack frame, if you happen to know what exactly has to
1720 be done, feel free to add this here.
1722 @item I get the following message in the OpenOCD console (or log file):
1723 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1725 This warning doesn't indicate any serious problem, as long as you don't want to
1726 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1727 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1728 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1729 independently. With this setup, it's not possible to halt the core right out of
1730 reset, everything else should work fine.
1732 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1733 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1734 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1735 quit with an error message. Is there a stability issue with OpenOCD?
1737 No, this is not a stability issue concering OpenOCD. Most users have solved
1738 this issue by simply using a self-powered USB Hub, which they connect their
1739 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1740 supply stable enough for the Amontec JTAGkey to be operated.
1742 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1743 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1744 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1745 What does that mean and what might be the reason for this?
1747 First of all, the reason might be the USB power supply. Try using a self-powered
1748 hub instead of a direct connection to your computer. Secondly, the error code 4
1749 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1750 Chip ran into some sort of error - this points us to a USB problem.
1752 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1753 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1754 What does that mean and what might be the reason for this?
1756 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1757 has closed the connection to OpenOCD. This might be a GDB issue.
1759 @item In the configuration file in the section where flash device configurations
1760 are described, there is a parameter for specifying the clock frequency for
1761 LPC2000 internal flash devices (e.g.
1762 @option{flash bank lpc2000 0x0 0x40000 0 0 lpc2000_v1 0 14746 calc_checksum}),
1763 which must be sepcified in kilohertz. However, I do have a quartz crystal of a
1764 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1765 Is it possible to specify real numbers for the clock frequency?
1767 No. The clock frequency specified here must be given as an integral number.
1768 However, this clock frequency is used by the In-Application-Programming (IAP)
1769 routines of the LPC2000 family only, which seems to be very tolerant concerning
1770 the given clock frequency, so a slight difference between the specified clock
1771 frequency and the actual clock frequency will not cause any trouble.
1773 @item Do I have to keep a specific order for the commands in the configuration file?
1775 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1776 listed for the JTAG scan chain must be given in the right order (jtag_device),
1777 with the device closest to the TDO-Pin being listed first. In general,
1778 whenever objects of the same type exist which require an index number, then
1779 these objects must be given in the right order (jtag_devices, targets and flash
1780 banks - a target references a jtag_device and a flash bank references a target).
1782 @item Sometimes my debugging session terminates with an error. When I look into the
1783 log file, I can see these error messages: Error: arm7_9_common.c:561
1784 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP