1 \input texinfo @c -*-texinfo-*-
3 @setfilename openocd.info
4 @settitle Open On-Chip Debugger (openocd)
5 @dircategory Development
7 * OpenOCD: (openocd). Open On-Chip Debugger.
14 Copyright @copyright{} 2007-2008 Spen @email{spen@@spen-soft.co.uk}
16 Permission is granted to copy, distribute and/or modify this document
17 under the terms of the GNU Free Documentation License, Version 1.2 or
18 any later version published by the Free Software Foundation; with no
19 Invariant Sections, with no Front-Cover Texts, and with no Back-Cover
20 Texts. A copy of the license is included in the section entitled ``GNU
21 Free Documentation License''.
26 @title Open On-Chip Debugger (openocd)
27 @subtitle Edition @value{EDITION} for openocd version @value{VERSION}
28 @subtitle @value{UPDATED}
30 @vskip 0pt plus 1filll
36 @node Top, About, , (dir)
39 This manual documents edition @value{EDITION} of the Open On-Chip Debugger
40 (openocd) version @value{VERSION}, @value{UPDATED}.
45 * About:: About Openocd.
46 * Developers:: Openocd developers
47 * Building:: Building Openocd
48 * Running:: Running Openocd
49 * Configuration:: Openocd Configuration.
50 * Commands:: Openocd Commands
51 * Sample Scripts:: Sample Target Scripts
52 * GDB and Openocd:: Using GDB and Openocd
53 * FAQ:: Frequently Asked Questions
54 * License:: GNU Free Documentation License
62 The Open On-Chip Debugger (openocd) aims to provide debugging, in-system programming
63 and boundary-scan testing for embedded target devices. The targets are interfaced
64 using JTAG (IEEE 1149.1) compliant hardware, but this may be extended to other
65 connection types in the future.
67 Openocd currently supports Wiggler (clones), FTDI FT2232 based JTAG interfaces, the
68 Amontec JTAG Accelerator, and the Gateworks GW1602. It allows ARM7 (ARM7TDMI and ARM720t),
69 ARM9 (ARM920t, ARM922t, ARM926ej--s, ARM966e--s), XScale (PXA25x, IXP42x) and
70 Cortex-M3 (Luminary Stellaris LM3 and ST STM32) based cores to be debugged.
72 Flash writing is supported for external CFI compatible flashes (Intel and AMD/Spansion
73 command set) and several internal flashes (LPC2000, AT91SAM7, STR7x, STR9x, LM3
74 and STM32x). Preliminary support for using the LPC3180's NAND flash controller is included.
80 Openocd has been created by Dominic Rath as part of a diploma thesis written at the
81 University of Applied Sciences Augsburg (@uref{http://www.fh-augsburg.de}).
82 Others interested in improving the state of free and open debug and testing technology
83 are welcome to participate.
85 Other developers have contributed support for additional targets and flashes as well
86 as numerous bugfixes and enhancements. See the AUTHORS file for regular contributors.
90 @cindex building openocd
92 You can download the current SVN version with SVN client of your choice from the
93 following repositories:
95 (@uref{svn://svn.berlios.de/openocd/trunk})
99 (@uref{http://svn.berlios.de/svnroot/repos/openocd/trunk})
101 Using the SVN command line client, you could use the following command to fetch the
102 latest version (make sure there is no (non-svn) directory called "openocd" in the
106 svn checkout svn://svn.berlios.de/openocd/trunk openocd
109 Building the OpenOCD requires a recent version of the GNU autotools.
110 On my build system, I'm using autoconf 2.13 and automake 1.9. For building on Windows,
111 you have to use Cygwin. Make sure that your @env{PATH} environment variable contains no
112 other locations with Unix utils (like UnxUtils) - these can't handle the Cygwin
113 paths, resulting in obscure dependency errors (This is an observation I've gathered
114 from the logs of one user - correct me if I'm wrong).
116 You further need the appropriate driver files, if you want to build support for
117 a FTDI FT2232 based interface:
119 @item @b{ftdi2232} libftdi (@uref{http://www.intra2net.com/opensource/ftdi/})
120 @item @b{ftd2xx} libftd2xx (@uref{http://www.ftdichip.com/Drivers/D2XX.htm})
121 @item When using the Amontec JTAGkey, you have to get the drivers from the Amontec
122 homepage (@uref{www.amontec.com}), as the JTAGkey uses a non-standard VID/PID.
125 Please note that the ftdi2232 variant (using libftdi) isn't supported under Cygwin.
126 You have to use the ftd2xx variant (using FTDI's D2XX) on Cygwin.
128 In general, the D2XX driver provides superior performance (several times as fast),
129 but has the draw-back of being binary-only - though that isn't as worse, as it isn't
130 a kernel module, only a user space library.
132 To build OpenOCD (on both Linux and Cygwin), use the following commands:
136 Bootstrap generates the configure script, and prepares building on your system.
140 Configure generates the Makefiles used to build OpenOCD.
144 Make builds the OpenOCD, and places the final executable in ./src/.
146 The configure script takes several options, specifying which JTAG interfaces
151 @option{--enable-parport}
153 @option{--enable-parport_ppdev}
155 @option{--enable-amtjtagaccel}
157 @option{--enable-ft2232_ftd2xx}
158 @footnote{Using the latest D2XX drivers from FTDI and following their installation
159 instructions, I had to use @option{--enable-ft2232_libftd2xx} for the OpenOCD to
162 @option{--enable-ft2232_libftdi}
164 @option{--with-ftd2xx=/path/to/d2xx/}
167 If you want to access the parallel port using the PPDEV interface you have to specify
168 both the @option{--enable-parport} AND the @option{--enable-parport_ppdev} option since
169 the @option{--enable-parport_ppdev} option actually is an option to the parport driver
170 (see @uref{http://forum.sparkfun.com/viewtopic.php?t=3795} for more info).
172 Cygwin users have to specify the location of the FTDI D2XX package. This should be an
173 absolute path containing no spaces.
175 Linux users should copy the various parts of the D2XX package to the appropriate
176 locations, i.e. /usr/include, /usr/lib.
180 @cindex running openocd
182 @cindex --debug_level
185 The OpenOCD runs as a daemon, waiting for connections from clients (Telnet or GDB).
186 Run with @option{--help} or @option{-h} to view the available command line arguments.
188 It reads its configuration by default from the file openocd.cfg located in the current
189 working directory. This may be overwritten with the @option{-f <configfile>} command line
192 To enable debug output (when reporting problems or working on OpenOCD itself), use
193 the @option{-d} command line switch. This sets the debug_level to "3", outputting
194 the most information, including debug messages. The default setting is "2", outputting
195 only informational messages, warnings and errors. You can also change this setting
196 from within a telnet or gdb session (@option{debug_level <n>}).
198 You can redirect all output from the daemon to a file using the @option{-l <logfile>} switch.
200 Search paths for config/script files can be added to openocd by using
201 the @option{-s <search>} switch.
204 @chapter Configuration
205 @cindex configuration
206 The Open On-Chip Debugger (OpenOCD) runs as a daemon, and reads it current configuration
207 by default from the file openocd.cfg in the current directory. A different configuration
208 file can be specified with the @option{-f <conf.file>} given at the openocd command line.
210 The configuration file is used to specify on which ports the daemon listens for new
211 connections, the JTAG interface used to connect to the target, the layout of the JTAG
212 chain, the targets that should be debugged, and connected flashes.
214 @section Daemon configuration
217 @item @b{telnet_port} <@var{number}>
219 Port on which to listen for incoming telnet connections
220 @item @b{gdb_port} <@var{number}>
222 First port on which to listen for incoming GDB connections. The GDB port for the
223 first target will be gdb_port, the second target will listen on gdb_port + 1, and so on.
224 @item @b{gdb_detach} <@var{resume|reset|halt|nothing}>
226 Configures what openocd will do when gdb detaches from the daeman.
227 Default behaviour is <@var{resume}>
228 @item @b{gdb_memory_map} <@var{enable|disable}>
229 @cindex gdb_memory_map
230 Set to <@var{enable}> so that openocd will send the memory configuration to gdb when
231 requested. gdb will then know when to set hardware breakpoints, and program flash
232 using the gdb load command. @option{gdb_flash_program enable} will also need enabling
233 for flash programming to work.
234 Default behaviour is <@var{disable}>
235 @item @b{gdb_flash_program} <@var{enable|disable}>
236 @cindex gdb_flash_program
237 Set to <@var{enable}> so that openocd will program the flash memory when a
238 vFlash packet is received.
239 Default behaviour is <@var{disable}>
240 @item @b{daemon_startup} <@var{mode}> either @samp{attach} or @samp{reset}
241 @cindex daemon_startup
242 Tells the OpenOCD whether it should reset the target when the daemon is launched, or
243 if it should just attach to the target.
246 @section JTAG interface configuration
249 @item @b{interface} <@var{name}>
251 Use the interface driver <@var{name}> to connect to the target. Currently supported
255 PC parallel port bit-banging (Wigglers, PLD download cable, ...)
259 Amontec Chameleon in its JTAG Accelerator configuration connected to a PC's EPP
264 FTDI FT2232 based devices using either the open-source libftdi or the binary only
265 FTD2XX driver. The FTD2XX is superior in performance, but not available on every
266 platform. The libftdi uses libusb, and should be portable to all systems that provide
271 Cirrus Logic EP93xx based single-board computer bit-banging (in development)
276 @item @b{jtag_speed} <@var{number}>
278 Limit the maximum speed of the JTAG interface. Usually, a value of zero means maximum
279 speed. The actual effect of this option depends on the JTAG interface used.
282 @item wiggler: maximum speed / @var{number}
283 @item ft2232: 6MHz / (@var{number}+1)
284 @item amt jtagaccel: 8 / 2**@var{number}
287 Note: Make sure the jtag clock is no more than @math{1/6th × CPU-Clock}. This is
288 especially true for synthesized cores (-S).
290 @item @b{reset_config} <@var{signals}> [@var{combination}] [@var{trst_type}] [@var{srst_type}]
292 The configuration of the reset signals available on the JTAG interface AND the target.
293 If the JTAG interface provides SRST, but the target doesn't connect that signal properly,
294 then OpenOCD can't use it. <@var{signals}> can be @samp{none}, @samp{trst_only},
295 @samp{srst_only} or @samp{trst_and_srst}.
296 [@var{combination}] is an optional value specifying broken reset signal implementations.
297 @samp{srst_pulls_trst} states that the testlogic is reset together with the reset of
298 the system (e.g. Philips LPC2000, "broken" board layout), @samp{trst_pulls_srst} says
299 that the system is reset together with the test logic (only hypothetical, I haven't
300 seen hardware with such a bug, and can be worked around).
302 The [@var{trst_type}] and [@var{srst_type}] parameters allow the driver type of the
303 reset lines to be specified. Possible values are @samp{trst_push_pull} (default)
304 and @samp{trst_open_drain} for the test reset signal, and @samp{srst_open_drain}
305 (default) and @samp{srst_push_pull} for the system reset. These values only affect
306 JTAG interfaces with support for different drivers, like the Amontec JTAGkey and JTAGAccelerator.
308 @item @b{jtag_device} <@var{IR length}> <@var{IR capture}> <@var{IR mask}> <@var{IDCODE instruction}>
310 Describes the devices that form the JTAG daisy chain, with the first device being
311 the one closest to TDO. The parameters are the length of the instruction register
312 (4 for all ARM7/9s), the value captured during Capture-IR (0x1 for ARM7/9), and a mask
313 of bits that should be validated when doing IR scans (all four bits (0xf) for ARM7/9).
314 The IDCODE instruction will in future be used to query devices for their JTAG
315 identification code. This line is the same for all ARM7 and ARM9 devices.
316 Other devices, like CPLDs, require different parameters. An example configuration
317 line for a Xilinx XC9500 CPLD would look like this:
319 jtag_device 8 0x01 0x0e3 0xfe
321 The instruction register (IR) is 8 bits long, during Capture-IR 0x01 is loaded into
322 the IR, but only bits 0-1 and 5-7 should be checked, the others (2-4) might vary.
323 The IDCODE instruction is 0xfe.
325 @item @b{jtag_nsrst_delay} <@var{ms}>
326 @cindex jtag_nsrst_delay
327 How long (in miliseconds) the OpenOCD should wait after deasserting nSRST before
328 starting new JTAG operations.
329 @item @b{jtag_ntrst_delay} <@var{ms}>
330 @cindex jtag_ntrst_delay
331 How long (in miliseconds) the OpenOCD should wait after deasserting nTRST before
332 starting new JTAG operations.
334 The jtag_n[st]rst_delay options are useful if reset circuitry (like a reset supervisor,
335 or on-chip features) keep a reset line asserted for some time after the external reset
339 @section parport options
342 @item @b{parport_port} <@var{number}>
344 Either the address of the I/O port (default: 0x378 for LPT1) or the number of
345 the @file{/dev/parport} device
347 When using PPDEV to access the parallel port, use the number of the parallel port:
348 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
349 you may encounter a problem.
350 @item @b{parport_cable} <@var{name}>
351 @cindex parport_cable
352 The layout of the parallel port cable used to connect to the target.
353 Currently supported cables are
357 Original Wiggler layout, also supported by several clones, such
358 as the Olimex ARM-JTAG
359 @item old_amt_wiggler
360 @cindex old_amt_wiggler
361 The Wiggler configuration that comes with Amontec's Chameleon Programmer. The new
362 version available from the website uses the original Wiggler layout ('@var{wiggler}')
365 Describes the connection of the Amontec Chameleon's CPLD when operated in
366 configuration mode. This is only used to program the Chameleon itself, not
370 Xilinx Parallel cable III.
373 The parallel port adapter found on the 'Karo Triton 1 Development Board'.
374 This is also the layout used by the HollyGates design
375 (see @uref{http://www.lartmaker.nl/projects/jtag/}).
380 @item @b{parport_write_on_exit} <@var{on|off}>
381 @cindex parport_write_on_exit
382 This will configure the parallel driver to write a known value to the parallel
383 interface on exiting openocd
386 @section amt_jtagaccel options
388 @item @b{parport_port} <@var{number}>
390 Either the address of the I/O port (default: 0x378 for LPT1) or the number of the
391 @file{/dev/parport} device
393 @section ft2232 options
396 @item @b{ft2232_device_desc} <@var{description}>
397 @cindex ft2232_device_desc
398 The USB device description of the FTDI FT2232 device. If not specified, the FTDI
399 default value is used. This setting is only valid if compiled with FTD2XX support.
400 @item @b{ft2232_layout} <@var{name}>
401 @cindex ft2232_layout
402 The layout of the FT2232 GPIO signals used to control output-enables and reset
403 signals. Valid layouts are
406 The "USBJTAG-1" layout described in the original OpenOCD diploma thesis
408 Amontec JTAGkey and JTAGkey-tiny
414 American Microsystems M5960
416 Luminary Micro EVB_LM3S811 as a JTAG interface (not onboard processor), no TRST or
417 SRST signals on external connector
421 Hitex STM32 Performance Stick
423 Tin Can Tools Flyswatter
425 egnite Software turtelizer2
430 @item @b{ft2232_vid_pid} <@var{vid}> <@var{pid}>
431 The vendor ID and product ID of the FTDI FT2232 device. If not specified, the FTDI
432 default values are used. This command is not available on Windows.
433 @item @b{ft2232_latency} <@var{ms}>
434 On some systems using ft2232 based JTAG interfaces the FT_Read function call in
435 ft2232_read() fails to return the expected number of bytes. This can be caused by
436 USB communication delays and has proved hard to reproduce and debug. Setting the
437 FT2232 latency timer to a larger value increases delays for short USB packages but it
438 also reduces the risk of timeouts before receiving the expected number of bytes.
439 The OpenOCD default value is 2 and for some systems a value of 10 has proved useful.
442 @section ep93xx options
443 @cindex ep93xx options
444 Currently, there are no options available for the ep93xx interface.
447 @section Target configuration
450 @item @b{target} <@var{type}> <@var{endianess}> <@var{reset_mode}> <@var{JTAG pos}>
453 Defines a target that should be debugged. Currently supported types are:
467 If you want to use a target board that is not on this list, see Adding a new
470 Endianess may be @option{little} or @option{big}.
472 The reset_mode specifies what should happen to the target when a reset occurs:
476 Immediately request a target halt after reset. This allows targets to be debugged
477 from the very first instruction. This is only possible with targets and JTAG
478 interfaces that correctly implement the reset signals.
481 Similar to @option{reset_halt}, but executes the script file defined to handle the
482 'reset' event for the target. Like @option{reset_halt} this only works with
483 correct reset implementations.
486 Simply let the target run after a reset.
489 Let the target run for some time (default: 1s), and then request halt.
492 A combination of @option{reset_init} and @option{run_and_halt}. The target is allowed
493 to run for some time, then halted, and the @option{reset} event script is executed.
496 On JTAG interfaces / targets where system reset and test-logic reset can't be driven
497 completely independent (like the LPC2000 series), or where the JTAG interface is
498 unavailable for some time during startup (like the STR7 series), you can't use
499 @option{reset_halt} or @option{reset_init}.
501 @item @b{target_script} <@var{target#}> <@var{event}> <@var{script_file}>
502 @cindex target_script
503 Event is either @option{reset}, @option{post_halt}, @option{pre_resume} or @option{gdb_program_config}
505 TODO: describe exact semantic of events
506 @item @b{run_and_halt_time} <@var{target#}> <@var{time_in_ms}>
507 @cindex run_and_halt_time
508 The amount of time the debugger should wait after releasing reset before it asserts
509 a debug request. This is used by the @option{run_and_halt} and @option{run_and_init}
511 @item @b{working_area} <@var{target#}> <@var{address}> <@var{size}>
512 <@var{backup}|@var{nobackup}>
514 Specifies a working area for the debugger to use. This may be used to speed-up
515 downloads to target memory and flash operations, or to perform otherwise unavailable
516 operations (some coprocessor operations on ARM7/9 systems, for example). The last
517 parameter decides whether the memory should be preserved <@var{backup}>. If possible, use
518 a working_area that doesn't need to be backed up, as that slows down operation.
521 @subsection arm7tdmi options
522 @cindex arm7tdmi options
523 target arm7tdmi <@var{endianess}> <@var{reset_mode}> <@var{jtag#}>
524 The arm7tdmi target definition requires at least one additional argument, specifying
525 the position of the target in the JTAG daisy-chain. The first JTAG device is number 0.
526 The optional [@var{variant}] parameter has been removed in recent versions.
527 The correct feature set is determined at runtime.
529 @subsection arm720t options
530 @cindex arm720t options
531 ARM720t options are similar to ARM7TDMI options.
533 @subsection arm9tdmi options
534 @cindex arm9tdmi options
535 ARM9TDMI options are similar to ARM7TDMI options. Supported variants are
536 @option{arm920t}, @option{arm922t} and @option{arm940t}.
537 This enables the hardware single-stepping support found on these cores.
539 @subsection arm920t options
540 @cindex arm920t options
541 ARM920t options are similar to ARM9TDMI options.
543 @subsection arm966e options
544 @cindex arm966e options
545 ARM966e options are similar to ARM9TDMI options.
547 @subsection xscale options
548 @cindex xscale options
549 Supported variants are @option{ixp42x}, @option{ixp45x}, @option{ixp46x},
550 @option{pxa250}, @option{pxa255}, @option{pxa26x}.
552 @section Flash configuration
553 @cindex Flash configuration
556 @item @b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
557 <@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
559 Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
560 and <@var{bus_width}> bytes using the selected flash <driver>.
562 @item @b{flash auto_erase} <@option{on}|@option{off}>
563 @cindex flash auto_erase
564 auto erase flash banks prior to writing. Currently only works when using
565 @option{flash write_image} command. Default is @option{off}.
568 @subsection lpc2000 options
569 @cindex lpc2000 options
571 @b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
572 <@var{clock}> [@var{calc_checksum}]
573 LPC flashes don't require the chip and bus width to be specified. Additional
574 parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
575 or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
576 of the target this flash belongs to (first is 0), the frequency at which the core
577 is currently running (in kHz - must be an integral number), and the optional keyword
578 @var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
581 @subsection cfi options
584 @b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
586 CFI flashes require the number of the target they're connected to as an additional
587 argument. The CFI driver makes use of a working area (specified for the target)
588 to significantly speed up operation.
590 @var{chip_width} and @var{bus_width} are specified in bytes.
592 @subsection at91sam7 options
593 @cindex at91sam7 options
595 @b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
596 AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
597 reading the chip-id and type.
599 @subsection str7 options
602 @b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
603 variant can be either STR71x, STR73x or STR75x.
605 @subsection str9 options
608 @b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
609 The str9 needs the flash controller to be configured prior to Flash programming, eg.
611 str9x flash_config 0 4 2 0 0x80000
613 This will setup the BBSR, NBBSR, BBADR and NBBADR registers respectively.
615 @subsection str9 options (str9xpec driver)
617 @b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
618 Before using the flash commands the turbo mode will need enabling using str9xpec
619 @option{enable_turbo} <@var{num>.}
621 Only use this driver for locking/unlocking the device or configuring the option bytes.
622 Use the standard str9 driver for programming.
624 @subsection stellaris (LM3Sxxx) options
625 @cindex stellaris (LM3Sxxx) options
627 @b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
628 stellaris flash plugin only require the @var{target#}.
630 @subsection stm32x options
631 @cindex stm32x options
633 @b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
634 stm32x flash plugin only require the @var{target#}.
640 The Open On-Chip Debugger (OpenOCD) allows user interaction through a telnet interface
641 (default: port 4444) and a GDB server (default: port 3333). The command line interpreter
642 is available from both the telnet interface and a GDB session. To issue commands to the
643 interpreter from within a GDB session, use the @option{monitor} command, e.g. use
644 @option{monitor poll} to issue the @option{poll} command. All output is relayed through the
650 @item @b{sleep} <@var{msec}>
652 Wait for n milliseconds before resuming. Useful in connection with script files
653 (@var{script} command and @var{target_script} configuration).
657 Close the OpenOCD daemon, disconnecting all clients (GDB, Telnet).
659 @item @b{debug_level} [@var{n}]
661 Display or adjust debug level to n<0-3>
663 @item @b{log_output} <@var{file}>
665 Redirect logging to <file> (default: stderr)
667 @item @b{script} <@var{file}>
669 Execute commands from <file>
673 @subsection Target state handling
675 @item @b{poll} [@option{on}|@option{off}]
677 Poll the target for its current state. If the target is in debug mode, architecture
678 specific information about the current state are printed. An optional parameter
679 allows continuous polling to be enabled and disabled.
681 @item @b{halt} [@option{ms}]
683 Send a halt request to the target and waits for it to halt for [@option{ms}].
684 Default [@option{ms}] is 5 seconds if no arg given.
685 Optional arg @option{ms} is a timeout in milliseconds. Using 0 as the [@option{ms}]
686 will stop openocd from waiting.
688 @item @b{wait_halt} [@option{ms}]
690 Wait for the target to enter debug mode. Optional [@option{ms}] is
691 a timeout in milliseconds. Default [@option{ms}] is 5 seconds if no
694 @item @b{resume} [@var{address}]
696 Resume the target at its current code position, or at an optional address.
697 Openocd will wait 5 seconds for the target to resume.
699 @item @b{step} [@var{address}]
701 Single-step the target at its current code position, or at an optional address.
703 @item @b{reset} [@option{run}|@option{halt}|@option{init}|@option{run_and_halt}
704 |@option{run_and_init}]
706 Do a hard-reset. The optional parameter specifies what should happen after the reset.
707 This optional parameter overwrites the setting specified in the configuration file,
708 making the new behaviour the default for the @option{reset} command.
715 Immediately halt the target (works only with certain configurations).
718 Immediately halt the target, and execute the reset script (works only with certain
721 @cindex reset run_and_halt
722 Let the target run for a certain amount of time, then request a halt.
724 @cindex reset run_and_init
725 Let the target run for a certain amount of time, then request a halt. Execute the
726 reset script once the target entered debug mode.
730 @subsection Memory access commands
731 These commands allow accesses of a specific size to the memory system:
733 @item @b{mdw} <@var{addr}> [@var{count}]
736 @item @b{mdh} <@var{addr}> [@var{count}]
738 display memory half-words
739 @item @b{mdb} <@var{addr}> [@var{count}]
742 @item @b{mww} <@var{addr}> <@var{value}>
745 @item @b{mwh} <@var{addr}> <@var{value}>
747 write memory half-word
748 @item @b{mwb} <@var{addr}> <@var{value}>
752 @item @b{load_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
754 Load image <@var{file}> to target memory at <@var{address}>
755 @item @b{dump_image} <@var{file}> <@var{address}> <@var{size}>
757 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
758 (binary) <@var{file}>.
759 @item @b{verify_image} <@var{file}> <@var{address}> [@option{bin}|@option{ihex}|@option{elf}]
761 Verify <@var{file}> to target memory starting at <@var{address}>.
762 This will first attempt using a crc checksum, if this fails it will try a binary compare.
763 @item @b{load_binary} <@var{file}> <@var{address}> [DEPRECATED]
765 Load binary <@var{file}> to target memory at <@var{address}>
766 @item @b{dump_binary} <@var{file}> <@var{address}> <@var{size}> [DEPRECATED]
768 Dump <@var{size}> bytes of target memory starting at <@var{address}> to a
769 (binary) <@var{file}>.
772 @subsection Flash commands
773 @cindex Flash commands
775 @item @b{flash banks}
777 List configured flash banks
778 @item @b{flash info} <@var{num}>
780 Print info about flash bank <@option{num}>
781 @item @b{flash probe} <@var{num}>
783 Identify the flash, or validate the parameters of the configured flash. Operation
784 depends on the flash type.
785 @item @b{flash erase_check} <@var{num}>
786 @cindex flash erase_check
787 Check erase state of sectors in flash bank <@var{num}>. This is the only operation that
788 updates the erase state information displayed by @option{flash info}. That means you have
789 to issue an @option{erase_check} command after erasing or programming the device to get
791 @item @b{flash protect_check} <@var{num}>
792 @cindex flash protect_check
793 Check protection state of sectors in flash bank <num>.
795 @item @b{flash erase} <@var{num}> <@var{first}> <@var{last}> [DEPRECATED]
797 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
798 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
799 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
800 the CFI driver). This command was replaced by the new command
801 @option{flash erase_sector} using the same syntax.
802 @item @b{flash erase_sector} <@var{num}> <@var{first}> <@var{last}>
803 @cindex flash erase_sector
804 Erase sectors at bank <@var{num}>, starting at sector <@var{first}> up to and including
805 <@var{last}>. Sector numbering starts at 0. Depending on the flash type, erasing might
806 require the protection to be disabled first (e.g. Intel Advanced Bootblock flash using
808 @item @b{flash erase_address} <@var{address}> <@var{length}>
809 @cindex flash erase_address
810 Erase sectors starting at <@var{address}> for <@var{length}> number of bytes
811 @item @b{flash write} <@var{num}> <@var{file}> <@var{offset}> [DEPRECATED]
813 Write the binary <@var{file}> to flash bank <@var{num}>, starting at <@var{offset}>
814 bytes from the beginning of the bank. This command was replaced by the new command
815 @option{flash write_binary} using the same syntax.
816 @item @b{flash write_binary} <@var{num}> <@var{file}> <@var{offset}>
817 @cindex flash write_binary
818 Write the binary <@var{file}> to flash bank <@var{num}>, starting at
819 <@option{offset}> bytes from the beginning of the bank.
820 @item @b{flash write_image} <@var{file}> [@var{offset}] [@var{type}]
821 @cindex flash write_image
822 Write the image <@var{file}> to the current target's flash bank(s). A relocation
823 [@var{offset}] can be specified and the file [@var{type}] can be specified
824 explicitly as @option{bin} (binary), @option{ihex} (Intel hex), @option{elf}
825 (ELF file) or @option{s19} (Motorola s19).
826 @item @b{flash protect} <@var{num}> <@var{first}> <@var{last}> <@option{on}|@option{off}>
827 @cindex flash protect
828 Enable (@var{on}) or disable (@var{off}) protection of flash sectors <@var{first}> to
829 <@var{last}> of @option{flash bank} <@var{num}>.
830 @item @b{flash auto_erase} <@var{on}|@var{off}>
831 @cindex flash auto_erase
832 Enable (@option{on}) to erase flash banks prior to writing using the flash @option{write_image} command
833 only. Default is (@option{off}), flash banks have to be erased using @option{flash erase} command.
837 @section Target Specific Commands
838 @cindex Target Specific Commands
840 @subsection AT91SAM7 specific commands
841 @cindex AT91SAM7 specific commands
842 The flash configuration is deduced from the chip identification register. The flash
843 controller handles erases automatically on a page (128/265 byte) basis so erase is
844 not necessary for flash programming. AT91SAM7 processors with less than 512K flash
845 only have a single flash bank embedded on chip. AT91SAM7xx512 have two flash planes
846 that can be erased separatly.Only an EraseAll command is supported by the controller
847 for each flash plane and this is called with
849 @item @b{flash erase} <@var{num}> @var{first_plane} @var{last_plane}
850 bulk erase flash planes first_plane to last_plane.
851 @item @b{at91sam7 gpnvm} <@var{num}> <@var{bit}> <@option{set}|@option{clear}>
852 @cindex at91sam7 gpnvm
853 set or clear a gpnvm bit for the processor
856 @subsection STR9 specific commands
857 @cindex STR9 specific commands
858 These are flash specific commands when using the str9xpec driver.
860 @item @b{str9xpec enable_turbo} <@var{num}>
861 @cindex str9xpec enable_turbo
862 enable turbo mode, simply this will remove the str9 from the chain and talk
863 directly to the embedded flash controller.
864 @item @b{str9xpec disable_turbo} <@var{num}>
865 @cindex str9xpec disable_turbo
866 restore the str9 into jtag chain.
867 @item @b{str9xpec lock} <@var{num}>
868 @cindex str9xpec lock
869 lock str9 device. The str9 will only respond to an unlock command that will
871 @item @b{str9xpec unlock} <@var{num}>
872 @cindex str9xpec unlock
874 @item @b{str9xpec options_read} <@var{num}>
875 @cindex str9xpec options_read
876 read str9 option bytes.
877 @item @b{str9xpec options_write} <@var{num}>
878 @cindex str9xpec options_write
879 write str9 option bytes.
882 @subsection STR9 configuration
883 @cindex STR9 configuration
885 @item @b{str9x flash_config} <@var{bank}> <@var{BBSR}> <@var{NBBSR}>
886 <@var{BBADR}> <@var{NBBADR}>
887 @cindex str9x flash_config
888 Configure str9 flash controller.
890 eg. str9x flash_config 0 4 2 0 0x80000
892 BBSR - Boot Bank Size register
893 NBBSR - Non Boot Bank Size register
894 BBADR - Boot Bank Start Address register
895 NBBADR - Boot Bank Start Address register
899 @subsection STR9 option byte configuration
900 @cindex STR9 option byte configuration
902 @item @b{str9xpec options_cmap} <@var{num}> <@option{bank0}|@option{bank1}>
903 @cindex str9xpec options_cmap
904 configure str9 boot bank.
905 @item @b{str9xpec options_lvdthd} <@var{num}> <@option{2.4v}|@option{2.7v}>
906 @cindex str9xpec options_lvdthd
907 configure str9 lvd threshold.
908 @item @b{str9xpec options_lvdsel} <@var{num}> <@option{vdd}|@option{vdd_vddq}>
909 @cindex str9xpec options_lvdsel
910 configure str9 lvd source.
911 @item @b{str9xpec options_lvdwarn} <@var{bank}> <@option{vdd}|@option{vdd_vddq}>
912 @cindex str9xpec options_lvdwarn
913 configure str9 lvd reset warning source.
916 @subsection STM32x specific commands
917 @cindex STM32x specific commands
919 These are flash specific commands when using the stm32x driver.
921 @item @b{stm32x lock} <@var{num}>
924 @item @b{stm32x unlock} <@var{num}>
925 @cindex stm32x unlock
927 @item @b{stm32x options_read} <@var{num}>
928 @cindex stm32x options_read
929 read stm32 option bytes.
930 @item @b{stm32x options_write} <@var{num}> <@option{SWWDG}|@option{HWWDG}>
931 <@option{RSTSTNDBY}|@option{NORSTSTNDBY}> <@option{RSTSTOP}|@option{NORSTSTOP}>
932 @cindex stm32x options_write
933 write stm32 option bytes.
934 @item @b{stm32x mass_erase} <@var{num}>
935 @cindex stm32x mass_erase
936 mass erase flash memory.
940 @section Architecture Specific Commands
941 @cindex Architecture Specific Commands
943 @subsection ARMV4/5 specific commands
944 @cindex ARMV4/5 specific commands
946 These commands are specific to ARM architecture v4 and v5, like all ARM7/9 systems
947 or Intel XScale (XScale isn't supported yet).
949 @item @b{armv4_5 reg}
951 Display a list of all banked core registers, fetching the current value from every
952 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
954 @item @b{armv4_5 core_mode} [@option{arm}|@option{thumb}]
955 @cindex armv4_5 core_mode
956 Displays the core_mode, optionally changing it to either ARM or Thumb mode.
957 The target is resumed in the currently set @option{core_mode}.
960 @subsection ARM7/9 specific commands
961 @cindex ARM7/9 specific commands
963 These commands are specific to ARM7 and ARM9 targets, like ARM7TDMI, ARM720t,
964 ARM920t or ARM926EJ-S.
966 @item @b{arm7_9 sw_bkpts} <@option{enable}|@option{disable}>
967 @cindex arm7_9 sw_bkpts
968 Enable/disable use of software breakpoints. On ARMv4 systems, this reserves
969 one of the watchpoint registers to implement software breakpoints. Disabling
970 SW Bkpts frees that register again.
971 @item @b{arm7_9 force_hw_bkpts} <@option{enable}|@option{disable}>
972 @cindex arm7_9 force_hw_bkpts
973 When @option{force_hw_bkpts} is enabled, the @option{sw_bkpts} support is disabled, and all
974 breakpoints are turned into hardware breakpoints.
975 @item @b{arm7_9 dbgrq} <@option{enable}|@option{disable}>
977 Enable use of the DBGRQ bit to force entry into debug mode. This should be
978 safe for all but ARM7TDMI--S cores (like Philips LPC).
979 @item @b{arm7_9 fast_writes} <@option{enable}|@option{disable}>
980 @cindex arm7_9 fast_writes [DEPRECATED]
981 See @option{arm7_9 fast_memory_access} instead.
982 @item @b{arm7_9 fast_memory_access} <@option{enable}|@option{disable}>
983 @cindex arm7_9 fast_memory_access
984 Allow the OpenOCD to read and write memory without checking completion of
985 the operation. This provides a huge speed increase, especially with USB JTAG
986 cables (FT2232), but might be unsafe if used with targets running at a very low
987 speed, like the 32kHz startup clock of an AT91RM9200.
988 @item @b{arm7_9 dcc_downloads} <@option{enable}|@option{disable}>
989 @cindex arm7_9 dcc_downloads
990 Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
991 amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
992 unsafe, especially with targets running at a very low speed. This command was introduced
993 with OpenOCD rev. 60.
996 @subsection ARM920T specific commands
997 @cindex ARM920T specific commands
1000 @item @b{arm920t cache_info}
1001 @cindex arm920t cache_info
1002 Print information about the caches found. This allows you to see if your target
1003 is a ARM920T (2x16kByte cache) or ARM922T (2x8kByte cache).
1004 @item @b{arm920t md<bhw>_phys} <@var{addr}> [@var{count}]
1005 @cindex arm920t md<bhw>_phys
1006 Display memory at physical address addr.
1007 @item @b{arm920t mw<bhw>_phys} <@var{addr}> <@var{value}>
1008 @cindex arm920t mw<bhw>_phys
1009 Write memory at physical address addr.
1010 @item @b{arm920t read_cache} <@var{filename}>
1011 @cindex arm920t read_cache
1012 Dump the content of ICache and DCache to a file.
1013 @item @b{arm920t read_mmu} <@var{filename}>
1014 @cindex arm920t read_mmu
1015 Dump the content of the ITLB and DTLB to a file.
1016 @item @b{arm920t virt2phys} <@var{VA}>
1017 @cindex arm920t virt2phys
1018 Translate a virtual address to a physical address.
1022 @section Debug commands
1023 @cindex Debug commands
1024 The following commands give direct access to the core, and are most likely
1025 only useful while debugging the OpenOCD.
1027 @item @b{arm7_9 write_xpsr} <@var{32-bit value}> <@option{0=cpsr}, @option{1=spsr}>
1028 @cindex arm7_9 write_xpsr
1029 Immediately write either the current program status register (CPSR) or the saved
1030 program status register (SPSR), without changing the register cache (as displayed
1031 by the @option{reg} and @option{armv4_5 reg} commands).
1032 @item @b{arm7_9 write_xpsr_im8} <@var{8-bit value}> <@var{rotate 4-bit}>
1033 <@var{0=cpsr},@var{1=spsr}>
1034 @cindex arm7_9 write_xpsr_im8
1035 Write the 8-bit value rotated right by 2*rotate bits, using an immediate write
1036 operation (similar to @option{write_xpsr}).
1037 @item @b{arm7_9 write_core_reg} <@var{num}> <@var{mode}> <@var{value}>
1038 @cindex arm7_9 write_core_reg
1039 Write a core register, without changing the register cache (as displayed by the
1040 @option{reg} and @option{armv4_5 reg} commands). The <@var{mode}> argument takes the
1041 encoding of the [M4:M0] bits of the PSR.
1045 @section JTAG commands
1046 @cindex JTAG commands
1048 @item @b{scan_chain}
1050 Print current scan chain configuration.
1051 @item @b{jtag_reset}
1053 Toggle reset lines <@var{trst}> <@var{srst}>.
1054 @item @b{endstate} <@var{tap_state}>
1056 Finish JTAG operations in <@var{tap_state}>.
1057 @item @b{runtest} <@var{num_cycles}>
1059 Move to Run-Test/Idle, and execute <@var{num_cycles}>
1060 @item @b{statemove} [@var{tap_state}]
1062 Move to current endstate or [@var{tap_state}]
1065 Execute IR scan <@var{device}> <@var{instr}> [@var{dev2}] [@var{instr2}] ...
1068 Execute DR scan <@var{device}> [@var{dev2}] [@var{var2}] ...
1069 @item @b{verify_ircapture}
1070 @cindex verify_ircapture
1071 Verify value captured during Capture-IR <@option{enable}|@option{disable}>
1074 Allocate, display or delete variable <@var{name}> [@var{num_fields}|@var{del}] [@var{size1}] ...
1077 Display/modify variable field <@var{var}> <@var{field}> [@var{value}|@var{flip}]
1080 @node Sample Scripts
1081 @chapter Sample Scripts
1084 This page will collect some script examples for different CPUs.
1086 The configuration script can be divided in the following section:
1088 @item daemon configuration
1090 @item jtag scan chain
1091 @item target configuration
1092 @item flash configuration
1095 Detailed information about each section can be found at OpenOCD configuration
1097 @section OMAP5912 Flash Debug
1098 @cindex OMAP5912 Flash Debug
1099 The following two scripts were used with a wiggler PP and and a TI OMAP5912
1100 dual core processor - (@uref{http://www.ti.com}), on a OMAP5912 OSK board
1101 - (@uref{http://www.spectrumdigital.com}).
1102 @subsection Openocd config
1104 #daemon configuration
1111 parport_cable wiggler
1114 #use combined on interfaces or targets that can't set TRST/SRST separately
1115 reset_config trst_and_srst
1118 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1119 jtag_device 38 0x0 0x0 0x0
1120 jtag_device 4 0x1 0x0 0xe
1121 jtag_device 8 0x0 0x0 0x0
1123 #target configuration
1124 daemon_startup reset
1126 #target <type> <endianness> <reset mode> <chainpos> <variant>
1127 target arm926ejs little run_and_init 1 arm926ejs
1128 target_script 0 reset omap5912_osk.init
1129 run_and_halt_time 0 30
1131 # omap5912 lcd frame buffer as working area
1132 working_area 0 0x20000000 0x3e800 nobackup
1134 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1135 flash bank cfi 0x00000000 0x1000000 2 2 0
1138 @subsection Openocd init
1150 mww 0xfffec808 0x000000f5
1151 mww 0xfffec808 0x000000a0
1153 mww 0xfffeb048 0x0000aaaa
1155 mww 0xfffeb048 0x00005555
1164 @section STR71x Script
1165 @cindex STR71x Script
1166 The following script was used with an Amontec JTAGkey and a STR710 / STR711 CPU:
1168 #daemon configuration
1174 ft2232_device_desc "Amontec JTAGkey A"
1175 ft2232_layout jtagkey
1176 ft2232_vid_pid 0x0403 0xcff8
1179 #use combined on interfaces or targets that can't set TRST/SRST separately
1180 reset_config trst_and_srst srst_pulls_trst
1183 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1184 jtag_device 4 0x1 0xf 0xe
1186 #target configuration
1187 daemon_startup reset
1189 #target <type> <startup mode>
1190 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1191 target arm7tdmi little run_and_halt 0 arm7tdmi
1192 run_and_halt_time 0 30
1194 working_area 0 0x2000C000 0x4000 nobackup
1196 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1197 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
1200 @section STR750 Script
1201 @cindex STR750 Script
1202 The following script was used with an Amontec JTAGkey and a STR750 CPU:
1204 #daemon configuration
1210 ft2232_device_desc "Amontec JTAGkey A"
1211 ft2232_layout jtagkey
1212 ft2232_vid_pid 0x0403 0xcff8
1215 #use combined on interfaces or targets that can't set TRST/SRST separately
1216 #reset_config trst_and_srst srst_pulls_trst
1217 reset_config trst_and_srst srst_pulls_trst
1220 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1221 jtag_device 4 0x1 0xf 0xe
1223 #jtag nTRST and nSRST delay
1224 jtag_nsrst_delay 500
1225 jtag_ntrst_delay 500
1227 #target configuration
1228 daemon_startup reset
1230 #target <type> <startup mode>
1231 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1232 target arm7tdmi little run_and_halt 0 arm7tdmi
1233 run_and_halt_time 0 30
1235 working_area 0 0x40000000 0x4000 nobackup
1237 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1238 flash bank str7x 0x20000000 0x000040000 0 0 0 STR75x
1241 @section STR912 Script
1242 @cindex STR912 Script
1243 The following script was used with an Amontec JTAGkey and a STR912 CPU:
1245 #daemon configuration
1251 ft2232_device_desc "Amontec JTAGkey A"
1252 ft2232_layout jtagkey
1255 #use combined on interfaces or targets that can't set TRST/SRST separately
1256 reset_config trst_and_srst
1259 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1260 jtag_device 8 0x1 0x1 0xfe
1261 jtag_device 4 0x1 0xf 0xe
1262 jtag_device 5 0x1 0x1 0x1e
1264 #target configuration
1265 daemon_startup reset
1267 #target <type> <startup mode>
1268 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1269 target arm966e little reset_halt 1 arm966e
1270 run_and_halt_time 0 30
1272 working_area 0 0x50000000 16384 nobackup
1274 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1275 flash bank str9x 0x00000000 0x00080000 0 0 0
1278 @section STR912 comstick
1279 @cindex STR912 comstick Script
1280 The following script was used with a Hitex STR9 Comstick:
1282 #daemon configuration
1288 ft2232_device_desc "STR9-comStick A"
1289 ft2232_layout comstick
1292 jtag_nsrst_delay 100
1293 jtag_ntrst_delay 100
1295 #use combined on interfaces or targets that can't set TRST/SRST separately
1296 reset_config trst_and_srst
1299 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1300 jtag_device 8 0x1 0x1 0xfe
1301 jtag_device 4 0x1 0xf 0xe
1302 jtag_device 5 0x1 0x1 0x1e
1304 #target configuration
1305 daemon_startup reset
1307 #target <type> <startup mode>
1308 #target arm966e <endianness> <reset mode> <chainpos> <variant>
1309 target arm966e little reset_halt 1 arm966e
1310 run_and_halt_time 0 30
1312 working_area 0 0x50000000 16384 nobackup
1314 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1315 flash bank str9x 0x00000000 0x00080000 0 0 0
1318 @section STM32x Script
1319 @cindex STM32x Script
1320 The following script was used with an Amontec JTAGkey and a STM32x CPU:
1322 #daemon configuration
1328 ft2232_device_desc "Amontec JTAGkey A"
1329 ft2232_layout jtagkey
1332 jtag_nsrst_delay 100
1333 jtag_ntrst_delay 100
1335 #use combined on interfaces or targets that can't set TRST/SRST separately
1336 reset_config trst_and_srst
1339 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1340 jtag_device 4 0x1 0xf 0xe
1341 jtag_device 5 0x1 0x1 0x1e
1343 #target configuration
1344 daemon_startup reset
1346 #target <type> <startup mode>
1347 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1348 target cortex_m3 little run_and_halt 0
1349 run_and_halt_time 0 30
1351 working_area 0 0x20000000 16384 nobackup
1353 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1354 flash bank stm32x 0x08000000 0x00020000 0 0 0
1357 @section STM32x Performance Stick
1358 @cindex STM32x Performance Stick Script
1359 The following script was used with the Hitex STM32 Performance Stick
1361 #daemon configuration
1367 ft2232_device_desc "STM32-PerformanceStick A"
1368 ft2232_layout stm32stick
1371 jtag_nsrst_delay 100
1372 jtag_ntrst_delay 100
1374 #use combined on interfaces or targets that can't set TRST/SRST separately
1375 reset_config trst_and_srst
1378 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1379 jtag_device 4 0x1 0xf 0xe
1380 jtag_device 5 0x1 0x1 0x1e
1381 jtag_device 4 0x1 0xf 0xe
1383 #target configuration
1384 daemon_startup reset
1386 #target <type> <startup mode>
1387 #target cortex_m3 <endianness> <reset mode> <chainpos> <variant>
1388 target cortex_m3 little run_and_halt 0
1389 run_and_halt_time 0 30
1391 working_area 0 0x20000000 16384 nobackup
1393 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1394 flash bank stm32x 0x08000000 0x00020000 0 0 0
1397 @section LPC2129 Script
1398 @cindex LPC2129 Script
1399 The following script was used with an wiggler PP and a LPC-2129 CPU:
1401 #daemon configuration
1408 parport_cable wiggler
1411 #use combined on interfaces or targets that can't set TRST/SRST separately
1412 reset_config trst_and_srst srst_pulls_trst
1415 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1416 jtag_device 4 0x1 0xf 0xe
1418 #target configuration
1419 daemon_startup reset
1421 #target <type> <startup mode>
1422 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1423 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1424 run_and_halt_time 0 30
1426 working_area 0 0x40000000 0x4000 nobackup
1428 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1429 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1432 @section LPC2148 Script
1433 @cindex LPC2148 Script
1434 The following script was used with an Amontec JTAGkey and a LPC2148 CPU:
1436 #daemon configuration
1442 ft2232_device_desc "Amontec JTAGkey A"
1443 ft2232_layout jtagkey
1444 ft2232_vid_pid 0x0403 0xcff8
1447 #use combined on interfaces or targets that can't set TRST/SRST separately
1448 reset_config trst_and_srst srst_pulls_trst
1451 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1452 jtag_device 4 0x1 0xf 0xe
1454 #target configuration
1455 daemon_startup reset
1457 #target <type> <startup mode>
1458 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1459 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1460 run_and_halt_time 0 30
1462 working_area 0 0x40000000 0x8000 nobackup
1464 #flash configuration
1465 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v1 14765 calc_checksum
1468 @section LPC2294 Script
1469 @cindex LPC2294 Script
1470 The following script was used with an Amontec JTAGkey and a LPC2294 CPU:
1472 #daemon configuration
1478 ft2232_device_desc "Amontec JTAGkey A"
1479 ft2232_layout jtagkey
1480 ft2232_vid_pid 0x0403 0xcff8
1483 #use combined on interfaces or targets that can't set TRST/SRST separately
1484 reset_config trst_and_srst srst_pulls_trst
1487 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1488 jtag_device 4 0x1 0xf 0xe
1490 #target configuration
1491 daemon_startup reset
1493 #target <type> <startup mode>
1494 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1495 target arm7tdmi little run_and_halt 0 arm7tdmi-s_r4
1496 run_and_halt_time 0 30
1498 working_area 0 0x40000000 0x4000 nobackup
1500 #flash configuration
1501 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
1504 @section AT91R40008 Script
1505 @cindex AT91R40008 Script
1506 The following script was used with an Amontec JTAGkey and a AT91R40008 CPU:
1508 #daemon configuration
1514 ft2232_device_desc "Amontec JTAGkey A"
1515 ft2232_layout jtagkey
1516 ft2232_vid_pid 0x0403 0xcff8
1518 jtag_nsrst_delay 200
1519 jtag_ntrst_delay 200
1521 #use combined on interfaces or targets that can't set TRST/SRST separately
1522 reset_config srst_only srst_pulls_trst
1525 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1526 jtag_device 4 0x1 0xf 0xe
1528 #target configuration
1529 daemon_startup reset
1531 #target <type> <startup mode>
1532 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1533 target arm7tdmi little run_and_halt 0 arm7tdmi
1534 run_and_halt_time 0 30
1537 @section AT91SAM7s Script
1538 @cindex AT91SAM7s Script
1539 The following script was used with an Olimex ARM-JTAG-OCD and a AT91SAM7S64 CPU:
1541 #daemon configuration
1547 ft2232_device_desc "Olimex OpenOCD JTAG A"
1548 ft2232_layout olimex-jtag
1549 ft2232_vid_pid 0x15BA 0x0003
1551 jtag_nsrst_delay 200
1552 jtag_ntrst_delay 200
1554 #use combined on interfaces or targets that can't set TRST/SRST separately
1555 reset_config srst_only srst_pulls_trst
1558 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1559 jtag_device 4 0x1 0xf 0xe
1561 #target configuration
1562 daemon_startup reset
1564 #target <type> <startup mode>
1565 #target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
1566 target arm7tdmi little run_and_halt 0 arm7tdmi
1567 run_and_halt_time 0 30
1569 # flash-options AT91
1570 working_area 0 0x00200000 0x4000 nobackup
1571 flash bank at91sam7 0 0 0 0 0
1574 # erase command (telnet-interface) for complete flash:
1575 # flash erase <num> 0 numlockbits-1 (can be seen from output of flash info 0)
1576 # SAM7S64 with 16 lockbits and bank 0: flash erase 0 0 15
1577 # set/clear NVM-Bits:
1578 # at91sam7 gpnvm <num> <bit> <set|clear>
1579 # disable locking from SAM-BA:
1580 # flash protect 0 0 1 off
1583 @section XSCALE IXP42x Script
1584 @cindex XSCALE IXP42x Script
1585 The following script was used with an Amontec JTAGkey-Tiny and a xscale ixp42x CPU:
1587 #daemon configuration
1593 ft2232_device_desc "Amontec JTAGkey A"
1594 ft2232_layout jtagkey
1595 ft2232_vid_pid 0x0403 0xcff8
1597 jtag_nsrst_delay 200
1598 jtag_ntrst_delay 200
1600 #use combined on interfaces or targets that can't set TRST/SRST separately
1601 reset_config srst_only srst_pulls_trst
1604 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1605 jtag_device 7 0x1 0x7f 0x7e
1607 #target configuration
1608 daemon_startup reset
1610 #target <type> <startup mode>
1611 #target arm7tdmi <reset mode> <chainpos> <endianness> <variant>
1612 target xscale big run_and_halt 0 IXP42x
1613 run_and_halt_time 0 30
1616 @section Cirrus Logic EP9301 Script
1617 @cindex Cirrus Logic EP9301 Script
1618 The following script was used with FT2232 based JTAG interfaces and a
1619 Cirrus Logic EP9301 processor on an Olimex CS-E9301 board.
1621 #daemon configuration
1629 #ft2232_device_desc "Olimex OpenOCD JTAG"
1630 #ft2232_layout olimex-jtag
1631 #ft2232_vid_pid 0x15ba 0x0003
1633 #Amontec JTAGkey (and JTAGkey-Tiny)
1634 #Serial is only necessary if more than one JTAGkey is connected
1635 ft2232_device_desc "Amontec JTAGkey A"
1636 #ft2232_serial AMTJKV31
1637 #ft2232_serial T1P3S2W8
1638 ft2232_layout jtagkey
1639 ft2232_vid_pid 0x0403 0xcff8
1641 #wiggler/parallel port interface
1644 #parport_cable wiggler
1647 reset_config trst_and_srst
1650 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1651 jtag_device 4 0x1 0xf 0xe
1653 jtag_nsrst_delay 100
1654 jtag_ntrst_delay 100
1656 #target configuration
1657 daemon_startup attach
1659 #target <type> <endianess> <reset mode>
1660 target arm920t little reset_halt 0
1661 working_area 0 0x80014000 0x1000 backup
1663 #flash configuration
1664 #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
1665 flash bank cfi 0x60000000 0x1000000 2 2 0
1668 @section Hilscher netX 100 / 500 Script
1669 @cindex Hilscher netX 100 / 500 Script
1670 The following script was used with an Amontec JTAGkey and a Hilscher
1673 #daemon configuration
1679 ft2232_device_desc "Amontec JTAGkey A"
1680 ft2232_layout jtagkey
1681 ft2232_vid_pid 0x0403 0xcff8
1684 #use combined on interfaces or targets that can't set TRST/SRST separately
1685 reset_config trst_and_srst
1688 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1689 jtag_device 4 0x1 0xf 0xe
1691 jtag_nsrst_delay 100
1692 jtag_ntrst_delay 100
1694 #target configuration
1695 daemon_startup reset
1697 #target <type> <endianness> <startup mode> <chainpos> <variant>
1698 target arm926ejs little run_and_halt 0 arm926ejs
1699 run_and_halt_time 0 500
1702 @section Marvell/Intel PXA270 Script
1703 @cindex Marvell/Intel PXA270 Script
1705 # config for Intel PXA270
1706 # not, as of 2007-06-22, openocd only works with the
1707 # libftd2xx library from ftdi. libftdi does not work.
1713 ft2232_layout olimex-jtag
1714 ft2232_vid_pid 0x15BA 0x0003
1715 ft2232_device_desc "Olimex OpenOCD JTAG"
1717 # set jtag_nsrst_delay to the delay introduced by your reset circuit
1718 # the rest of the needed delays are built into the openocd program
1719 jtag_nsrst_delay 260
1720 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
1721 # the rest of the needed delays are built into the openocd program
1724 #use combined on interfaces or targets that can't set TRST/SRST separately
1725 reset_config trst_and_srst separate
1728 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
1729 jtag_device 7 0x1 0x7f 0x7e
1731 #target configuration
1732 daemon_startup reset
1734 target xscale little reset_halt 0 pxa27x
1736 # maps to PXA internal RAM. If you are using a PXA255
1737 # you must initialize SDRAM or leave this option off
1738 working_area 0 0x5c000000 0x10000 nobackup
1740 run_and_halt_time 0 30
1742 #flash bank <driver> <base> <size> <chip_width> <bus_width>
1743 # works for P30 flash
1744 flash bank cfi 0x00000000 0x1000000 2 4 0
1747 @node GDB and Openocd
1748 @chapter GDB and Openocd
1749 @cindex GDB and Openocd
1750 Openocd complies with the remote gdbserver protocol, and as such can be used
1751 to debug remote targets.
1753 @section Connecting to gdb
1754 @cindex Connecting to gdb
1755 A connection is typically started as follows:
1757 target remote localhost:3333
1759 This would cause gdb to connect to the gdbserver on the local pc using port 3333.
1761 To see a list of available openocd commands type @option{monitor help} on the
1764 Openocd supports the gdb @option{qSupported} packet, this enables information
1765 to be sent by the gdb server (openocd) to gdb. Typical information includes
1766 packet size and device memory map.
1768 Previous versions of openocd required the following gdb options to increase
1769 the packet size and speed up gdb communication.
1771 set remote memory-write-packet-size 1024
1772 set remote memory-write-packet-size fixed
1773 set remote memory-read-packet-size 1024
1774 set remote memory-read-packet-size fixed
1776 This is now handled in the @option{qSupported} PacketSize.
1778 @section Programming using gdb
1779 @cindex Programming using gdb
1781 By default the target memory map is not sent to gdb, this can be enabled by
1782 the following openocd config option:
1784 gdb_memory_map enable
1786 For this to function correctly a valid flash config must also be configured
1787 in openocd. For speed also configure a valid working area.
1789 Informing gdb of the memory map of the target will enable gdb to protect any
1790 flash area of the target and use hardware breakpoints by default. This means
1791 that the openocd option @option{arm7_9 force_hw_bkpts} is not required when
1794 To view the configured memory map in gdb, use the gdb command @option{info mem}
1795 All other unasigned addresses within gdb are treated as RAM.
1797 If @option{gdb_flash_program enable} is also used, gdb will be able to
1798 program any flash memory using the vFlash interface.
1800 gdb will look at the target memory map when a load command is given, if any
1801 areas to be programmed lie within the target flash area the vFlash packets
1804 Incase the target needs configuring before gdb programming, a script can be executed.
1806 target_script 0 gdb_program_config config.script
1809 To verify any flash programming the gdb command @option{compare-sections}
1816 @item OpenOCD complains about a missing cygwin1.dll.
1818 Make sure you have Cygwin installed, or at least a version of OpenOCD that
1819 claims to come with all the necessary dlls. When using Cygwin, try launching
1820 the OpenOCD from the Cygwin shell.
1822 @item I'm trying to set a breakpoint using GDB (or a frontend like Insight or
1823 Eclipse), but OpenOCD complains that "Info: arm7_9_common.c:213
1824 arm7_9_add_breakpoint(): sw breakpoint requested, but software breakpoints not enabled".
1826 GDB issues software breakpoints when a normal breakpoint is requested, or to implement
1827 source-line single-stepping. On ARMv4T systems, like ARM7TDMI, ARM720t or ARM920t,
1828 software breakpoints consume one of the two available hardware breakpoints,
1829 and are therefore disabled by default. If your code is running from RAM, you
1830 can enable software breakpoints with the @option{arm7_9 sw_bkpts enable} command. If
1831 your code resides in Flash, you can't use software breakpoints, but you can force
1832 OpenOCD to use hardware breakpoints instead: @option{arm7_9 force_hw_bkpts enable}.
1834 @item When erasing or writing LPC2000 on-chip flash, the operation fails sometimes
1835 and works sometimes fine.
1837 Make sure the core frequency specified in the @option{flash lpc2000} line matches the
1838 clock at the time you're programming the flash. If you've specified the crystal's
1839 frequency, make sure the PLL is disabled, if you've specified the full core speed
1840 (e.g. 60MHz), make sure the PLL is enabled.
1842 @item When debugging using an Amontec Chameleon in its JTAG Accelerator configuration,
1843 I keep getting "Error: amt_jtagaccel.c:184 amt_wait_scan_busy(): amt_jtagaccel timed
1844 out while waiting for end of scan, rtck was disabled".
1846 Make sure your PC's parallel port operates in EPP mode. You might have to try several
1847 settings in your PC BIOS (ECP, EPP, and different versions of those).
1849 @item When debugging with the OpenOCD and GDB (plain GDB, Insight, or Eclipse),
1850 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
1851 memory read caused data abort".
1853 The errors are non-fatal, and are the result of GDB trying to trace stack frames
1854 beyond the last valid frame. It might be possible to prevent this by setting up
1855 a proper "initial" stack frame, if you happen to know what exactly has to
1856 be done, feel free to add this here.
1858 @item I get the following message in the OpenOCD console (or log file):
1859 "Warning: arm7_9_common.c:679 arm7_9_assert_reset(): srst resets test logic, too".
1861 This warning doesn't indicate any serious problem, as long as you don't want to
1862 debug your core right out of reset. Your .cfg file specified @option{jtag_reset
1863 trst_and_srst srst_pulls_trst} to tell the OpenOCD that either your board,
1864 your debugger or your target uC (e.g. LPC2000) can't assert the two reset signals
1865 independently. With this setup, it's not possible to halt the core right out of
1866 reset, everything else should work fine.
1868 @item When using OpenOCD in conjunction with Amontec JTAGkey and the Yagarto
1869 Toolchain (Eclipse, arm-elf-gcc, arm-elf-gdb), the debugging seems to be
1870 unstable. When single-stepping over large blocks of code, GDB and OpenOCD
1871 quit with an error message. Is there a stability issue with OpenOCD?
1873 No, this is not a stability issue concerning OpenOCD. Most users have solved
1874 this issue by simply using a self-powered USB hub, which they connect their
1875 Amontec JTAGkey to. Apparently, some computers do not provide a USB power
1876 supply stable enough for the Amontec JTAGkey to be operated.
1878 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the
1879 following error messages: "Error: ft2232.c:201 ft2232_read(): FT_Read returned:
1880 4" and "Error: ft2232.c:365 ft2232_send_and_recv(): couldn't read from FT2232".
1881 What does that mean and what might be the reason for this?
1883 First of all, the reason might be the USB power supply. Try using a self-powered
1884 hub instead of a direct connection to your computer. Secondly, the error code 4
1885 corresponds to an FT_IO_ERROR, which means that the driver for the FTDI USB
1886 chip ran into some sort of error - this points us to a USB problem.
1888 @item When using the Amontec JTAGkey, sometimes OpenOCD crashes with the following
1889 error message: "Error: gdb_server.c:101 gdb_get_char(): read: 10054".
1890 What does that mean and what might be the reason for this?
1892 Error code 10054 corresponds to WSAECONNRESET, which means that the debugger (GDB)
1893 has closed the connection to OpenOCD. This might be a GDB issue.
1895 @item In the configuration file in the section where flash device configurations
1896 are described, there is a parameter for specifying the clock frequency for
1897 LPC2000 internal flash devices (e.g.
1898 @option{flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}),
1899 which must be specified in kilohertz. However, I do have a quartz crystal of a
1900 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz, i.e. 14,745.600 kHz).
1901 Is it possible to specify real numbers for the clock frequency?
1903 No. The clock frequency specified here must be given as an integral number.
1904 However, this clock frequency is used by the In-Application-Programming (IAP)
1905 routines of the LPC2000 family only, which seems to be very tolerant concerning
1906 the given clock frequency, so a slight difference between the specified clock
1907 frequency and the actual clock frequency will not cause any trouble.
1909 @item Do I have to keep a specific order for the commands in the configuration file?
1911 Well, yes and no. Commands can be given in arbitrary order, yet the devices
1912 listed for the JTAG scan chain must be given in the right order (jtag_device),
1913 with the device closest to the TDO-Pin being listed first. In general,
1914 whenever objects of the same type exist which require an index number, then
1915 these objects must be given in the right order (jtag_devices, targets and flash
1916 banks - a target references a jtag_device and a flash bank references a target).
1918 @item Sometimes my debugging session terminates with an error. When I look into the
1919 log file, I can see these error messages: Error: arm7_9_common.c:561
1920 arm7_9_execute_sys_speed(): timeout waiting for SYSCOMP