1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 /***************************************************************************
22 There are some things to notice
24 * AT91SAM7S64 is tested
25 * All AT91SAM7Sxx and AT91SAM7Xxx should work but is not tested
26 * All parameters are identified from onchip configuartion registers
28 * The flash controller handles erases automatically on a page (128/265 byte) basis
29 * Only an EraseAll command is supported by the controller
30 * Partial erases can be implemented in software by writing one 0xFFFFFFFF word to
31 * some location in every page in the region to be erased
33 * Lock regions (sectors) are 32 or 64 pages
35 ***************************************************************************/
40 #include "replacements.h"
47 #include "binarybuffer.h"
54 int at91sam7_register_commands(struct command_context_s
*cmd_ctx
);
55 int at91sam7_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
56 int at91sam7_erase(struct flash_bank_s
*bank
, int first
, int last
);
57 int at91sam7_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
58 int at91sam7_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
59 int at91sam7_probe(struct flash_bank_s
*bank
);
60 int at91sam7_erase_check(struct flash_bank_s
*bank
);
61 int at91sam7_protect_check(struct flash_bank_s
*bank
);
62 int at91sam7_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
64 u32
at91sam7_get_flash_status(flash_bank_t
*bank
);
65 void at91sam7_set_flash_mode(flash_bank_t
*bank
,int mode
);
66 u32
at91sam7_wait_status_busy(flash_bank_t
*bank
, u32 waitbits
, int timeout
);
67 int at91sam7_handle_gpnvm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
69 flash_driver_t at91sam7_flash
=
72 .register_commands
= at91sam7_register_commands
,
73 .flash_bank_command
= at91sam7_flash_bank_command
,
74 .erase
= at91sam7_erase
,
75 .protect
= at91sam7_protect
,
76 .write
= at91sam7_write
,
77 .probe
= at91sam7_probe
,
78 .erase_check
= at91sam7_erase_check
,
79 .protect_check
= at91sam7_protect_check
,
84 char * EPROC
[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
100 0x200000, /* 2048K */
123 int at91sam7_register_commands(struct command_context_s
*cmd_ctx
)
125 command_t
*at91sam7_cmd
= register_command(cmd_ctx
, NULL
, "at91sam7", NULL
, COMMAND_ANY
, NULL
);
126 register_command(cmd_ctx
, at91sam7_cmd
, "gpnvm", at91sam7_handle_gpnvm_command
, COMMAND_EXEC
,
127 "at91sam7 gpnvm <num> <bit> set|clear, set or clear at91sam7 gpnvm bit");
132 u32
at91sam7_get_flash_status(flash_bank_t
*bank
)
134 target_t
*target
= bank
->target
;
137 target_read_u32(target
, MC_FSR
, &fsr
);
142 /** Read clock configuration and set at91sam7_info->usec_clocks*/
143 void at91sam7_read_clock_info(flash_bank_t
*bank
)
145 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
146 target_t
*target
= bank
->target
;
147 u32 mckr
, mcfr
, pllr
;
148 unsigned long tmp
= 0, mainfreq
;
150 /* Read main clock freqency register */
151 target_read_u32(target
, CKGR_MCFR
, &mcfr
);
152 /* Read master clock register */
153 target_read_u32(target
, PMC_MCKR
, &mckr
);
154 /* Read Clock Generator PLL Register */
155 target_read_u32(target
, CKGR_PLLR
, &pllr
);
157 at91sam7_info
->mck_valid
= 0;
158 switch (mckr
& PMC_MCKR_CSS
) {
159 case 0: /* Slow Clock */
160 at91sam7_info
->mck_valid
= 1;
163 case 1: /* Main Clock */
164 if (mcfr
& CKGR_MCFR_MAINRDY
)
166 at91sam7_info
->mck_valid
= 1;
167 mainfreq
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
172 case 2: /* Reserved */
174 case 3: /* PLL Clock */
175 if (mcfr
& CKGR_MCFR_MAINRDY
)
177 target_read_u32(target
, CKGR_PLLR
, &pllr
);
178 if (!(pllr
& CKGR_PLLR_DIV
))
180 at91sam7_info
->mck_valid
= 1;
181 mainfreq
= RC_FREQ
/ 16ul * (mcfr
& 0xffff);
182 /* Integer arithmetic should have sufficient precision
183 as long as PLL is properly configured. */
184 tmp
= mainfreq
/ (pllr
& CKGR_PLLR_DIV
) *
185 (((pllr
& CKGR_PLLR_MUL
) >> 16) + 1);
190 /* Prescaler adjust */
191 if (((mckr
& PMC_MCKR_PRES
) >> 2) == 7)
192 at91sam7_info
->mck_valid
= 0;
194 at91sam7_info
->mck_freq
= tmp
>> ((mckr
& PMC_MCKR_PRES
) >> 2);
196 /* Forget old flash timing */
197 at91sam7_set_flash_mode(bank
,FMR_TIMING_NONE
);
200 /* Setup the timimg registers for nvbits or normal flash */
201 void at91sam7_set_flash_mode(flash_bank_t
*bank
,int mode
)
203 u32 fmr
, fmcn
= 0, fws
= 0;
204 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
205 target_t
*target
= bank
->target
;
207 if (mode
&& (mode
!= at91sam7_info
->flashmode
))
209 /* Always round up (ceil) */
210 if (mode
==FMR_TIMING_NVBITS
)
212 if (at91sam7_info
->cidr_arch
== 0x60)
214 /* AT91SAM7A3 uses master clocks in 100 ns */
215 fmcn
= (at91sam7_info
->mck_freq
/10000000ul)+1;
219 /* master clocks in 1uS for ARCH 0x7 types */
220 fmcn
= (at91sam7_info
->mck_freq
/1000000ul)+1;
223 else if (mode
==FMR_TIMING_FLASH
)
224 /* main clocks in 1.5uS */
225 fmcn
= (at91sam7_info
->mck_freq
/666666ul)+1;
227 /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
228 if (at91sam7_info
->mck_freq
<= 33333ul)
230 /* Only allow fws=0 if clock frequency is < 30 MHz. */
231 if (at91sam7_info
->mck_freq
> 30000000ul)
234 DEBUG("fmcn: %i", fmcn
);
235 fmr
= fmcn
<< 16 | fws
<< 8;
236 target_write_u32(target
, MC_FMR
, fmr
);
239 at91sam7_info
->flashmode
= mode
;
242 u32
at91sam7_wait_status_busy(flash_bank_t
*bank
, u32 waitbits
, int timeout
)
246 while ((!((status
= at91sam7_get_flash_status(bank
)) & waitbits
)) && (timeout
-- > 0))
248 DEBUG("status: 0x%x", status
);
252 DEBUG("status: 0x%x", status
);
256 ERROR("status register: 0x%x", status
);
258 ERROR("Lock Error Bit Detected, Operation Abort");
260 ERROR("Invalid command and/or bad keyword, Operation Abort");
262 ERROR("Security Bit Set, Operation Abort");
269 /* Send one command to the AT91SAM flash controller */
270 int at91sam7_flash_command(struct flash_bank_s
*bank
,u8 cmd
,u16 pagen
)
273 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
274 target_t
*target
= bank
->target
;
276 fcr
= (0x5A<<24) | (pagen
<<8) | cmd
;
277 target_write_u32(target
, MC_FCR
, fcr
);
278 DEBUG("Flash command: 0x%x, pagenumber:%u", fcr
, pagen
);
280 if ((at91sam7_info
->cidr_arch
== 0x60)&&((cmd
==SLB
)|(cmd
==CLB
)))
282 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
283 if (at91sam7_wait_status_busy(bank
, MC_FSR_EOL
, 10)&0x0C)
285 return ERROR_FLASH_OPERATION_FAILED
;
290 if (at91sam7_wait_status_busy(bank
, MC_FSR_FRDY
, 10)&0x0C)
292 return ERROR_FLASH_OPERATION_FAILED
;
297 /* Read device id register, main clock frequency register and fill in driver info structure */
298 int at91sam7_read_part_info(struct flash_bank_s
*bank
)
300 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
301 target_t
*target
= bank
->target
;
304 if (bank
->target
->state
!= TARGET_HALTED
)
306 return ERROR_TARGET_NOT_HALTED
;
309 /* Read and parse chip identification register */
310 target_read_u32(target
, DBGU_CIDR
, &cidr
);
314 WARNING("Cannot identify target as an AT91SAM");
315 return ERROR_FLASH_OPERATION_FAILED
;
318 at91sam7_info
->cidr
= cidr
;
319 at91sam7_info
->cidr_ext
= (cidr
>>31)&0x0001;
320 at91sam7_info
->cidr_nvptyp
= (cidr
>>28)&0x0007;
321 at91sam7_info
->cidr_arch
= (cidr
>>20)&0x00FF;
322 at91sam7_info
->cidr_sramsiz
= (cidr
>>16)&0x000F;
323 at91sam7_info
->cidr_nvpsiz2
= (cidr
>>12)&0x000F;
324 at91sam7_info
->cidr_nvpsiz
= (cidr
>>8)&0x000F;
325 at91sam7_info
->cidr_eproc
= (cidr
>>5)&0x0007;
326 at91sam7_info
->cidr_version
= cidr
&0x001F;
327 bank
->size
= NVPSIZ
[at91sam7_info
->cidr_nvpsiz
];
328 at91sam7_info
->target_name
= "Unknown";
330 DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info
->cidr_nvptyp
, at91sam7_info
->cidr_arch
);
332 /* Read main and master clock freqency register */
333 at91sam7_read_clock_info(bank
);
335 status
= at91sam7_get_flash_status(bank
);
336 at91sam7_info
->lockbits
= status
>>16;
337 at91sam7_info
->securitybit
= (status
>>4)&0x01;
339 if (at91sam7_info
->cidr_arch
== 0x70 )
341 at91sam7_info
->num_nvmbits
= 2;
342 at91sam7_info
->nvmbits
= (status
>>8)&0x03;
343 bank
->base
= 0x100000;
345 if (bank
->size
==0x40000) /* AT91SAM7S256 */
347 at91sam7_info
->target_name
= "AT91SAM7S256";
348 at91sam7_info
->num_lockbits
= 16;
349 at91sam7_info
->pagesize
= 256;
350 at91sam7_info
->pages_in_lockregion
= 64;
351 at91sam7_info
->num_pages
= 16*64;
353 if (bank
->size
==0x20000) /* AT91SAM7S128 */
355 at91sam7_info
->target_name
= "AT91SAM7S128";
356 at91sam7_info
->num_lockbits
= 8;
357 at91sam7_info
->pagesize
= 256;
358 at91sam7_info
->pages_in_lockregion
= 64;
359 at91sam7_info
->num_pages
= 8*64;
361 if (bank
->size
==0x10000) /* AT91SAM7S64 */
363 at91sam7_info
->target_name
= "AT91SAM7S64";
364 at91sam7_info
->num_lockbits
= 16;
365 at91sam7_info
->pagesize
= 128;
366 at91sam7_info
->pages_in_lockregion
= 32;
367 at91sam7_info
->num_pages
= 16*32;
369 if (bank
->size
==0x08000) /* AT91SAM7S321/32 */
371 at91sam7_info
->target_name
= "AT91SAM7S321/32";
372 at91sam7_info
->num_lockbits
= 8;
373 at91sam7_info
->pagesize
= 128;
374 at91sam7_info
->pages_in_lockregion
= 32;
375 at91sam7_info
->num_pages
= 8*32;
381 if (at91sam7_info
->cidr_arch
== 0x71 )
383 at91sam7_info
->num_nvmbits
= 3;
384 at91sam7_info
->nvmbits
= (status
>>8)&0x07;
385 bank
->base
= 0x100000;
387 if (bank
->size
==0x40000) /* AT91SAM7XC256 */
389 at91sam7_info
->target_name
= "AT91SAM7XC256";
390 at91sam7_info
->num_lockbits
= 16;
391 at91sam7_info
->pagesize
= 256;
392 at91sam7_info
->pages_in_lockregion
= 64;
393 at91sam7_info
->num_pages
= 16*64;
395 if (bank
->size
==0x20000) /* AT91SAM7XC128 */
397 at91sam7_info
->target_name
= "AT91SAM7XC128";
398 at91sam7_info
->num_lockbits
= 8;
399 at91sam7_info
->pagesize
= 256;
400 at91sam7_info
->pages_in_lockregion
= 64;
401 at91sam7_info
->num_pages
= 8*64;
407 if (at91sam7_info
->cidr_arch
== 0x72 )
409 at91sam7_info
->num_nvmbits
= 2;
410 at91sam7_info
->nvmbits
= (status
>>8)&0x03;
411 bank
->base
= 0x100000;
413 if (bank
->size
==0x80000) /* AT91SAM7SE512 */
415 at91sam7_info
->target_name
= "AT91SAM7SE512";
416 at91sam7_info
->num_lockbits
= 32;
417 at91sam7_info
->pagesize
= 256;
418 at91sam7_info
->pages_in_lockregion
= 64;
419 at91sam7_info
->num_pages
= 32*64;
421 if (bank
->size
==0x40000)
423 at91sam7_info
->target_name
= "AT91SAM7SE256";
424 at91sam7_info
->num_lockbits
= 16;
425 at91sam7_info
->pagesize
= 256;
426 at91sam7_info
->pages_in_lockregion
= 64;
427 at91sam7_info
->num_pages
= 16*64;
429 if (bank
->size
==0x08000)
431 at91sam7_info
->target_name
= "AT91SAM7SE32";
432 at91sam7_info
->num_lockbits
= 8;
433 at91sam7_info
->pagesize
= 128;
434 at91sam7_info
->pages_in_lockregion
= 32;
435 at91sam7_info
->num_pages
= 8*32;
441 if (at91sam7_info
->cidr_arch
== 0x75 )
443 at91sam7_info
->num_nvmbits
= 3;
444 at91sam7_info
->nvmbits
= (status
>>8)&0x07;
445 bank
->base
= 0x100000;
447 if (bank
->size
==0x40000) /* AT91SAM7X256 */
449 at91sam7_info
->target_name
= "AT91SAM7X256";
450 at91sam7_info
->num_lockbits
= 16;
451 at91sam7_info
->pagesize
= 256;
452 at91sam7_info
->pages_in_lockregion
= 64;
453 at91sam7_info
->num_pages
= 16*64;
455 if (bank
->size
==0x20000) /* AT91SAM7X128 */
457 at91sam7_info
->target_name
= "AT91SAM7X128";
458 at91sam7_info
->num_lockbits
= 8;
459 at91sam7_info
->pagesize
= 256;
460 at91sam7_info
->pages_in_lockregion
= 64;
461 at91sam7_info
->num_pages
= 8*64;
467 if (at91sam7_info
->cidr_arch
== 0x60 )
469 at91sam7_info
->num_nvmbits
= 3;
470 at91sam7_info
->nvmbits
= (status
>>8)&0x07;
471 bank
->base
= 0x100000;
474 if (bank
->size
== 0x40000) /* AT91SAM7A3 */
476 at91sam7_info
->target_name
= "AT91SAM7A3";
477 at91sam7_info
->num_lockbits
= 16;
478 at91sam7_info
->pagesize
= 256;
479 at91sam7_info
->pages_in_lockregion
= 16;
480 at91sam7_info
->num_pages
= 16*64;
485 WARNING("at91sam7 flash only tested for AT91SAM7Sxx series");
490 int at91sam7_erase_check(struct flash_bank_s
*bank
)
492 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
494 if (!at91sam7_info
->working_area_size
)
504 int at91sam7_protect_check(struct flash_bank_s
*bank
)
508 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
510 if (at91sam7_info
->cidr
== 0)
512 at91sam7_read_part_info(bank
);
515 if (at91sam7_info
->cidr
== 0)
517 WARNING("Cannot identify target as an AT91SAM");
518 return ERROR_FLASH_OPERATION_FAILED
;
521 status
= at91sam7_get_flash_status(bank
);
522 at91sam7_info
->lockbits
= status
>> 16;
527 /* flash_bank at91sam7 0 0 0 0 <target#>
529 int at91sam7_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
531 at91sam7_flash_bank_t
*at91sam7_info
;
535 WARNING("incomplete flash_bank at91sam7 configuration");
536 return ERROR_FLASH_BANK_INVALID
;
539 at91sam7_info
= malloc(sizeof(at91sam7_flash_bank_t
));
540 bank
->driver_priv
= at91sam7_info
;
542 /* part wasn't probed for info yet */
543 at91sam7_info
->cidr
= 0;
548 int at91sam7_erase(struct flash_bank_s
*bank
, int first
, int last
)
550 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
552 if (bank
->target
->state
!= TARGET_HALTED
)
554 return ERROR_TARGET_NOT_HALTED
;
557 if (at91sam7_info
->cidr
== 0)
559 at91sam7_read_part_info(bank
);
562 if (at91sam7_info
->cidr
== 0)
564 WARNING("Cannot identify target as an AT91SAM");
565 return ERROR_FLASH_OPERATION_FAILED
;
568 if ((first
< 0) || (last
< first
) || (last
>= at91sam7_info
->num_lockbits
))
570 return ERROR_FLASH_SECTOR_INVALID
;
573 /* Configure the flash controller timing */
574 at91sam7_read_clock_info(bank
);
575 at91sam7_set_flash_mode(bank
,FMR_TIMING_FLASH
);
577 if ((first
== 0) && (last
== (at91sam7_info
->num_lockbits
-1)))
579 return at91sam7_flash_command(bank
, EA
, 0);
582 WARNING("Can only erase the whole flash area, pages are autoerased on write");
583 return ERROR_FLASH_OPERATION_FAILED
;
586 int at91sam7_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
588 u32 cmd
, pagen
, status
;
591 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
593 if (bank
->target
->state
!= TARGET_HALTED
)
595 return ERROR_TARGET_NOT_HALTED
;
598 if ((first
< 0) || (last
< first
) || (last
>= at91sam7_info
->num_lockbits
))
600 return ERROR_FLASH_SECTOR_INVALID
;
603 if (at91sam7_info
->cidr
== 0)
605 at91sam7_read_part_info(bank
);
608 if (at91sam7_info
->cidr
== 0)
610 WARNING("Cannot identify target as an AT91SAM");
611 return ERROR_FLASH_OPERATION_FAILED
;
614 /* Configure the flash controller timing */
615 at91sam7_read_clock_info(bank
);
616 at91sam7_set_flash_mode(bank
,FMR_TIMING_NVBITS
);
618 for (lockregion
=first
;lockregion
<=last
;lockregion
++)
620 pagen
= lockregion
*at91sam7_info
->pages_in_lockregion
;
625 if (at91sam7_flash_command(bank
, cmd
, pagen
) != ERROR_OK
)
627 return ERROR_FLASH_OPERATION_FAILED
;
631 status
= at91sam7_get_flash_status(bank
);
632 at91sam7_info
->lockbits
= status
>>16;
638 int at91sam7_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
640 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
641 target_t
*target
= bank
->target
;
642 u32 dst_min_alignment
, wcount
, bytes_remaining
= count
;
643 u32 first_page
, last_page
, pagen
, buffer_pos
;
645 if (bank
->target
->state
!= TARGET_HALTED
)
647 return ERROR_TARGET_NOT_HALTED
;
650 if (at91sam7_info
->cidr
== 0)
652 at91sam7_read_part_info(bank
);
655 if (at91sam7_info
->cidr
== 0)
657 WARNING("Cannot identify target as an AT91SAM");
658 return ERROR_FLASH_OPERATION_FAILED
;
661 if (offset
+ count
> bank
->size
)
662 return ERROR_FLASH_DST_OUT_OF_BANK
;
664 dst_min_alignment
= at91sam7_info
->pagesize
;
666 if (offset
% dst_min_alignment
)
668 WARNING("offset 0x%x breaks required alignment 0x%x", offset
, dst_min_alignment
);
669 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
672 if (at91sam7_info
->cidr_arch
== 0)
673 return ERROR_FLASH_BANK_NOT_PROBED
;
675 first_page
= offset
/dst_min_alignment
;
676 last_page
= CEIL(offset
+ count
, dst_min_alignment
);
678 DEBUG("first_page: %i, last_page: %i, count %i", first_page
, last_page
, count
);
680 /* Configure the flash controller timing */
681 at91sam7_read_clock_info(bank
);
682 at91sam7_set_flash_mode(bank
,FMR_TIMING_FLASH
);
684 for (pagen
=first_page
; pagen
<last_page
; pagen
++) {
685 if (bytes_remaining
<dst_min_alignment
)
686 count
= bytes_remaining
;
688 count
= dst_min_alignment
;
689 bytes_remaining
-= count
;
691 /* Write one block to the PageWriteBuffer */
692 buffer_pos
= (pagen
-first_page
)*dst_min_alignment
;
693 wcount
= CEIL(count
,4);
694 target
->type
->write_memory(target
, bank
->base
, 4, wcount
, buffer
+buffer_pos
);
696 /* Send Write Page command to Flash Controller */
697 if (at91sam7_flash_command(bank
, WP
, pagen
) != ERROR_OK
)
699 return ERROR_FLASH_OPERATION_FAILED
;
701 DEBUG("Write page number:%i", pagen
);
708 int at91sam7_probe(struct flash_bank_s
*bank
)
710 /* we can't probe on an at91sam7
711 * if this is an at91sam7, it has the configured flash
713 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
715 if (at91sam7_info
->cidr
== 0)
717 at91sam7_read_part_info(bank
);
720 if (at91sam7_info
->cidr
== 0)
722 WARNING("Cannot identify target as an AT91SAM");
723 return ERROR_FLASH_OPERATION_FAILED
;
729 int at91sam7_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
732 at91sam7_flash_bank_t
*at91sam7_info
= bank
->driver_priv
;
734 at91sam7_read_part_info(bank
);
736 if (at91sam7_info
->cidr
== 0)
738 printed
= snprintf(buf
, buf_size
, "Cannot identify target as an AT91SAM\n");
741 return ERROR_FLASH_OPERATION_FAILED
;
744 printed
= snprintf(buf
, buf_size
, "\nat91sam7 information: Chip is %s\n",at91sam7_info
->target_name
);
748 printed
= snprintf(buf
, buf_size
, "cidr: 0x%8.8x, arch: 0x%4.4x, eproc: %s, version:0x%3.3x, flashsize: 0x%8.8x\n", at91sam7_info
->cidr
, at91sam7_info
->cidr_arch
, EPROC
[at91sam7_info
->cidr_eproc
], at91sam7_info
->cidr_version
, bank
->size
);
752 printed
= snprintf(buf
, buf_size
, "master clock(estimated): %ikHz \n", at91sam7_info
->mck_freq
/ 1000);
756 if (at91sam7_info
->num_lockbits
>0) {
757 printed
= snprintf(buf
, buf_size
, "pagesize: %i, lockbits: %i 0x%4.4x, pages in lock region: %i \n", at91sam7_info
->pagesize
, at91sam7_info
->num_lockbits
, at91sam7_info
->lockbits
,at91sam7_info
->num_pages
/at91sam7_info
->num_lockbits
);
762 printed
= snprintf(buf
, buf_size
, "securitybit: %i, nvmbits: 0x%1.1x\n", at91sam7_info
->securitybit
, at91sam7_info
->nvmbits
);
770 * On AT91SAM7S: When the gpnmv bits are set with
771 * > at91sam7 gpnvm 0 bitnr set
772 * the changes are not visible in the flash controller status register MC_FSR
773 * until the processor has been reset.
774 * On the Olimex board this requires a power cycle.
775 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
776 * The maximum number of write/erase cycles for Non Volatile Memory bits is 100. This includes
777 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
779 int at91sam7_handle_gpnvm_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
786 at91sam7_flash_bank_t
*at91sam7_info
;
790 command_print(cmd_ctx
, "at91sam7 gpnvm <num> <bit> <set|clear>");
794 bank
= get_flash_bank_by_num(strtoul(args
[0], NULL
, 0));
800 command_print(cmd_ctx
, "flash bank '#%s' is out of bounds", args
[0]);
804 at91sam7_info
= bank
->driver_priv
;
806 if (bank
->target
->state
!= TARGET_HALTED
)
808 return ERROR_TARGET_NOT_HALTED
;
811 if (at91sam7_info
->cidr
== 0)
813 at91sam7_read_part_info(bank
);
816 if (at91sam7_info
->cidr
== 0)
818 WARNING("Cannot identify target as an AT91SAM");
819 return ERROR_FLASH_OPERATION_FAILED
;
822 if ((bit
<0) || (at91sam7_info
->num_nvmbits
<= bit
))
824 command_print(cmd_ctx
, "gpnvm bit '#%s' is out of bounds for target %s", args
[1],at91sam7_info
->target_name
);
828 if (strcmp(value
, "set") == 0)
832 else if (strcmp(value
, "clear") == 0)
838 command_print(cmd_ctx
, "usage: at91sam7 gpnvm <num> <bit> <set|clear>");
842 /* Configure the flash controller timing */
843 at91sam7_read_clock_info(bank
);
844 at91sam7_set_flash_mode(bank
,FMR_TIMING_NVBITS
);
846 if (at91sam7_flash_command(bank
, flashcmd
, (u16
)(bit
)) != ERROR_OK
)
848 return ERROR_FLASH_OPERATION_FAILED
;
851 status
= at91sam7_get_flash_status(bank
);
852 DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n",flashcmd
,bit
,status
);
853 at91sam7_info
->nvmbits
= (status
>>8)&((1<<at91sam7_info
->num_nvmbits
)-1);
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