1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "replacements.h"
33 #include "algorithm.h"
34 #include "binarybuffer.h"
41 int cfi_register_commands(struct command_context_s
*cmd_ctx
);
42 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
43 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
);
44 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
45 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
46 int cfi_probe(struct flash_bank_s
*bank
);
47 int cfi_auto_probe(struct flash_bank_s
*bank
);
48 int cfi_protect_check(struct flash_bank_s
*bank
);
49 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
51 int cfi_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
53 #define CFI_MAX_BUS_WIDTH 4
54 #define CFI_MAX_CHIP_WIDTH 4
56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
57 #define CFI_MAX_INTEL_CODESIZE 256
59 flash_driver_t cfi_flash
=
62 .register_commands
= cfi_register_commands
,
63 .flash_bank_command
= cfi_flash_bank_command
,
65 .protect
= cfi_protect
,
68 .auto_probe
= cfi_auto_probe
,
69 .erase_check
= default_flash_blank_check
,
70 .protect_check
= cfi_protect_check
,
74 cfi_unlock_addresses_t cfi_unlock_addresses
[] =
76 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
77 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
80 /* CFI fixups foward declarations */
81 void cfi_fixup_0002_erase_regions(flash_bank_t
*flash
, void *param
);
82 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*flash
, void *param
);
83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*flash
, void *param
);
85 /* fixup after identifying JEDEC manufactuer and ID */
86 cfi_fixup_t cfi_jedec_fixups
[] = {
87 {CFI_MFR_SST
, 0x00D4, cfi_fixup_non_cfi
, NULL
},
88 {CFI_MFR_SST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
89 {CFI_MFR_SST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
90 {CFI_MFR_SST
, 0x00D7, cfi_fixup_non_cfi
, NULL
},
91 {CFI_MFR_SST
, 0x2780, cfi_fixup_non_cfi
, NULL
},
92 {CFI_MFR_ST
, 0x00D5, cfi_fixup_non_cfi
, NULL
},
93 {CFI_MFR_ST
, 0x00D6, cfi_fixup_non_cfi
, NULL
},
94 {CFI_MFR_AMD
, 0x2223, cfi_fixup_non_cfi
, NULL
},
95 {CFI_MFR_AMD
, 0x22ab, cfi_fixup_non_cfi
, NULL
},
96 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_non_cfi
, NULL
},
97 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_non_cfi
, NULL
},
98 {CFI_MFR_MX
, 0x225b, cfi_fixup_non_cfi
, NULL
},
99 {CFI_MFR_AMD
, 0x225b, cfi_fixup_non_cfi
, NULL
},
103 /* fixup after reading cmdset 0002 primary query table */
104 cfi_fixup_t cfi_0002_fixups
[] = {
105 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
106 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
107 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
108 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
109 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
110 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_atmel_reversed_erase_regions
, NULL
},
111 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
112 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
113 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
114 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
115 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
119 /* fixup after reading cmdset 0001 primary query table */
120 cfi_fixup_t cfi_0001_fixups
[] = {
124 void cfi_fixup(flash_bank_t
*bank
, cfi_fixup_t
*fixups
)
126 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
129 for (f
= fixups
; f
->fixup
; f
++)
131 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
132 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
134 f
->fixup(bank
, f
->param
);
139 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
140 __inline__ u32
flash_address(flash_bank_t
*bank
, int sector
, u32 offset
)
142 /* while the sector list isn't built, only accesses to sector 0 work */
144 return bank
->base
+ offset
* bank
->bus_width
;
149 LOG_ERROR("BUG: sector list not yet built");
152 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
157 void cfi_command(flash_bank_t
*bank
, u8 cmd
, u8
*cmd_buf
)
161 /* clear whole buffer, to ensure bits that exceed the bus_width
164 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
167 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
169 for (i
= bank
->bus_width
; i
> 0; i
--)
171 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
176 for (i
= 1; i
<= bank
->bus_width
; i
++)
178 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
183 /* read unsigned 8-bit value from the bank
184 * flash banks are expected to be made of similar chips
185 * the query result should be the same for all
187 u8
cfi_query_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
189 target_t
*target
= bank
->target
;
190 u8 data
[CFI_MAX_BUS_WIDTH
];
192 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
194 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
197 return data
[bank
->bus_width
- 1];
200 /* read unsigned 8-bit value from the bank
201 * in case of a bank made of multiple chips,
202 * the individual values are ORed
204 u8
cfi_get_u8(flash_bank_t
*bank
, int sector
, u32 offset
)
206 target_t
*target
= bank
->target
;
207 u8 data
[CFI_MAX_BUS_WIDTH
];
210 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
212 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
214 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
222 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
223 value
|= data
[bank
->bus_width
- 1 - i
];
229 u16
cfi_query_u16(flash_bank_t
*bank
, int sector
, u32 offset
)
231 target_t
*target
= bank
->target
;
232 u8 data
[CFI_MAX_BUS_WIDTH
* 2];
234 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
236 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
237 return data
[0] | data
[bank
->bus_width
] << 8;
239 return data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
242 u32
cfi_query_u32(flash_bank_t
*bank
, int sector
, u32 offset
)
244 target_t
*target
= bank
->target
;
245 u8 data
[CFI_MAX_BUS_WIDTH
* 4];
247 target
->type
->read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
249 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
250 return data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
252 return data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
253 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
256 void cfi_intel_clear_status_register(flash_bank_t
*bank
)
258 target_t
*target
= bank
->target
;
261 if (target
->state
!= TARGET_HALTED
)
263 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
267 cfi_command(bank
, 0x50, command
);
268 target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
271 u8
cfi_intel_wait_status_busy(flash_bank_t
*bank
, int timeout
)
275 while ((!((status
= cfi_get_u8(bank
, 0, 0x0)) & 0x80)) && (timeout
-- > 0))
277 LOG_DEBUG("status: 0x%x", status
);
281 /* mask out bit 0 (reserved) */
282 status
= status
& 0xfe;
284 LOG_DEBUG("status: 0x%x", status
);
286 if ((status
& 0x80) != 0x80)
288 LOG_ERROR("timeout while waiting for WSM to become ready");
290 else if (status
!= 0x80)
292 LOG_ERROR("status register: 0x%x", status
);
294 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
296 LOG_ERROR("Program suspended");
298 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
300 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
302 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
304 LOG_ERROR("Block Erase Suspended");
306 cfi_intel_clear_status_register(bank
);
312 int cfi_spansion_wait_status_busy(flash_bank_t
*bank
, int timeout
)
314 u8 status
, oldstatus
;
316 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
319 status
= cfi_get_u8(bank
, 0, 0x0);
320 if ((status
^ oldstatus
) & 0x40) {
322 oldstatus
= cfi_get_u8(bank
, 0, 0x0);
323 status
= cfi_get_u8(bank
, 0, 0x0);
324 if ((status
^ oldstatus
) & 0x40) {
325 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
326 return(ERROR_FLASH_OPERATION_FAILED
);
328 LOG_DEBUG("status: 0x%x", status
);
333 LOG_DEBUG("status: 0x%x", status
);
339 } while (timeout
-- > 0);
341 LOG_ERROR("timeout, status: 0x%x", status
);
343 return(ERROR_FLASH_BUSY
);
346 int cfi_read_intel_pri_ext(flash_bank_t
*bank
)
349 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
350 cfi_intel_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_intel_pri_ext_t
));
351 target_t
*target
= bank
->target
;
354 cfi_info
->pri_ext
= pri_ext
;
356 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
357 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
358 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
360 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
362 cfi_command(bank
, 0xf0, command
);
363 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
367 cfi_command(bank
, 0xff, command
);
368 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
372 LOG_ERROR("Could not read bank flash bank information");
373 return ERROR_FLASH_BANK_INVALID
;
376 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
377 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
379 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
381 pri_ext
->feature_support
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5);
382 pri_ext
->suspend_cmd_support
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
383 pri_ext
->blk_status_reg_mask
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa);
385 LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
387 pri_ext
->vcc_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc);
388 pri_ext
->vpp_optimal
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd);
390 LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
391 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
392 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
394 pri_ext
->num_protection_fields
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe);
395 if (pri_ext
->num_protection_fields
!= 1)
397 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
400 pri_ext
->prot_reg_addr
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf);
401 pri_ext
->fact_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11);
402 pri_ext
->user_prot_reg_size
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12);
404 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
409 int cfi_read_spansion_pri_ext(flash_bank_t
*bank
)
412 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
413 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
414 target_t
*target
= bank
->target
;
417 cfi_info
->pri_ext
= pri_ext
;
419 pri_ext
->pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
420 pri_ext
->pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
421 pri_ext
->pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
423 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
425 cfi_command(bank
, 0xf0, command
);
426 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
430 LOG_ERROR("Could not read spansion bank information");
431 return ERROR_FLASH_BANK_INVALID
;
434 pri_ext
->major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
435 pri_ext
->minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
437 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
439 pri_ext
->SiliconRevision
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
440 pri_ext
->EraseSuspend
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
441 pri_ext
->BlkProt
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
442 pri_ext
->TmpBlkUnprotect
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
443 pri_ext
->BlkProtUnprot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9);
444 pri_ext
->SimultaneousOps
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10);
445 pri_ext
->BurstMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11);
446 pri_ext
->PageMode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12);
447 pri_ext
->VppMin
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13);
448 pri_ext
->VppMax
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14);
449 pri_ext
->TopBottom
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15);
451 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
452 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
454 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
455 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
457 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
460 LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
461 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
462 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
464 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
466 /* default values for implementation specific workarounds */
467 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
468 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
469 pri_ext
->_reversed_geometry
= 0;
474 int cfi_read_atmel_pri_ext(flash_bank_t
*bank
)
477 cfi_atmel_pri_ext_t atmel_pri_ext
;
478 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
479 cfi_spansion_pri_ext_t
*pri_ext
= malloc(sizeof(cfi_spansion_pri_ext_t
));
480 target_t
*target
= bank
->target
;
483 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
484 * but a different primary extended query table.
485 * We read the atmel table, and prepare a valid AMD/Spansion query table.
488 memset(pri_ext
, 0, sizeof(cfi_spansion_pri_ext_t
));
490 cfi_info
->pri_ext
= pri_ext
;
492 atmel_pri_ext
.pri
[0] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0);
493 atmel_pri_ext
.pri
[1] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1);
494 atmel_pri_ext
.pri
[2] = cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2);
496 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
498 cfi_command(bank
, 0xf0, command
);
499 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
503 LOG_ERROR("Could not read atmel bank information");
504 return ERROR_FLASH_BANK_INVALID
;
507 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
508 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
509 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
511 atmel_pri_ext
.major_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3);
512 atmel_pri_ext
.minor_version
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4);
514 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
516 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
517 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
519 atmel_pri_ext
.features
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5);
520 atmel_pri_ext
.bottom_boot
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6);
521 atmel_pri_ext
.burst_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7);
522 atmel_pri_ext
.page_mode
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8);
524 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
525 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
527 if (atmel_pri_ext
.features
& 0x02)
528 pri_ext
->EraseSuspend
= 2;
530 if (atmel_pri_ext
.bottom_boot
)
531 pri_ext
->TopBottom
= 2;
533 pri_ext
->TopBottom
= 3;
535 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
536 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
541 int cfi_read_0002_pri_ext(flash_bank_t
*bank
)
543 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
545 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
547 return cfi_read_atmel_pri_ext(bank
);
551 return cfi_read_spansion_pri_ext(bank
);
555 int cfi_spansion_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
558 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
559 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
561 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
565 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
566 pri_ext
->pri
[1], pri_ext
->pri
[2],
567 pri_ext
->major_version
, pri_ext
->minor_version
);
571 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
572 (pri_ext
->SiliconRevision
) >> 2,
573 (pri_ext
->SiliconRevision
) & 0x03);
577 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
578 pri_ext
->EraseSuspend
,
583 printed
= snprintf(buf
, buf_size
, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
584 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
585 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
590 int cfi_intel_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
593 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
594 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
596 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
600 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
604 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
608 printed
= snprintf(buf
, buf_size
, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
609 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
610 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
614 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
619 int cfi_register_commands(struct command_context_s
*cmd_ctx
)
621 /*command_t *cfi_cmd = */
622 register_command(cmd_ctx
, NULL
, "cfi", NULL
, COMMAND_ANY
, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
624 register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
625 "print part id of cfi flash bank <num>");
630 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
632 int cfi_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
634 cfi_flash_bank_t
*cfi_info
;
639 LOG_WARNING("incomplete flash_bank cfi configuration");
640 return ERROR_FLASH_BANK_INVALID
;
643 if ((strtoul(args
[4], NULL
, 0) > CFI_MAX_CHIP_WIDTH
)
644 || (strtoul(args
[3], NULL
, 0) > CFI_MAX_BUS_WIDTH
))
646 LOG_ERROR("chip and bus width have to specified in bytes");
647 return ERROR_FLASH_BANK_INVALID
;
650 cfi_info
= malloc(sizeof(cfi_flash_bank_t
));
651 cfi_info
->probed
= 0;
652 bank
->driver_priv
= cfi_info
;
654 cfi_info
->write_algorithm
= NULL
;
656 cfi_info
->x16_as_x8
= 0;
657 cfi_info
->jedec_probe
= 0;
658 cfi_info
->not_cfi
= 0;
660 for (i
= 6; i
< argc
; i
++)
662 if (strcmp(args
[i
], "x16_as_x8") == 0)
664 cfi_info
->x16_as_x8
= 1;
666 else if (strcmp(args
[i
], "jedec_probe") == 0)
668 cfi_info
->jedec_probe
= 1;
672 cfi_info
->write_algorithm
= NULL
;
674 /* bank wasn't probed yet */
675 cfi_info
->qry
[0] = -1;
680 int cfi_intel_erase(struct flash_bank_s
*bank
, int first
, int last
)
683 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
684 target_t
*target
= bank
->target
;
688 cfi_intel_clear_status_register(bank
);
690 for (i
= first
; i
<= last
; i
++)
692 cfi_command(bank
, 0x20, command
);
693 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
698 cfi_command(bank
, 0xd0, command
);
699 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
704 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == 0x80)
705 bank
->sectors
[i
].is_erased
= 1;
708 cfi_command(bank
, 0xff, command
);
709 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
714 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
715 return ERROR_FLASH_OPERATION_FAILED
;
719 cfi_command(bank
, 0xff, command
);
720 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
724 int cfi_spansion_erase(struct flash_bank_s
*bank
, int first
, int last
)
727 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
728 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
729 target_t
*target
= bank
->target
;
733 for (i
= first
; i
<= last
; i
++)
735 cfi_command(bank
, 0xaa, command
);
736 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
741 cfi_command(bank
, 0x55, command
);
742 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
747 cfi_command(bank
, 0x80, command
);
748 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
753 cfi_command(bank
, 0xaa, command
);
754 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
759 cfi_command(bank
, 0x55, command
);
760 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
765 cfi_command(bank
, 0x30, command
);
766 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
771 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
772 bank
->sectors
[i
].is_erased
= 1;
775 cfi_command(bank
, 0xf0, command
);
776 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
781 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i
, bank
->base
);
782 return ERROR_FLASH_OPERATION_FAILED
;
786 cfi_command(bank
, 0xf0, command
);
787 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
790 int cfi_erase(struct flash_bank_s
*bank
, int first
, int last
)
792 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
794 if (bank
->target
->state
!= TARGET_HALTED
)
796 LOG_ERROR("Target not halted");
797 return ERROR_TARGET_NOT_HALTED
;
800 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
802 return ERROR_FLASH_SECTOR_INVALID
;
805 if (cfi_info
->qry
[0] != 'Q')
806 return ERROR_FLASH_BANK_NOT_PROBED
;
808 switch(cfi_info
->pri_id
)
812 return cfi_intel_erase(bank
, first
, last
);
815 return cfi_spansion_erase(bank
, first
, last
);
818 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
825 int cfi_intel_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
828 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
829 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
830 target_t
*target
= bank
->target
;
835 /* if the device supports neither legacy lock/unlock (bit 3) nor
836 * instant individual block locking (bit 5).
838 if (!(pri_ext
->feature_support
& 0x28))
839 return ERROR_FLASH_OPERATION_FAILED
;
841 cfi_intel_clear_status_register(bank
);
843 for (i
= first
; i
<= last
; i
++)
845 cfi_command(bank
, 0x60, command
);
846 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
847 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
853 cfi_command(bank
, 0x01, command
);
854 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
855 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
859 bank
->sectors
[i
].is_protected
= 1;
863 cfi_command(bank
, 0xd0, command
);
864 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank
, i
, 0x0), target_buffer_get_u32(target
, command
));
865 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
869 bank
->sectors
[i
].is_protected
= 0;
872 /* instant individual block locking doesn't require reading of the status register */
873 if (!(pri_ext
->feature_support
& 0x20))
875 /* Clear lock bits operation may take up to 1.4s */
876 cfi_intel_wait_status_busy(bank
, 1400);
881 /* read block lock bit, to verify status */
882 cfi_command(bank
, 0x90, command
);
883 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
887 block_status
= cfi_get_u8(bank
, i
, 0x2);
889 if ((block_status
& 0x1) != set
)
891 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
892 cfi_command(bank
, 0x70, command
);
893 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
897 cfi_intel_wait_status_busy(bank
, 10);
900 return ERROR_FLASH_OPERATION_FAILED
;
910 /* if the device doesn't support individual block lock bits set/clear,
911 * all blocks have been unlocked in parallel, so we set those that should be protected
913 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
915 for (i
= 0; i
< bank
->num_sectors
; i
++)
917 if (bank
->sectors
[i
].is_protected
== 1)
919 cfi_intel_clear_status_register(bank
);
921 cfi_command(bank
, 0x60, command
);
922 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
927 cfi_command(bank
, 0x01, command
);
928 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, i
, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
933 cfi_intel_wait_status_busy(bank
, 100);
938 cfi_command(bank
, 0xff, command
);
939 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
942 int cfi_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
944 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
946 if (bank
->target
->state
!= TARGET_HALTED
)
948 LOG_ERROR("Target not halted");
949 return ERROR_TARGET_NOT_HALTED
;
952 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
954 return ERROR_FLASH_SECTOR_INVALID
;
957 if (cfi_info
->qry
[0] != 'Q')
958 return ERROR_FLASH_BANK_NOT_PROBED
;
960 switch(cfi_info
->pri_id
)
964 cfi_intel_protect(bank
, set
, first
, last
);
967 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
974 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
975 static void cfi_add_byte(struct flash_bank_s
*bank
, u8
*word
, u8 byte
)
977 /* target_t *target = bank->target; */
982 * The data to flash must not be changed in endian! We write a bytestrem in
983 * target byte order already. Only the control and status byte lane of the flash
984 * WSM is interpreted by the CPU in different ways, when read a u16 or u32
985 * word (data seems to be in the upper or lower byte lane for u16 accesses).
989 if (target
->endianness
== TARGET_LITTLE_ENDIAN
)
993 for (i
= 0; i
< bank
->bus_width
- 1; i
++)
994 word
[i
] = word
[i
+ 1];
995 word
[bank
->bus_width
- 1] = byte
;
1001 for (i
= bank
->bus_width
- 1; i
> 0; i
--)
1002 word
[i
] = word
[i
- 1];
1008 /* Convert code image to target endian */
1009 /* FIXME create general block conversion fcts in target.c?) */
1010 static void cfi_fix_code_endian(target_t
*target
, u8
*dest
, const u32
*src
, u32 count
)
1013 for (i
=0; i
< count
; i
++)
1015 target_buffer_set_u32(target
, dest
, *src
);
1021 u32
cfi_command_val(flash_bank_t
*bank
, u8 cmd
)
1023 target_t
*target
= bank
->target
;
1025 u8 buf
[CFI_MAX_BUS_WIDTH
];
1026 cfi_command(bank
, cmd
, buf
);
1027 switch (bank
->bus_width
)
1033 return target_buffer_get_u16(target
, buf
);
1036 return target_buffer_get_u32(target
, buf
);
1039 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1044 int cfi_intel_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1046 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1047 target_t
*target
= bank
->target
;
1048 reg_param_t reg_params
[7];
1049 armv4_5_algorithm_t armv4_5_info
;
1050 working_area_t
*source
;
1051 u32 buffer_size
= 32768;
1052 u32 write_command_val
, busy_pattern_val
, error_pattern_val
;
1054 /* algorithm register usage:
1055 * r0: source address (in RAM)
1056 * r1: target address (in Flash)
1058 * r3: flash write command
1059 * r4: status byte (returned to host)
1060 * r5: busy test pattern
1061 * r6: error test pattern
1064 static const u32 word_32_code
[] = {
1065 0xe4904004, /* loop: ldr r4, [r0], #4 */
1066 0xe5813000, /* str r3, [r1] */
1067 0xe5814000, /* str r4, [r1] */
1068 0xe5914000, /* busy: ldr r4, [r1] */
1069 0xe0047005, /* and r7, r4, r5 */
1070 0xe1570005, /* cmp r7, r5 */
1071 0x1afffffb, /* bne busy */
1072 0xe1140006, /* tst r4, r6 */
1073 0x1a000003, /* bne done */
1074 0xe2522001, /* subs r2, r2, #1 */
1075 0x0a000001, /* beq done */
1076 0xe2811004, /* add r1, r1 #4 */
1077 0xeafffff2, /* b loop */
1078 0xeafffffe /* done: b -2 */
1081 static const u32 word_16_code
[] = {
1082 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1083 0xe1c130b0, /* strh r3, [r1] */
1084 0xe1c140b0, /* strh r4, [r1] */
1085 0xe1d140b0, /* busy ldrh r4, [r1] */
1086 0xe0047005, /* and r7, r4, r5 */
1087 0xe1570005, /* cmp r7, r5 */
1088 0x1afffffb, /* bne busy */
1089 0xe1140006, /* tst r4, r6 */
1090 0x1a000003, /* bne done */
1091 0xe2522001, /* subs r2, r2, #1 */
1092 0x0a000001, /* beq done */
1093 0xe2811002, /* add r1, r1 #2 */
1094 0xeafffff2, /* b loop */
1095 0xeafffffe /* done: b -2 */
1098 static const u32 word_8_code
[] = {
1099 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1100 0xe5c13000, /* strb r3, [r1] */
1101 0xe5c14000, /* strb r4, [r1] */
1102 0xe5d14000, /* busy ldrb r4, [r1] */
1103 0xe0047005, /* and r7, r4, r5 */
1104 0xe1570005, /* cmp r7, r5 */
1105 0x1afffffb, /* bne busy */
1106 0xe1140006, /* tst r4, r6 */
1107 0x1a000003, /* bne done */
1108 0xe2522001, /* subs r2, r2, #1 */
1109 0x0a000001, /* beq done */
1110 0xe2811001, /* add r1, r1 #1 */
1111 0xeafffff2, /* b loop */
1112 0xeafffffe /* done: b -2 */
1114 u8 target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1115 const u32
*target_code_src
;
1116 int target_code_size
;
1117 int retval
= ERROR_OK
;
1120 cfi_intel_clear_status_register(bank
);
1122 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1123 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1124 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1126 /* If we are setting up the write_algorith, we need target_code_src */
1127 /* if not we only need target_code_size. */
1129 /* However, we don't want to create multiple code paths, so we */
1130 /* do the unecessary evaluation of target_code_src, which the */
1131 /* compiler will probably nicely optimize away if not needed */
1133 /* prepare algorithm code for target endian */
1134 switch (bank
->bus_width
)
1137 target_code_src
= word_8_code
;
1138 target_code_size
= sizeof(word_8_code
);
1141 target_code_src
= word_16_code
;
1142 target_code_size
= sizeof(word_16_code
);
1145 target_code_src
= word_32_code
;
1146 target_code_size
= sizeof(word_32_code
);
1149 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1150 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1153 /* flash write code */
1154 if (!cfi_info
->write_algorithm
)
1156 if ( target_code_size
> sizeof(target_code
) )
1158 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1159 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1161 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1163 /* Get memory for block write handler */
1164 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1165 if (retval
!= ERROR_OK
)
1167 LOG_WARNING("No working area available, can't do block memory writes");
1168 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1171 /* write algorithm code to working area */
1172 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1173 if (retval
!= ERROR_OK
)
1175 LOG_ERROR("Unable to write block write code to target");
1180 /* Get a workspace buffer for the data to flash starting with 32k size.
1181 Half size until buffer would be smaller 256 Bytem then fail back */
1182 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1183 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1186 if (buffer_size
<= 256)
1188 LOG_WARNING("no large enough working area available, can't do block memory writes");
1189 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1194 /* setup algo registers */
1195 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1196 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1197 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1198 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1199 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1200 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1201 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1203 /* prepare command and status register patterns */
1204 write_command_val
= cfi_command_val(bank
, 0x40);
1205 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1206 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1208 LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source
->address
, buffer_size
);
1210 /* Programming main loop */
1213 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1216 if((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1221 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1222 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1223 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1225 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1226 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1227 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1229 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count
, address
);
1231 /* Execute algorithm, assume breakpoint for last instruction */
1232 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 7, reg_params
,
1233 cfi_info
->write_algorithm
->address
,
1234 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(u32
),
1235 10000, /* 10s should be enough for max. 32k of data */
1238 /* On failure try a fall back to direct word writes */
1239 if (retval
!= ERROR_OK
)
1241 cfi_intel_clear_status_register(bank
);
1242 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1243 retval
= ERROR_FLASH_OPERATION_FAILED
;
1244 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1245 /* FIXME To allow fall back or recovery, we must save the actual status
1246 somewhere, so that a higher level code can start recovery. */
1250 /* Check return value from algo code */
1251 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1254 /* read status register (outputs debug inforation) */
1255 cfi_intel_wait_status_busy(bank
, 100);
1256 cfi_intel_clear_status_register(bank
);
1257 retval
= ERROR_FLASH_OPERATION_FAILED
;
1261 buffer
+= thisrun_count
;
1262 address
+= thisrun_count
;
1263 count
-= thisrun_count
;
1266 /* free up resources */
1269 target_free_working_area(target
, source
);
1271 if (cfi_info
->write_algorithm
)
1273 target_free_working_area(target
, cfi_info
->write_algorithm
);
1274 cfi_info
->write_algorithm
= NULL
;
1277 destroy_reg_param(®_params
[0]);
1278 destroy_reg_param(®_params
[1]);
1279 destroy_reg_param(®_params
[2]);
1280 destroy_reg_param(®_params
[3]);
1281 destroy_reg_param(®_params
[4]);
1282 destroy_reg_param(®_params
[5]);
1283 destroy_reg_param(®_params
[6]);
1288 int cfi_spansion_write_block(struct flash_bank_s
*bank
, u8
*buffer
, u32 address
, u32 count
)
1290 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1291 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1292 target_t
*target
= bank
->target
;
1293 reg_param_t reg_params
[10];
1294 armv4_5_algorithm_t armv4_5_info
;
1295 working_area_t
*source
;
1296 u32 buffer_size
= 32768;
1298 int retval
, retvaltemp
;
1299 int exit_code
= ERROR_OK
;
1301 /* input parameters - */
1302 /* R0 = source address */
1303 /* R1 = destination address */
1304 /* R2 = number of writes */
1305 /* R3 = flash write command */
1306 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1307 /* output parameters - */
1308 /* R5 = 0x80 ok 0x00 bad */
1309 /* temp registers - */
1310 /* R6 = value read from flash to test status */
1311 /* R7 = holding register */
1312 /* unlock registers - */
1313 /* R8 = unlock1_addr */
1314 /* R9 = unlock1_cmd */
1315 /* R10 = unlock2_addr */
1316 /* R11 = unlock2_cmd */
1318 static const u32 word_32_code
[] = {
1319 /* 00008100 <sp_32_code>: */
1320 0xe4905004, /* ldr r5, [r0], #4 */
1321 0xe5889000, /* str r9, [r8] */
1322 0xe58ab000, /* str r11, [r10] */
1323 0xe5883000, /* str r3, [r8] */
1324 0xe5815000, /* str r5, [r1] */
1325 0xe1a00000, /* nop */
1327 /* 00008110 <sp_32_busy>: */
1328 0xe5916000, /* ldr r6, [r1] */
1329 0xe0257006, /* eor r7, r5, r6 */
1330 0xe0147007, /* ands r7, r4, r7 */
1331 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1332 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1333 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1334 0xe5916000, /* ldr r6, [r1] */
1335 0xe0257006, /* eor r7, r5, r6 */
1336 0xe0147007, /* ands r7, r4, r7 */
1337 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1338 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1339 0x1a000004, /* bne 8154 <sp_32_done> */
1341 /* 00008140 <sp_32_cont>: */
1342 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1343 0x03a05080, /* moveq r5, #128 ; 0x80 */
1344 0x0a000001, /* beq 8154 <sp_32_done> */
1345 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1346 0xeaffffe8, /* b 8100 <sp_32_code> */
1348 /* 00008154 <sp_32_done>: */
1349 0xeafffffe /* b 8154 <sp_32_done> */
1352 static const u32 word_16_code
[] = {
1353 /* 00008158 <sp_16_code>: */
1354 0xe0d050b2, /* ldrh r5, [r0], #2 */
1355 0xe1c890b0, /* strh r9, [r8] */
1356 0xe1cab0b0, /* strh r11, [r10] */
1357 0xe1c830b0, /* strh r3, [r8] */
1358 0xe1c150b0, /* strh r5, [r1] */
1359 0xe1a00000, /* nop (mov r0,r0) */
1361 /* 00008168 <sp_16_busy>: */
1362 0xe1d160b0, /* ldrh r6, [r1] */
1363 0xe0257006, /* eor r7, r5, r6 */
1364 0xe0147007, /* ands r7, r4, r7 */
1365 0x0a000007, /* beq 8198 <sp_16_cont> */
1366 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1367 0x0afffff9, /* beq 8168 <sp_16_busy> */
1368 0xe1d160b0, /* ldrh r6, [r1] */
1369 0xe0257006, /* eor r7, r5, r6 */
1370 0xe0147007, /* ands r7, r4, r7 */
1371 0x0a000001, /* beq 8198 <sp_16_cont> */
1372 0xe3a05000, /* mov r5, #0 ; 0x0 */
1373 0x1a000004, /* bne 81ac <sp_16_done> */
1375 /* 00008198 <sp_16_cont>: */
1376 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1377 0x03a05080, /* moveq r5, #128 ; 0x80 */
1378 0x0a000001, /* beq 81ac <sp_16_done> */
1379 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1380 0xeaffffe8, /* b 8158 <sp_16_code> */
1382 /* 000081ac <sp_16_done>: */
1383 0xeafffffe /* b 81ac <sp_16_done> */
1386 static const u32 word_8_code
[] = {
1387 /* 000081b0 <sp_16_code_end>: */
1388 0xe4d05001, /* ldrb r5, [r0], #1 */
1389 0xe5c89000, /* strb r9, [r8] */
1390 0xe5cab000, /* strb r11, [r10] */
1391 0xe5c83000, /* strb r3, [r8] */
1392 0xe5c15000, /* strb r5, [r1] */
1393 0xe1a00000, /* nop (mov r0,r0) */
1395 /* 000081c0 <sp_8_busy>: */
1396 0xe5d16000, /* ldrb r6, [r1] */
1397 0xe0257006, /* eor r7, r5, r6 */
1398 0xe0147007, /* ands r7, r4, r7 */
1399 0x0a000007, /* beq 81f0 <sp_8_cont> */
1400 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1401 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1402 0xe5d16000, /* ldrb r6, [r1] */
1403 0xe0257006, /* eor r7, r5, r6 */
1404 0xe0147007, /* ands r7, r4, r7 */
1405 0x0a000001, /* beq 81f0 <sp_8_cont> */
1406 0xe3a05000, /* mov r5, #0 ; 0x0 */
1407 0x1a000004, /* bne 8204 <sp_8_done> */
1409 /* 000081f0 <sp_8_cont>: */
1410 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1411 0x03a05080, /* moveq r5, #128 ; 0x80 */
1412 0x0a000001, /* beq 8204 <sp_8_done> */
1413 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1414 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1416 /* 00008204 <sp_8_done>: */
1417 0xeafffffe /* b 8204 <sp_8_done> */
1420 armv4_5_info
.common_magic
= ARMV4_5_COMMON_MAGIC
;
1421 armv4_5_info
.core_mode
= ARMV4_5_MODE_SVC
;
1422 armv4_5_info
.core_state
= ARMV4_5_STATE_ARM
;
1424 /* flash write code */
1425 if (!cfi_info
->write_algorithm
)
1428 int target_code_size
;
1431 /* convert bus-width dependent algorithm code to correct endiannes */
1432 switch (bank
->bus_width
)
1436 target_code_size
= sizeof(word_8_code
);
1440 target_code_size
= sizeof(word_16_code
);
1444 target_code_size
= sizeof(word_32_code
);
1447 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1448 return ERROR_FLASH_OPERATION_FAILED
;
1450 target_code
= malloc(target_code_size
);
1451 cfi_fix_code_endian(target
, target_code
, src
, target_code_size
/ 4);
1453 /* allocate working area */
1454 retval
=target_alloc_working_area(target
, target_code_size
,
1455 &cfi_info
->write_algorithm
);
1456 if (retval
!= ERROR_OK
)
1462 /* write algorithm code to working area */
1463 if((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1464 target_code_size
, target_code
)) != ERROR_OK
)
1472 /* the following code still assumes target code is fixed 24*4 bytes */
1474 while (target_alloc_working_area(target
, buffer_size
, &source
) != ERROR_OK
)
1477 if (buffer_size
<= 256)
1479 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1480 if (cfi_info
->write_algorithm
)
1481 target_free_working_area(target
, cfi_info
->write_algorithm
);
1483 LOG_WARNING("not enough working area available, can't do block memory writes");
1484 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1488 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1489 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1490 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1491 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1492 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1493 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1494 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1495 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1496 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1497 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1501 u32 thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1503 retvaltemp
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1505 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1506 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1507 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1508 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1509 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1510 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1511 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1512 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1513 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1515 retval
= target
->type
->run_algorithm(target
, 0, NULL
, 10, reg_params
,
1516 cfi_info
->write_algorithm
->address
,
1517 cfi_info
->write_algorithm
->address
+ ((24 * 4) - 4),
1518 10000, &armv4_5_info
);
1520 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1522 if ((retval
!= ERROR_OK
) || (retvaltemp
!= ERROR_OK
) || status
!= 0x80)
1524 LOG_DEBUG("status: 0x%x", status
);
1525 exit_code
= ERROR_FLASH_OPERATION_FAILED
;
1529 buffer
+= thisrun_count
;
1530 address
+= thisrun_count
;
1531 count
-= thisrun_count
;
1534 target_free_working_area(target
, source
);
1536 destroy_reg_param(®_params
[0]);
1537 destroy_reg_param(®_params
[1]);
1538 destroy_reg_param(®_params
[2]);
1539 destroy_reg_param(®_params
[3]);
1540 destroy_reg_param(®_params
[4]);
1541 destroy_reg_param(®_params
[5]);
1542 destroy_reg_param(®_params
[6]);
1543 destroy_reg_param(®_params
[7]);
1544 destroy_reg_param(®_params
[8]);
1545 destroy_reg_param(®_params
[9]);
1550 int cfi_intel_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1553 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1554 target_t
*target
= bank
->target
;
1557 cfi_intel_clear_status_register(bank
);
1558 cfi_command(bank
, 0x40, command
);
1559 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1564 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1569 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != 0x80)
1571 cfi_command(bank
, 0xff, command
);
1572 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1577 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1578 return ERROR_FLASH_OPERATION_FAILED
;
1584 int cfi_intel_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1587 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1588 target_t
*target
= bank
->target
;
1591 /* Calculate buffer size and boundary mask */
1592 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1593 u32 buffermask
= buffersize
-1;
1596 /* Check for valid range */
1597 if (address
& buffermask
)
1599 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1600 return ERROR_FLASH_OPERATION_FAILED
;
1602 switch(bank
->chip_width
)
1604 case 4 : bufferwsize
= buffersize
/ 4; break;
1605 case 2 : bufferwsize
= buffersize
/ 2; break;
1606 case 1 : bufferwsize
= buffersize
; break;
1608 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1609 return ERROR_FLASH_OPERATION_FAILED
;
1612 /* Check for valid size */
1613 if (wordcount
> bufferwsize
)
1615 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1616 return ERROR_FLASH_OPERATION_FAILED
;
1619 /* Write to flash buffer */
1620 cfi_intel_clear_status_register(bank
);
1622 /* Initiate buffer operation _*/
1623 cfi_command(bank
, 0xE8, command
);
1624 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1628 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1630 cfi_command(bank
, 0xff, command
);
1631 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1636 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank
->base
, address
);
1637 return ERROR_FLASH_OPERATION_FAILED
;
1640 /* Write buffer wordcount-1 and data words */
1641 cfi_command(bank
, bufferwsize
-1, command
);
1642 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1647 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1652 /* Commit write operation */
1653 cfi_command(bank
, 0xd0, command
);
1654 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1658 if (cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
)) != 0x80)
1660 cfi_command(bank
, 0xff, command
);
1661 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1666 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank
->base
, address
);
1667 return ERROR_FLASH_OPERATION_FAILED
;
1673 int cfi_spansion_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1676 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1677 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1678 target_t
*target
= bank
->target
;
1681 cfi_command(bank
, 0xaa, command
);
1682 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1687 cfi_command(bank
, 0x55, command
);
1688 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1693 cfi_command(bank
, 0xa0, command
);
1694 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1699 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1704 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1706 cfi_command(bank
, 0xf0, command
);
1707 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1712 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank
->base
, address
);
1713 return ERROR_FLASH_OPERATION_FAILED
;
1719 int cfi_spansion_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1722 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1723 target_t
*target
= bank
->target
;
1725 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
1727 /* Calculate buffer size and boundary mask */
1728 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1729 u32 buffermask
= buffersize
-1;
1732 /* Check for valid range */
1733 if (address
& buffermask
)
1735 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1736 return ERROR_FLASH_OPERATION_FAILED
;
1738 switch(bank
->chip_width
)
1740 case 4 : bufferwsize
= buffersize
/ 4; break;
1741 case 2 : bufferwsize
= buffersize
/ 2; break;
1742 case 1 : bufferwsize
= buffersize
; break;
1744 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1745 return ERROR_FLASH_OPERATION_FAILED
;
1748 /* Check for valid size */
1749 if (wordcount
> bufferwsize
)
1751 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount
, buffersize
);
1752 return ERROR_FLASH_OPERATION_FAILED
;
1756 cfi_command(bank
, 0xaa, command
);
1757 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1762 cfi_command(bank
, 0x55, command
);
1763 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1768 // Buffer load command
1769 cfi_command(bank
, 0x25, command
);
1770 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1775 /* Write buffer wordcount-1 and data words */
1776 cfi_command(bank
, bufferwsize
-1, command
);
1777 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1782 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1787 /* Commit write operation */
1788 cfi_command(bank
, 0x29, command
);
1789 if((retval
= target
->type
->write_memory(target
, address
, bank
->bus_width
, 1, command
)) != ERROR_OK
)
1794 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1796 cfi_command(bank
, 0xf0, command
);
1797 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
1802 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank
->base
, address
, bufferwsize
);
1803 return ERROR_FLASH_OPERATION_FAILED
;
1809 int cfi_write_word(struct flash_bank_s
*bank
, u8
*word
, u32 address
)
1811 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1813 switch(cfi_info
->pri_id
)
1817 return cfi_intel_write_word(bank
, word
, address
);
1820 return cfi_spansion_write_word(bank
, word
, address
);
1823 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1827 return ERROR_FLASH_OPERATION_FAILED
;
1830 int cfi_write_words(struct flash_bank_s
*bank
, u8
*word
, u32 wordcount
, u32 address
)
1832 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1834 switch(cfi_info
->pri_id
)
1838 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1841 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1844 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1848 return ERROR_FLASH_OPERATION_FAILED
;
1851 int cfi_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
1853 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
1854 target_t
*target
= bank
->target
;
1855 u32 address
= bank
->base
+ offset
; /* address of first byte to be programmed */
1856 u32 write_p
, copy_p
;
1857 int align
; /* number of unaligned bytes */
1858 int blk_count
; /* number of bus_width bytes for block copy */
1859 u8 current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
1863 if (bank
->target
->state
!= TARGET_HALTED
)
1865 LOG_ERROR("Target not halted");
1866 return ERROR_TARGET_NOT_HALTED
;
1869 if (offset
+ count
> bank
->size
)
1870 return ERROR_FLASH_DST_OUT_OF_BANK
;
1872 if (cfi_info
->qry
[0] != 'Q')
1873 return ERROR_FLASH_BANK_NOT_PROBED
;
1875 /* start at the first byte of the first word (bus_width size) */
1876 write_p
= address
& ~(bank
->bus_width
- 1);
1877 if ((align
= address
- write_p
) != 0)
1879 LOG_INFO("Fixup %d unaligned head bytes", align
);
1881 for (i
= 0; i
< bank
->bus_width
; i
++)
1882 current_word
[i
] = 0;
1885 /* copy bytes before the first write address */
1886 for (i
= 0; i
< align
; ++i
, ++copy_p
)
1889 if((retval
= target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1893 cfi_add_byte(bank
, current_word
, byte
);
1896 /* add bytes from the buffer */
1897 for (; (i
< bank
->bus_width
) && (count
> 0); i
++)
1899 cfi_add_byte(bank
, current_word
, *buffer
++);
1904 /* if the buffer is already finished, copy bytes after the last write address */
1905 for (; (count
== 0) && (i
< bank
->bus_width
); ++i
, ++copy_p
)
1908 if((retval
= target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
1912 cfi_add_byte(bank
, current_word
, byte
);
1915 retval
= cfi_write_word(bank
, current_word
, write_p
);
1916 if (retval
!= ERROR_OK
)
1921 /* handle blocks of bus_size aligned bytes */
1922 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
1923 switch(cfi_info
->pri_id
)
1925 /* try block writes (fails without working area) */
1928 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
1931 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
1934 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1935 retval
= ERROR_FLASH_OPERATION_FAILED
;
1938 if (retval
== ERROR_OK
)
1940 /* Increment pointers and decrease count on succesful block write */
1941 buffer
+= blk_count
;
1942 write_p
+= blk_count
;
1947 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
1949 u32 buffersize
= 1UL << cfi_info
->max_buf_write_size
;
1950 u32 buffermask
= buffersize
-1;
1953 switch(bank
->chip_width
)
1955 case 4 : bufferwsize
= buffersize
/ 4; break;
1956 case 2 : bufferwsize
= buffersize
/ 2; break;
1957 case 1 : bufferwsize
= buffersize
; break;
1959 LOG_ERROR("Unsupported chip width %d", bank
->chip_width
);
1960 return ERROR_FLASH_OPERATION_FAILED
;
1963 /* fall back to memory writes */
1964 while (count
>= bank
->bus_width
)
1967 if ((write_p
& 0xff) == 0)
1969 LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p
, count
);
1972 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
1974 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
1975 if (retval
== ERROR_OK
)
1977 buffer
+= buffersize
;
1978 write_p
+= buffersize
;
1979 count
-= buffersize
;
1983 /* try the slow way? */
1986 for (i
= 0; i
< bank
->bus_width
; i
++)
1987 current_word
[i
] = 0;
1989 for (i
= 0; i
< bank
->bus_width
; i
++)
1991 cfi_add_byte(bank
, current_word
, *buffer
++);
1994 retval
= cfi_write_word(bank
, current_word
, write_p
);
1995 if (retval
!= ERROR_OK
)
1998 write_p
+= bank
->bus_width
;
1999 count
-= bank
->bus_width
;
2007 /* return to read array mode, so we can read from flash again for padding */
2008 cfi_command(bank
, 0xf0, current_word
);
2009 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2013 cfi_command(bank
, 0xff, current_word
);
2014 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2019 /* handle unaligned tail bytes */
2022 LOG_INFO("Fixup %d unaligned tail bytes", count
);
2025 for (i
= 0; i
< bank
->bus_width
; i
++)
2026 current_word
[i
] = 0;
2028 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); ++i
, ++copy_p
)
2030 cfi_add_byte(bank
, current_word
, *buffer
++);
2033 for (; i
< bank
->bus_width
; ++i
, ++copy_p
)
2036 if((retval
= target
->type
->read_memory(target
, copy_p
, 1, 1, &byte
)) != ERROR_OK
)
2040 cfi_add_byte(bank
, current_word
, byte
);
2042 retval
= cfi_write_word(bank
, current_word
, write_p
);
2043 if (retval
!= ERROR_OK
)
2047 /* return to read array mode */
2048 cfi_command(bank
, 0xf0, current_word
);
2049 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2053 cfi_command(bank
, 0xff, current_word
);
2054 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, current_word
);
2057 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t
*bank
, void *param
)
2059 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2060 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2062 pri_ext
->_reversed_geometry
= 1;
2065 void cfi_fixup_0002_erase_regions(flash_bank_t
*bank
, void *param
)
2068 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2069 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2071 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2073 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2075 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2077 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2080 swap
= cfi_info
->erase_region_info
[i
];
2081 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2082 cfi_info
->erase_region_info
[j
] = swap
;
2087 void cfi_fixup_0002_unlock_addresses(flash_bank_t
*bank
, void *param
)
2089 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2090 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2091 cfi_unlock_addresses_t
*unlock_addresses
= param
;
2093 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2094 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2097 int cfi_probe(struct flash_bank_s
*bank
)
2099 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2100 target_t
*target
= bank
->target
;
2102 int num_sectors
= 0;
2106 u32 unlock1
= 0x555;
2107 u32 unlock2
= 0x2aa;
2110 if (bank
->target
->state
!= TARGET_HALTED
)
2112 LOG_ERROR("Target not halted");
2113 return ERROR_TARGET_NOT_HALTED
;
2116 cfi_info
->probed
= 0;
2118 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2119 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2121 if (cfi_info
->jedec_probe
)
2127 /* switch to read identifier codes mode ("AUTOSELECT") */
2128 cfi_command(bank
, 0xaa, command
);
2129 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2133 cfi_command(bank
, 0x55, command
);
2134 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2138 cfi_command(bank
, 0x90, command
);
2139 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2144 if (bank
->chip_width
== 1)
2146 u8 manufacturer
, device_id
;
2147 if((retval
= target_read_u8(target
, bank
->base
+ 0x0, &manufacturer
)) != ERROR_OK
)
2151 if((retval
= target_read_u8(target
, bank
->base
+ 0x1, &device_id
)) != ERROR_OK
)
2155 cfi_info
->manufacturer
= manufacturer
;
2156 cfi_info
->device_id
= device_id
;
2158 else if (bank
->chip_width
== 2)
2160 if((retval
= target_read_u16(target
, bank
->base
+ 0x0, &cfi_info
->manufacturer
)) != ERROR_OK
)
2164 if((retval
= target_read_u16(target
, bank
->base
+ 0x2, &cfi_info
->device_id
)) != ERROR_OK
)
2170 /* switch back to read array mode */
2171 cfi_command(bank
, 0xf0, command
);
2172 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2176 cfi_command(bank
, 0xff, command
);
2177 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2182 cfi_fixup(bank
, cfi_jedec_fixups
);
2184 /* query only if this is a CFI compatible flash,
2185 * otherwise the relevant info has already been filled in
2187 if (cfi_info
->not_cfi
== 0)
2189 /* enter CFI query mode
2190 * according to JEDEC Standard No. 68.01,
2191 * a single bus sequence with address = 0x55, data = 0x98 should put
2192 * the device into CFI query mode.
2194 * SST flashes clearly violate this, and we will consider them incompatbile for now
2196 cfi_command(bank
, 0x98, command
);
2197 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2202 cfi_info
->qry
[0] = cfi_query_u8(bank
, 0, 0x10);
2203 cfi_info
->qry
[1] = cfi_query_u8(bank
, 0, 0x11);
2204 cfi_info
->qry
[2] = cfi_query_u8(bank
, 0, 0x12);
2206 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2208 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2210 cfi_command(bank
, 0xf0, command
);
2211 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2215 cfi_command(bank
, 0xff, command
);
2216 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2220 LOG_ERROR("Could not probe bank");
2221 return ERROR_FLASH_BANK_INVALID
;
2224 cfi_info
->pri_id
= cfi_query_u16(bank
, 0, 0x13);
2225 cfi_info
->pri_addr
= cfi_query_u16(bank
, 0, 0x15);
2226 cfi_info
->alt_id
= cfi_query_u16(bank
, 0, 0x17);
2227 cfi_info
->alt_addr
= cfi_query_u16(bank
, 0, 0x19);
2229 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2231 cfi_info
->vcc_min
= cfi_query_u8(bank
, 0, 0x1b);
2232 cfi_info
->vcc_max
= cfi_query_u8(bank
, 0, 0x1c);
2233 cfi_info
->vpp_min
= cfi_query_u8(bank
, 0, 0x1d);
2234 cfi_info
->vpp_max
= cfi_query_u8(bank
, 0, 0x1e);
2235 cfi_info
->word_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x1f);
2236 cfi_info
->buf_write_timeout_typ
= cfi_query_u8(bank
, 0, 0x20);
2237 cfi_info
->block_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x21);
2238 cfi_info
->chip_erase_timeout_typ
= cfi_query_u8(bank
, 0, 0x22);
2239 cfi_info
->word_write_timeout_max
= cfi_query_u8(bank
, 0, 0x23);
2240 cfi_info
->buf_write_timeout_max
= cfi_query_u8(bank
, 0, 0x24);
2241 cfi_info
->block_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x25);
2242 cfi_info
->chip_erase_timeout_max
= cfi_query_u8(bank
, 0, 0x26);
2244 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2245 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2246 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2247 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2248 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2249 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2250 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2251 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2252 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2253 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2254 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2256 cfi_info
->dev_size
= cfi_query_u8(bank
, 0, 0x27);
2257 cfi_info
->interface_desc
= cfi_query_u16(bank
, 0, 0x28);
2258 cfi_info
->max_buf_write_size
= cfi_query_u16(bank
, 0, 0x2a);
2259 cfi_info
->num_erase_regions
= cfi_query_u8(bank
, 0, 0x2c);
2261 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2263 if (((1 << cfi_info
->dev_size
) * bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2265 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank
->size
, 1 << cfi_info
->dev_size
);
2268 if (cfi_info
->num_erase_regions
)
2270 cfi_info
->erase_region_info
= malloc(4 * cfi_info
->num_erase_regions
);
2271 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2273 cfi_info
->erase_region_info
[i
] = cfi_query_u32(bank
, 0, 0x2d + (4 * i
));
2274 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i
, (cfi_info
->erase_region_info
[i
] & 0xffff) + 1, (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2279 cfi_info
->erase_region_info
= NULL
;
2282 /* We need to read the primary algorithm extended query table before calculating
2283 * the sector layout to be able to apply fixups
2285 switch(cfi_info
->pri_id
)
2287 /* Intel command set (standard and extended) */
2290 cfi_read_intel_pri_ext(bank
);
2292 /* AMD/Spansion, Atmel, ... command set */
2294 cfi_read_0002_pri_ext(bank
);
2297 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2301 /* return to read array mode
2302 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2304 cfi_command(bank
, 0xf0, command
);
2305 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2309 cfi_command(bank
, 0xff, command
);
2310 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2316 /* apply fixups depending on the primary command set */
2317 switch(cfi_info
->pri_id
)
2319 /* Intel command set (standard and extended) */
2322 cfi_fixup(bank
, cfi_0001_fixups
);
2324 /* AMD/Spansion, Atmel, ... command set */
2326 cfi_fixup(bank
, cfi_0002_fixups
);
2329 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2333 if (cfi_info
->num_erase_regions
== 0)
2335 /* a device might have only one erase block, spanning the whole device */
2336 bank
->num_sectors
= 1;
2337 bank
->sectors
= malloc(sizeof(flash_sector_t
));
2339 bank
->sectors
[sector
].offset
= 0x0;
2340 bank
->sectors
[sector
].size
= bank
->size
;
2341 bank
->sectors
[sector
].is_erased
= -1;
2342 bank
->sectors
[sector
].is_protected
= -1;
2346 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2348 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2351 bank
->num_sectors
= num_sectors
;
2352 bank
->sectors
= malloc(sizeof(flash_sector_t
) * num_sectors
);
2354 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2357 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2359 bank
->sectors
[sector
].offset
= offset
;
2360 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2361 offset
+= bank
->sectors
[sector
].size
;
2362 bank
->sectors
[sector
].is_erased
= -1;
2363 bank
->sectors
[sector
].is_protected
= -1;
2369 cfi_info
->probed
= 1;
2374 int cfi_auto_probe(struct flash_bank_s
*bank
)
2376 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2377 if (cfi_info
->probed
)
2379 return cfi_probe(bank
);
2383 int cfi_intel_protect_check(struct flash_bank_s
*bank
)
2386 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2387 cfi_intel_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2388 target_t
*target
= bank
->target
;
2389 u8 command
[CFI_MAX_BUS_WIDTH
];
2392 /* check if block lock bits are supported on this device */
2393 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2394 return ERROR_FLASH_OPERATION_FAILED
;
2396 cfi_command(bank
, 0x90, command
);
2397 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, 0x55), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2402 for (i
= 0; i
< bank
->num_sectors
; i
++)
2404 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2406 if (block_status
& 1)
2407 bank
->sectors
[i
].is_protected
= 1;
2409 bank
->sectors
[i
].is_protected
= 0;
2412 cfi_command(bank
, 0xff, command
);
2413 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2416 int cfi_spansion_protect_check(struct flash_bank_s
*bank
)
2419 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2420 cfi_spansion_pri_ext_t
*pri_ext
= cfi_info
->pri_ext
;
2421 target_t
*target
= bank
->target
;
2425 cfi_command(bank
, 0xaa, command
);
2426 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2431 cfi_command(bank
, 0x55, command
);
2432 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock2
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2437 cfi_command(bank
, 0x90, command
);
2438 if((retval
= target
->type
->write_memory(target
, flash_address(bank
, 0, pri_ext
->_unlock1
), bank
->bus_width
, 1, command
)) != ERROR_OK
)
2443 for (i
= 0; i
< bank
->num_sectors
; i
++)
2445 u8 block_status
= cfi_get_u8(bank
, i
, 0x2);
2447 if (block_status
& 1)
2448 bank
->sectors
[i
].is_protected
= 1;
2450 bank
->sectors
[i
].is_protected
= 0;
2453 cfi_command(bank
, 0xf0, command
);
2454 return target
->type
->write_memory(target
, flash_address(bank
, 0, 0x0), bank
->bus_width
, 1, command
);
2457 int cfi_protect_check(struct flash_bank_s
*bank
)
2459 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2461 if (bank
->target
->state
!= TARGET_HALTED
)
2463 LOG_ERROR("Target not halted");
2464 return ERROR_TARGET_NOT_HALTED
;
2467 if (cfi_info
->qry
[0] != 'Q')
2468 return ERROR_FLASH_BANK_NOT_PROBED
;
2470 switch(cfi_info
->pri_id
)
2474 return cfi_intel_protect_check(bank
);
2477 return cfi_spansion_protect_check(bank
);
2480 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2487 int cfi_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
2490 cfi_flash_bank_t
*cfi_info
= bank
->driver_priv
;
2492 if (cfi_info
->qry
[0] == (char)-1)
2494 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2498 if (cfi_info
->not_cfi
== 0)
2499 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2501 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2503 buf_size
-= printed
;
2505 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2506 cfi_info
->manufacturer
, cfi_info
->device_id
);
2508 buf_size
-= printed
;
2510 if (cfi_info
->not_cfi
== 0)
2512 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2514 buf_size
-= printed
;
2516 printed
= snprintf(buf
, buf_size
, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2517 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2518 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2519 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2520 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2522 buf_size
-= printed
;
2524 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2525 1 << cfi_info
->word_write_timeout_typ
,
2526 1 << cfi_info
->buf_write_timeout_typ
,
2527 1 << cfi_info
->block_erase_timeout_typ
,
2528 1 << cfi_info
->chip_erase_timeout_typ
);
2530 buf_size
-= printed
;
2532 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2533 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2534 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2535 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2536 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2538 buf_size
-= printed
;
2540 printed
= snprintf(buf
, buf_size
, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2541 1 << cfi_info
->dev_size
,
2542 cfi_info
->interface_desc
,
2543 1 << cfi_info
->max_buf_write_size
);
2545 buf_size
-= printed
;
2547 switch(cfi_info
->pri_id
)
2551 cfi_intel_info(bank
, buf
, buf_size
);
2554 cfi_spansion_info(bank
, buf
, buf_size
);
2557 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
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