1 /***************************************************************************
2 * Copyright (C) 2008 by *
3 * Karl RobinSod <karl.robinsod@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
21 /***************************************************************************
22 * There are some things to notice
24 * You need to unprotect flash sectors each time you connect the OpenOCD
25 * Dumping 1MB takes about 60 Seconds
26 * Full erase (sectors 0-22 inclusive) takes 2-4 seconds
27 * Writing 1MB takes 88 seconds
29 ***************************************************************************/
34 #include "replacements.h"
41 #include "binarybuffer.h"
48 #define LOAD_TIMER_ERASE 0
49 #define LOAD_TIMER_WRITE 1
51 #define FLASH_PAGE_SIZE 512
53 /* LPC288X control registers */
54 #define DBGU_CIDR 0x8000507C
55 /* LPC288X flash registers */
56 #define F_CTRL 0x80102000 /* Flash control register R/W 0x5 */
57 #define F_STAT 0x80102004 /* Flash status register RO 0x45 */
58 #define F_PROG_TIME 0x80102008 /* Flash program time register R/W 0 */
59 #define F_WAIT 0x80102010 /* Flash read wait state register R/W 0xC004 */
60 #define F_CLK_TIME 0x8010201C /* Flash clock divider for 66 kHz generation R/W 0 */
61 #define F_INTEN_CLR 0x80102FD8 /* Clear interrupt enable bits WO - */
62 #define F_INTEN_SET 0x80102FDC /* Set interrupt enable bits WO - */
63 #define F_INT_STAT 0x80102FE0 /* Interrupt status bits RO 0 */
64 #define F_INTEN 0x80102FE4 /* Interrupt enable bits RO 0 */
65 #define F_INT_CLR 0x80102FE8 /* Clear interrupt status bits WO */
66 #define F_INT_SET 0x80102FEC /* Set interrupt status bits WO - */
67 #define FLASH_PD 0x80005030 /* Allows turning off the Flash memory for power savings. R/W 1*/
68 #define FLASH_INIT 0x80005034 /* Monitors Flash readiness, such as recovery from Power Down mode. R/W -*/
72 #define FC_FUNC 0x0002
74 #define FC_RD_LATCH 0x0020
75 #define FC_PROTECT 0x0080
76 #define FC_SET_DATA 0x0400
77 #define FC_RSSL 0x0800
78 #define FC_PROG_REQ 0x1000
79 #define FC_CLR_BUF 0x4000
80 #define FC_LOAD_REQ 0x8000
82 #define FS_DONE 0x0001
83 #define FS_PROGGNT 0x0002
87 #define FPT_TIME_MASK 0x7FFF
89 #define FPT_ENABLE 0x8000
91 #define FW_WAIT_STATES_MASK 0x00FF
92 #define FW_SET_MASK 0xC000
95 #define FCT_CLK_DIV_MASK 0x0FFF
97 int lpc288x_register_commands(struct command_context_s
*cmd_ctx
);
98 int lpc288x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
);
99 int lpc288x_erase(struct flash_bank_s
*bank
, int first
, int last
);
100 int lpc288x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
);
101 int lpc288x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
);
102 int lpc288x_probe(struct flash_bank_s
*bank
);
103 int lpc288x_auto_probe(struct flash_bank_s
*bank
);
104 int lpc288x_erase_check(struct flash_bank_s
*bank
);
105 int lpc288x_protect_check(struct flash_bank_s
*bank
);
106 int lpc288x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
);
107 void lpc288x_set_flash_mode(flash_bank_t
*bank
, u8 flashplane
, int mode
);
108 u32
lpc288x_wait_status_busy(flash_bank_t
*bank
, int timeout
);
109 void lpc288x_load_timer(int erase
, struct target_s
*target
);
110 void lpc288x_set_flash_clk(struct flash_bank_s
*bank
);
111 u32
lpc288x_system_ready(struct flash_bank_s
*bank
);
112 int lpc288x_handle_part_id_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
114 flash_driver_t lpc288x_flash
=
117 .register_commands
= lpc288x_register_commands
,
118 .flash_bank_command
= lpc288x_flash_bank_command
,
119 .erase
= lpc288x_erase
,
120 .protect
= lpc288x_protect
,
121 .write
= lpc288x_write
,
122 .probe
= lpc288x_probe
,
123 .auto_probe
= lpc288x_probe
,
124 .erase_check
= lpc288x_erase_check
,
125 .protect_check
= lpc288x_protect_check
,
129 int lpc288x_register_commands(struct command_context_s
*cmd_ctx
)
134 u32
lpc288x_wait_status_busy(flash_bank_t
*bank
, int timeout
)
137 target_t
*target
= bank
->target
;
142 target_read_u32(target
, F_STAT
, &status
);
143 }while (((status
& FS_DONE
) == 0) && timeout
);
147 LOG_DEBUG("Timedout!");
148 return ERROR_FLASH_OPERATION_FAILED
;
153 /* Read device id register and fill in driver info structure */
154 int lpc288x_read_part_info(struct flash_bank_s
*bank
)
156 lpc288x_flash_bank_t
*lpc288x_info
= bank
->driver_priv
;
157 target_t
*target
= bank
->target
;
163 if (lpc288x_info
->cidr
== 0x0102100A)
164 return ERROR_OK
; /* already probed, multiple probes may cause memory leak, not allowed */
166 /* Read and parse chip identification register */
167 target_read_u32(target
, DBGU_CIDR
, &cidr
);
169 if (cidr
!= 0x0102100A)
171 LOG_WARNING("Cannot identify target as an LPC288X (%08X)",cidr
);
172 return ERROR_FLASH_OPERATION_FAILED
;
175 lpc288x_info
->cidr
= cidr
;
176 lpc288x_info
->sector_size_break
= 0x000F0000;
177 lpc288x_info
->target_name
= "LPC288x";
179 /* setup the sector info... */
181 bank
->num_sectors
= 23;
182 bank
->sectors
= malloc(sizeof(flash_sector_t
) * 23);
184 for (i
= 0; i
< 15; i
++)
186 bank
->sectors
[i
].offset
= offset
;
187 bank
->sectors
[i
].size
= 64 * 1024;
188 offset
+= bank
->sectors
[i
].size
;
189 bank
->sectors
[i
].is_erased
= -1;
190 bank
->sectors
[i
].is_protected
= 1;
192 for (i
= 15; i
< 23; i
++)
194 bank
->sectors
[i
].offset
= offset
;
195 bank
->sectors
[i
].size
= 8 * 1024;
196 offset
+= bank
->sectors
[i
].size
;
197 bank
->sectors
[i
].is_erased
= -1;
198 bank
->sectors
[i
].is_protected
= 1;
204 int lpc288x_protect_check(struct flash_bank_s
*bank
)
209 /* flash_bank LPC288x 0 0 0 0 <target#> <cclk> */
210 int lpc288x_flash_bank_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
, struct flash_bank_s
*bank
)
212 lpc288x_flash_bank_t
*lpc288x_info
;
216 LOG_WARNING("incomplete flash_bank LPC288x configuration");
217 return ERROR_FLASH_BANK_INVALID
;
220 lpc288x_info
= malloc(sizeof(lpc288x_flash_bank_t
));
221 bank
->driver_priv
= lpc288x_info
;
223 /* part wasn't probed for info yet */
224 lpc288x_info
->cidr
= 0;
225 lpc288x_info
->cclk
= strtoul(args
[6], NULL
, 0);
230 /* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1.
231 * This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%.
233 * 12000000/66000 = 182
235 void lpc288x_set_flash_clk(struct flash_bank_s
*bank
)
238 lpc288x_flash_bank_t
*lpc288x_info
= bank
->driver_priv
;
239 clk_time
= (lpc288x_info
->cclk
/ 66000) / 3;
240 target_write_u32(bank
->target
, F_CTRL
, FC_CS
| FC_WEN
);
241 target_write_u32(bank
->target
, F_CLK_TIME
, clk_time
);
244 /* AHB tcyc (in ns) 83 ns
245 * LOAD_TIMER_ERASE FPT_TIME = ((400,000,000 / AHB tcyc (in ns)) - 2) / 512
246 * = 9412 (9500) (AN10548 9375)
247 * LOAD_TIMER_WRITE FPT_TIME = ((1,000,000 / AHB tcyc (in ns)) - 2) / 512
248 * = 23 (75) (AN10548 72 - is this wrong?)
249 * TODO: Sort out timing calcs ;) */
250 void lpc288x_load_timer(int erase
, struct target_s
*target
)
252 if (erase
== LOAD_TIMER_ERASE
)
254 target_write_u32(target
, F_PROG_TIME
, FPT_ENABLE
| 9500);
258 target_write_u32(target
, F_PROG_TIME
, FPT_ENABLE
| 75);
262 u32
lpc288x_system_ready(struct flash_bank_s
*bank
)
264 lpc288x_flash_bank_t
*lpc288x_info
= bank
->driver_priv
;
265 if (lpc288x_info
->cidr
== 0)
267 return ERROR_FLASH_BANK_NOT_PROBED
;
270 if (bank
->target
->state
!= TARGET_HALTED
)
272 LOG_ERROR("Target not halted");
273 return ERROR_TARGET_NOT_HALTED
;
278 int lpc288x_erase_check(struct flash_bank_s
*bank
)
280 u32 status
= lpc288x_system_ready(bank
); /* probed? halted? */
281 if (status
!= ERROR_OK
)
283 LOG_INFO("Processor not halted/not probed");
290 int lpc288x_erase(struct flash_bank_s
*bank
, int first
, int last
)
294 target_t
*target
= bank
->target
;
296 status
= lpc288x_system_ready(bank
); /* probed? halted? */
297 if (status
!= ERROR_OK
)
302 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
304 LOG_INFO("Bad sector range");
305 return ERROR_FLASH_SECTOR_INVALID
;
308 /* Configure the flash controller timing */
309 lpc288x_set_flash_clk(bank
);
311 for (sector
= first
; sector
<= last
; sector
++)
313 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
315 return ERROR_FLASH_OPERATION_FAILED
;
318 lpc288x_load_timer(LOAD_TIMER_ERASE
,target
);
320 target_write_u32(target
, bank
->sectors
[sector
].offset
, 0x00);
322 target_write_u32(target
, F_CTRL
, FC_PROG_REQ
| FC_PROTECT
| FC_CS
);
324 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
326 return ERROR_FLASH_OPERATION_FAILED
;
331 int lpc288x_write(struct flash_bank_s
*bank
, u8
*buffer
, u32 offset
, u32 count
)
333 u8 page_buffer
[FLASH_PAGE_SIZE
];
334 u32 i
, status
, source_offset
,dest_offset
;
335 target_t
*target
= bank
->target
;
336 u32 bytes_remaining
= count
;
337 u32 first_sector
, last_sector
, sector
, page
;
339 /* probed? halted? */
340 status
= lpc288x_system_ready(bank
);
341 if (status
!= ERROR_OK
)
346 /* Initialise search indices */
347 first_sector
= last_sector
= 0xffffffff;
349 /* validate the write range... */
350 for (i
= 0; i
< bank
->num_sectors
; i
++)
352 if ((offset
>= bank
->sectors
[i
].offset
) &&
353 (offset
< (bank
->sectors
[i
].offset
+ bank
->sectors
[i
].size
)) &&
354 (first_sector
== 0xffffffff))
357 /* all writes must start on a sector boundary... */
358 if (offset
% bank
->sectors
[i
].size
)
360 LOG_INFO("offset 0x%x breaks required alignment 0x%x", offset
, bank
->sectors
[i
].size
);
361 return ERROR_FLASH_DST_BREAKS_ALIGNMENT
;
364 if (((offset
+ count
) > bank
->sectors
[i
].offset
) &&
365 ((offset
+ count
) <= (bank
->sectors
[i
].offset
+ bank
->sectors
[i
].size
)) &&
366 (last_sector
== 0xffffffff))
373 if (first_sector
== 0xffffffff || last_sector
== 0xffffffff)
375 LOG_INFO("Range check failed %x %x", offset
, count
);
376 return ERROR_FLASH_DST_OUT_OF_BANK
;
379 /* Configure the flash controller timing */
380 lpc288x_set_flash_clk(bank
);
382 /* initialise the offsets */
386 for (sector
= first_sector
; sector
<= last_sector
; sector
++)
388 for (page
= 0; page
< bank
->sectors
[sector
].size
/ FLASH_PAGE_SIZE
; page
++)
390 if (bytes_remaining
== 0)
393 memset(page_buffer
, 0xFF, FLASH_PAGE_SIZE
);
395 else if (bytes_remaining
< FLASH_PAGE_SIZE
)
397 count
= bytes_remaining
;
398 memset(page_buffer
, 0xFF, FLASH_PAGE_SIZE
);
399 memcpy(page_buffer
, &buffer
[source_offset
], count
);
403 count
= FLASH_PAGE_SIZE
;
404 memcpy(page_buffer
, &buffer
[source_offset
], count
);
407 /* Wait for flash to become ready */
408 if (lpc288x_wait_status_busy(bank
, 1000) != ERROR_OK
)
410 return ERROR_FLASH_OPERATION_FAILED
;
413 /* fill flash data latches with 1's */
414 target_write_u32(target
, F_CTRL
, FC_CS
| FC_SET_DATA
| FC_WEN
| FC_FUNC
);
416 target_write_u32(target
, F_CTRL
, FC_CS
| FC_WEN
| FC_FUNC
);
417 /*would be better to use the clean target_write_buffer() interface but
418 * it seems not to be a LOT slower....
419 * bulk_write_memory() is no quicker :(*/
421 if (target
->type
->write_memory(target
, offset
+ dest_offset
, 4, 128, page_buffer
) != ERROR_OK
)
423 LOG_ERROR("Write failed s %x p %x", sector
, page
);
424 return ERROR_FLASH_OPERATION_FAILED
;
427 if (target_write_buffer(target
, offset
+ dest_offset
, FLASH_PAGE_SIZE
, page_buffer
) != ERROR_OK
)
429 LOG_INFO("Write to flash buffer failed");
430 return ERROR_FLASH_OPERATION_FAILED
;
433 dest_offset
+= FLASH_PAGE_SIZE
;
434 source_offset
+= count
;
435 bytes_remaining
-= count
;
437 lpc288x_load_timer(LOAD_TIMER_WRITE
, target
);
439 target_write_u32(target
, F_CTRL
, FC_PROG_REQ
| FC_PROTECT
| FC_FUNC
| FC_CS
);
446 int lpc288x_probe(struct flash_bank_s
*bank
)
448 /* we only deal with LPC2888 so flash config is fixed */
449 lpc288x_flash_bank_t
*lpc288x_info
= bank
->driver_priv
;
452 if (lpc288x_info
->cidr
!= 0)
454 return ERROR_OK
; /* already probed */
457 if (bank
->target
->state
!= TARGET_HALTED
)
459 LOG_ERROR("Target not halted");
460 return ERROR_TARGET_NOT_HALTED
;
463 retval
= lpc288x_read_part_info(bank
);
464 if (retval
!= ERROR_OK
)
469 int lpc288x_info(struct flash_bank_s
*bank
, char *buf
, int buf_size
)
471 snprintf(buf
, buf_size
, "lpc288x flash driver");
475 int lpc288x_protect(struct flash_bank_s
*bank
, int set
, int first
, int last
)
477 int lockregion
, status
;
479 target_t
*target
= bank
->target
;
481 /* probed? halted? */
482 status
= lpc288x_system_ready(bank
);
483 if (status
!= ERROR_OK
)
488 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
490 return ERROR_FLASH_SECTOR_INVALID
;
493 /* Configure the flash controller timing */
494 lpc288x_set_flash_clk(bank
);
496 for (lockregion
= first
; lockregion
<= last
; lockregion
++)
500 /* write an odd value to base addy to protect... */
505 /* write an even value to base addy to unprotect... */
508 target_write_u32(target
, bank
->sectors
[lockregion
].offset
, value
);
509 target_write_u32(target
, F_CTRL
, FC_LOAD_REQ
| FC_PROTECT
| FC_WEN
| FC_FUNC
| FC_CS
);
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