1 /***************************************************************************
2 * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
26 #include "time_support.h"
31 static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio
);
32 static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
);
33 static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio
);
34 static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
);
36 static struct mflash_bank
*mflash_bank
;
38 static struct mflash_gpio_drv pxa270_gpio
= {
40 .set_gpio_to_output
= pxa270_set_gpio_to_output
,
41 .set_gpio_output_val
= pxa270_set_gpio_output_val
44 static struct mflash_gpio_drv s3c2440_gpio
= {
46 .set_gpio_to_output
= s3c2440_set_gpio_to_output
,
47 .set_gpio_output_val
= s3c2440_set_gpio_output_val
50 static struct mflash_gpio_drv
*mflash_gpio
[] =
57 #define PXA270_GAFR0_L 0x40E00054
58 #define PXA270_GAFR3_U 0x40E00070
59 #define PXA270_GAFR3_U_RESERVED_BITS 0xfffc0000u
60 #define PXA270_GPDR0 0x40E0000C
61 #define PXA270_GPDR3 0x40E0010C
62 #define PXA270_GPDR3_RESERVED_BITS 0xfe000000u
63 #define PXA270_GPSR0 0x40E00018
64 #define PXA270_GPCR0 0x40E00024
66 static int pxa270_set_gpio_to_output (struct mflash_gpio_num gpio
)
68 uint32_t addr
, value
, mask
;
69 struct target
*target
= mflash_bank
->target
;
72 /* remove alternate function. */
73 mask
= 0x3u
<< (gpio
.num
& 0xF)*2;
75 addr
= PXA270_GAFR0_L
+ (gpio
.num
>> 4) * 4;
77 if ((ret
= target_read_u32(target
, addr
, &value
)) != ERROR_OK
)
81 if (addr
== PXA270_GAFR3_U
)
82 value
&= ~PXA270_GAFR3_U_RESERVED_BITS
;
84 if ((ret
= target_write_u32(target
, addr
, value
)) != ERROR_OK
)
87 /* set direction to output */
88 mask
= 0x1u
<< (gpio
.num
& 0x1F);
90 addr
= PXA270_GPDR0
+ (gpio
.num
>> 5) * 4;
92 if ((ret
= target_read_u32(target
, addr
, &value
)) != ERROR_OK
)
96 if (addr
== PXA270_GPDR3
)
97 value
&= ~PXA270_GPDR3_RESERVED_BITS
;
99 ret
= target_write_u32(target
, addr
, value
);
103 static int pxa270_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
)
105 uint32_t addr
, value
, mask
;
106 struct target
*target
= mflash_bank
->target
;
109 mask
= 0x1u
<< (gpio
.num
& 0x1F);
112 addr
= PXA270_GPSR0
+ (gpio
.num
>> 5) * 4;
114 addr
= PXA270_GPCR0
+ (gpio
.num
>> 5) * 4;
117 if ((ret
= target_read_u32(target
, addr
, &value
)) != ERROR_OK
)
122 ret
= target_write_u32(target
, addr
, value
);
127 #define S3C2440_GPACON 0x56000000
128 #define S3C2440_GPADAT 0x56000004
129 #define S3C2440_GPJCON 0x560000d0
130 #define S3C2440_GPJDAT 0x560000d4
132 static int s3c2440_set_gpio_to_output (struct mflash_gpio_num gpio
)
134 uint32_t data
, mask
, gpio_con
;
135 struct target
*target
= mflash_bank
->target
;
138 if (gpio
.port
[0] >= 'a' && gpio
.port
[0] <= 'h') {
139 gpio_con
= S3C2440_GPACON
+ (gpio
.port
[0] - 'a') * 0x10;
140 } else if (gpio
.port
[0] == 'j') {
141 gpio_con
= S3C2440_GPJCON
;
143 LOG_ERROR("mflash: invalid port %d%s", gpio
.num
, gpio
.port
);
144 return ERROR_INVALID_ARGUMENTS
;
147 ret
= target_read_u32(target
, gpio_con
, &data
);
149 if (ret
== ERROR_OK
) {
150 if (gpio
.port
[0] == 'a') {
151 mask
= 1 << gpio
.num
;
154 mask
= 3 << gpio
.num
* 2;
156 data
|= (1 << gpio
.num
* 2);
159 ret
= target_write_u32(target
, gpio_con
, data
);
164 static int s3c2440_set_gpio_output_val (struct mflash_gpio_num gpio
, uint8_t val
)
166 uint32_t data
, mask
, gpio_dat
;
167 struct target
*target
= mflash_bank
->target
;
170 if (gpio
.port
[0] >= 'a' && gpio
.port
[0] <= 'h') {
171 gpio_dat
= S3C2440_GPADAT
+ (gpio
.port
[0] - 'a') * 0x10;
172 } else if (gpio
.port
[0] == 'j') {
173 gpio_dat
= S3C2440_GPJDAT
;
175 LOG_ERROR("mflash: invalid port %d%s", gpio
.num
, gpio
.port
);
176 return ERROR_INVALID_ARGUMENTS
;
179 ret
= target_read_u32(target
, gpio_dat
, &data
);
181 if (ret
== ERROR_OK
) {
182 mask
= 1 << gpio
.num
;
188 ret
= target_write_u32(target
, gpio_dat
, data
);
193 static int mg_hdrst(uint8_t level
)
195 return mflash_bank
->gpio_drv
->set_gpio_output_val(mflash_bank
->rst_pin
, level
);
198 static int mg_init_gpio (void)
201 struct mflash_gpio_drv
*gpio_drv
= mflash_bank
->gpio_drv
;
203 ret
= gpio_drv
->set_gpio_to_output(mflash_bank
->rst_pin
);
207 ret
= gpio_drv
->set_gpio_output_val(mflash_bank
->rst_pin
, 1);
212 static int mg_dsk_wait(mg_io_type_wait wait
, uint32_t time
)
214 uint8_t status
, error
;
215 struct target
*target
= mflash_bank
->target
;
216 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
220 struct duration bench
;
221 duration_start(&bench
);
225 ret
= target_read_u8(target
, mg_task_reg
+ MG_REG_STATUS
, &status
);
229 if (status
& mg_io_rbit_status_busy
)
231 if (wait
== mg_io_wait_bsy
)
236 case mg_io_wait_not_bsy
:
238 case mg_io_wait_rdy_noerr
:
239 if (status
& mg_io_rbit_status_ready
)
242 case mg_io_wait_drq_noerr
:
243 if (status
& mg_io_rbit_status_data_req
)
250 /* Now we check the error condition! */
251 if (status
& mg_io_rbit_status_error
)
253 ret
= target_read_u8(target
, mg_task_reg
+ MG_REG_ERROR
, &error
);
257 LOG_ERROR("mflash: io error 0x%02x", error
);
265 if (status
& mg_io_rbit_status_ready
)
269 if (status
& mg_io_rbit_status_data_req
)
277 ret
= duration_measure(&bench
);
279 t
= duration_elapsed(&bench
) * 1000.0;
281 LOG_ERROR("mflash: duration measurement failed: %d", ret
);
287 LOG_ERROR("mflash: timeout occured");
288 return ERROR_MG_TIMEOUT
;
291 static int mg_dsk_srst(uint8_t on
)
293 struct target
*target
= mflash_bank
->target
;
294 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
298 if ((ret
= target_read_u8(target
, mg_task_reg
+ MG_REG_DRV_CTRL
, &value
)) != ERROR_OK
)
302 value
|= (mg_io_rbit_devc_srst
);
304 value
&= ~mg_io_rbit_devc_srst
;
307 ret
= target_write_u8(target
, mg_task_reg
+ MG_REG_DRV_CTRL
, value
);
311 static int mg_dsk_io_cmd(uint32_t sect_num
, uint32_t cnt
, uint8_t cmd
)
313 struct target
*target
= mflash_bank
->target
;
314 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
318 ret
= mg_dsk_wait(mg_io_wait_rdy_noerr
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
322 value
= mg_io_rval_dev_drv_master
| mg_io_rval_dev_lba_mode
|((sect_num
>> 24) & 0xf);
324 ret
= target_write_u8(target
, mg_task_reg
+ MG_REG_DRV_HEAD
, value
);
325 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_SECT_CNT
, (uint8_t)cnt
);
326 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_SECT_NUM
, (uint8_t)sect_num
);
327 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_CYL_LOW
, (uint8_t)(sect_num
>> 8));
328 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_CYL_HIGH
, (uint8_t)(sect_num
>> 16));
333 return target_write_u8(target
, mg_task_reg
+ MG_REG_COMMAND
, cmd
);
336 static int mg_dsk_drv_info(void)
338 struct target
*target
= mflash_bank
->target
;
339 uint32_t mg_buff
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
342 if ((ret
= mg_dsk_io_cmd(0, 1, mg_io_cmd_identify
)) != ERROR_OK
)
345 if ((ret
= mg_dsk_wait(mg_io_wait_drq
, MG_OEM_DISK_WAIT_TIME_NORMAL
)) != ERROR_OK
)
348 LOG_INFO("mflash: read drive info");
350 if (! mflash_bank
->drv_info
)
351 mflash_bank
->drv_info
= malloc(sizeof(struct mg_drv_info
));
353 target_read_memory(target
, mg_buff
, 2, sizeof(mg_io_type_drv_info
) >> 1,
354 (uint8_t *)&mflash_bank
->drv_info
->drv_id
);
358 mflash_bank
->drv_info
->tot_sects
= (uint32_t)(mflash_bank
->drv_info
->drv_id
.total_user_addressable_sectors_hi
<< 16)
359 + mflash_bank
->drv_info
->drv_id
.total_user_addressable_sectors_lo
;
361 return target_write_u8(target
, mflash_bank
->base
+ MG_REG_OFFSET
+ MG_REG_COMMAND
, mg_io_cmd_confirm_read
);
364 static int mg_mflash_rst(void)
368 if ((ret
= mg_init_gpio()) != ERROR_OK
)
371 if ((ret
= mg_hdrst(0)) != ERROR_OK
)
374 if ((ret
= mg_dsk_wait(mg_io_wait_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
377 if ((ret
= mg_hdrst(1)) != ERROR_OK
)
380 if ((ret
= mg_dsk_wait(mg_io_wait_not_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
383 if ((ret
= mg_dsk_srst(1)) != ERROR_OK
)
386 if ((ret
= mg_dsk_wait(mg_io_wait_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
389 if ((ret
= mg_dsk_srst(0)) != ERROR_OK
)
392 if ((ret
= mg_dsk_wait(mg_io_wait_not_bsy
, MG_OEM_DISK_WAIT_TIME_LONG
)) != ERROR_OK
)
395 LOG_INFO("mflash: reset ok");
400 static int mg_mflash_probe(void)
404 if ((ret
= mg_mflash_rst()) != ERROR_OK
)
407 return mg_dsk_drv_info();
410 COMMAND_HANDLER(mg_probe_cmd
)
414 ret
= mg_mflash_probe();
416 if (ret
== ERROR_OK
) {
417 command_print(CMD_CTX
, "mflash (total %" PRIu32
" sectors) found at 0x%8.8" PRIx32
"",
418 mflash_bank
->drv_info
->tot_sects
, mflash_bank
->base
);
424 static int mg_mflash_do_read_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
)
428 struct target
*target
= mflash_bank
->target
;
429 uint8_t *buff_ptr
= buff
;
431 if ((ret
= mg_dsk_io_cmd(sect_num
, sect_cnt
, mg_io_cmd_read
)) != ERROR_OK
)
434 address
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
436 struct duration bench
;
437 duration_start(&bench
);
439 for (i
= 0; i
< sect_cnt
; i
++) {
440 ret
= mg_dsk_wait(mg_io_wait_drq
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
444 ret
= target_read_memory(target
, address
, 2, MG_MFLASH_SECTOR_SIZE
/ 2, buff_ptr
);
448 buff_ptr
+= MG_MFLASH_SECTOR_SIZE
;
450 ret
= target_write_u8(target
, mflash_bank
->base
+ MG_REG_OFFSET
+ MG_REG_COMMAND
, mg_io_cmd_confirm_read
);
454 LOG_DEBUG("mflash: %" PRIu32
" (0x%8.8" PRIx32
") sector read", sect_num
+ i
, (sect_num
+ i
) * MG_MFLASH_SECTOR_SIZE
);
456 ret
= duration_measure(&bench
);
457 if ((ERROR_OK
== ret
) && (duration_elapsed(&bench
) > 3)) {
458 LOG_INFO("mflash: read %" PRIu32
"'th sectors", sect_num
+ i
);
459 duration_start(&bench
);
463 return mg_dsk_wait(mg_io_wait_rdy
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
466 static int mg_mflash_read_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
)
468 uint32_t quotient
, residue
, i
;
469 uint8_t *buff_ptr
= buff
;
472 quotient
= sect_cnt
>> 8;
473 residue
= sect_cnt
% 256;
475 for (i
= 0; i
< quotient
; i
++) {
476 LOG_DEBUG("mflash: sect num : %" PRIu32
" buff : %p",
478 ret
= mg_mflash_do_read_sects(buff_ptr
, sect_num
, 256);
483 buff_ptr
+= 256 * MG_MFLASH_SECTOR_SIZE
;
487 LOG_DEBUG("mflash: sect num : %" PRIx32
" buff : %p",
489 return mg_mflash_do_read_sects(buff_ptr
, sect_num
, residue
);
495 static int mg_mflash_do_write_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
,
500 struct target
*target
= mflash_bank
->target
;
501 uint8_t *buff_ptr
= buff
;
503 if ((ret
= mg_dsk_io_cmd(sect_num
, sect_cnt
, cmd
)) != ERROR_OK
)
506 address
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
508 struct duration bench
;
509 duration_start(&bench
);
511 for (i
= 0; i
< sect_cnt
; i
++) {
512 ret
= mg_dsk_wait(mg_io_wait_drq
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
516 ret
= target_write_memory(target
, address
, 2, MG_MFLASH_SECTOR_SIZE
/ 2, buff_ptr
);
520 buff_ptr
+= MG_MFLASH_SECTOR_SIZE
;
522 ret
= target_write_u8(target
, mflash_bank
->base
+ MG_REG_OFFSET
+ MG_REG_COMMAND
, mg_io_cmd_confirm_write
);
526 LOG_DEBUG("mflash: %" PRIu32
" (0x%8.8" PRIx32
") sector write", sect_num
+ i
, (sect_num
+ i
) * MG_MFLASH_SECTOR_SIZE
);
528 ret
= duration_measure(&bench
);
529 if ((ERROR_OK
== ret
) && (duration_elapsed(&bench
) > 3)) {
530 LOG_INFO("mflash: wrote %" PRIu32
"'th sectors", sect_num
+ i
);
531 duration_start(&bench
);
535 if (cmd
== mg_io_cmd_write
)
536 ret
= mg_dsk_wait(mg_io_wait_rdy
, MG_OEM_DISK_WAIT_TIME_NORMAL
);
538 ret
= mg_dsk_wait(mg_io_wait_rdy
, MG_OEM_DISK_WAIT_TIME_LONG
);
543 static int mg_mflash_write_sects(void *buff
, uint32_t sect_num
, uint32_t sect_cnt
)
545 uint32_t quotient
, residue
, i
;
546 uint8_t *buff_ptr
= buff
;
549 quotient
= sect_cnt
>> 8;
550 residue
= sect_cnt
% 256;
552 for (i
= 0; i
< quotient
; i
++) {
553 LOG_DEBUG("mflash: sect num : %" PRIu32
"buff : %p", sect_num
,
555 ret
= mg_mflash_do_write_sects(buff_ptr
, sect_num
, 256, mg_io_cmd_write
);
560 buff_ptr
+= 256 * MG_MFLASH_SECTOR_SIZE
;
564 LOG_DEBUG("mflash: sect num : %" PRIu32
" buff : %p", sect_num
,
566 return mg_mflash_do_write_sects(buff_ptr
, sect_num
, residue
, mg_io_cmd_write
);
572 static int mg_mflash_read (uint32_t addr
, uint8_t *buff
, uint32_t len
)
574 uint8_t *buff_ptr
= buff
;
575 uint8_t sect_buff
[MG_MFLASH_SECTOR_SIZE
];
576 uint32_t cur_addr
, next_sec_addr
, end_addr
, cnt
, sect_num
;
581 end_addr
= addr
+ len
;
583 if (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
) {
585 next_sec_addr
= (cur_addr
+ MG_MFLASH_SECTOR_SIZE
) & ~MG_MFLASH_SECTOR_SIZE_MASK
;
586 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
587 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
591 if (end_addr
< next_sec_addr
) {
592 memcpy(buff_ptr
, sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), end_addr
- cur_addr
);
593 LOG_DEBUG("mflash: copies %" PRIu32
" byte from sector offset 0x%8.8" PRIx32
"", end_addr
- cur_addr
, cur_addr
);
596 memcpy(buff_ptr
, sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), next_sec_addr
- cur_addr
);
597 LOG_DEBUG("mflash: copies %" PRIu32
" byte from sector offset 0x%8.8" PRIx32
"", next_sec_addr
- cur_addr
, cur_addr
);
598 buff_ptr
+= (next_sec_addr
- cur_addr
);
599 cur_addr
= next_sec_addr
;
603 if (cur_addr
< end_addr
) {
605 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
606 next_sec_addr
= cur_addr
+ MG_MFLASH_SECTOR_SIZE
;
608 while (next_sec_addr
<= end_addr
) {
610 next_sec_addr
+= MG_MFLASH_SECTOR_SIZE
;
614 if ((ret
= mg_mflash_read_sects(buff_ptr
, sect_num
, cnt
)) != ERROR_OK
)
617 buff_ptr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
618 cur_addr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
620 if (cur_addr
< end_addr
) {
622 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
623 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
627 memcpy(buff_ptr
, sect_buff
, end_addr
- cur_addr
);
628 LOG_DEBUG("mflash: copies %u byte", (unsigned)(end_addr
- cur_addr
));
636 static int mg_mflash_write(uint32_t addr
, uint8_t *buff
, uint32_t len
)
638 uint8_t *buff_ptr
= buff
;
639 uint8_t sect_buff
[MG_MFLASH_SECTOR_SIZE
];
640 uint32_t cur_addr
, next_sec_addr
, end_addr
, cnt
, sect_num
;
645 end_addr
= addr
+ len
;
647 if (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
) {
649 next_sec_addr
= (cur_addr
+ MG_MFLASH_SECTOR_SIZE
) & ~MG_MFLASH_SECTOR_SIZE_MASK
;
650 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
651 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
655 if (end_addr
< next_sec_addr
) {
656 memcpy(sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), buff_ptr
, end_addr
- cur_addr
);
657 LOG_DEBUG("mflash: copies %" PRIu32
" byte to sector offset 0x%8.8" PRIx32
"", end_addr
- cur_addr
, cur_addr
);
660 memcpy(sect_buff
+ (cur_addr
& MG_MFLASH_SECTOR_SIZE_MASK
), buff_ptr
, next_sec_addr
- cur_addr
);
661 LOG_DEBUG("mflash: copies %" PRIu32
" byte to sector offset 0x%8.8" PRIx32
"", next_sec_addr
- cur_addr
, cur_addr
);
662 buff_ptr
+= (next_sec_addr
- cur_addr
);
663 cur_addr
= next_sec_addr
;
666 ret
= mg_mflash_write_sects(sect_buff
, sect_num
, 1);
671 if (cur_addr
< end_addr
) {
673 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
674 next_sec_addr
= cur_addr
+ MG_MFLASH_SECTOR_SIZE
;
676 while (next_sec_addr
<= end_addr
) {
678 next_sec_addr
+= MG_MFLASH_SECTOR_SIZE
;
682 if ((ret
= mg_mflash_write_sects(buff_ptr
, sect_num
, cnt
)) != ERROR_OK
)
685 buff_ptr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
686 cur_addr
+= cnt
* MG_MFLASH_SECTOR_SIZE
;
688 if (cur_addr
< end_addr
) {
690 sect_num
= cur_addr
>> MG_MFLASH_SECTOR_SIZE_SHIFT
;
691 ret
= mg_mflash_read_sects(sect_buff
, sect_num
, 1);
695 memcpy(sect_buff
, buff_ptr
, end_addr
- cur_addr
);
696 LOG_DEBUG("mflash: copies %" PRIu32
" byte", end_addr
- cur_addr
);
697 ret
= mg_mflash_write_sects(sect_buff
, sect_num
, 1);
704 COMMAND_HANDLER(mg_write_cmd
)
706 uint32_t address
, cnt
, res
, i
;
708 struct fileio fileio
;
712 return ERROR_COMMAND_SYNTAX_ERROR
;
715 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], address
);
717 ret
= fileio_open(&fileio
, CMD_ARGV
[1], FILEIO_READ
, FILEIO_BINARY
);
721 buffer
= malloc(MG_FILEIO_CHUNK
);
723 fileio_close(&fileio
);
727 cnt
= fileio
.size
/ MG_FILEIO_CHUNK
;
728 res
= fileio
.size
% MG_FILEIO_CHUNK
;
730 struct duration bench
;
731 duration_start(&bench
);
734 for (i
= 0; i
< cnt
; i
++) {
735 if ((ret
= fileio_read(&fileio
, MG_FILEIO_CHUNK
, buffer
, &buf_cnt
)) !=
737 goto mg_write_cmd_err
;
738 if ((ret
= mg_mflash_write(address
, buffer
, MG_FILEIO_CHUNK
)) != ERROR_OK
)
739 goto mg_write_cmd_err
;
740 address
+= MG_FILEIO_CHUNK
;
744 if ((ret
= fileio_read(&fileio
, res
, buffer
, &buf_cnt
)) != ERROR_OK
)
745 goto mg_write_cmd_err
;
746 if ((ret
= mg_mflash_write(address
, buffer
, res
)) != ERROR_OK
)
747 goto mg_write_cmd_err
;
750 if (duration_measure(&bench
) == ERROR_OK
)
752 command_print(CMD_CTX
, "wrote %zu byte from file %s "
753 "in %fs (%0.3f kB/s)", fileio
.size
, CMD_ARGV
[1],
754 duration_elapsed(&bench
), duration_kbps(&bench
, fileio
.size
));
758 fileio_close(&fileio
);
764 fileio_close(&fileio
);
769 COMMAND_HANDLER(mg_dump_cmd
)
771 uint32_t address
, size
, cnt
, res
, i
;
773 struct fileio fileio
;
777 return ERROR_COMMAND_SYNTAX_ERROR
;
780 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], address
);
781 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[3], size
);
783 ret
= fileio_open(&fileio
, CMD_ARGV
[1], FILEIO_WRITE
, FILEIO_BINARY
);
787 buffer
= malloc(MG_FILEIO_CHUNK
);
789 fileio_close(&fileio
);
793 cnt
= size
/ MG_FILEIO_CHUNK
;
794 res
= size
% MG_FILEIO_CHUNK
;
796 struct duration bench
;
797 duration_start(&bench
);
800 for (i
= 0; i
< cnt
; i
++) {
801 if ((ret
= mg_mflash_read(address
, buffer
, MG_FILEIO_CHUNK
)) != ERROR_OK
)
802 goto mg_dump_cmd_err
;
803 if ((ret
= fileio_write(&fileio
, MG_FILEIO_CHUNK
, buffer
, &size_written
))
805 goto mg_dump_cmd_err
;
806 address
+= MG_FILEIO_CHUNK
;
810 if ((ret
= mg_mflash_read(address
, buffer
, res
)) != ERROR_OK
)
811 goto mg_dump_cmd_err
;
812 if ((ret
= fileio_write(&fileio
, res
, buffer
, &size_written
)) != ERROR_OK
)
813 goto mg_dump_cmd_err
;
816 if (duration_measure(&bench
) == ERROR_OK
)
818 command_print(CMD_CTX
, "dump image (address 0x%8.8" PRIx32
" "
819 "size %" PRIu32
") to file %s in %fs (%0.3f kB/s)",
820 address
, size
, CMD_ARGV
[1],
821 duration_elapsed(&bench
), duration_kbps(&bench
, size
));
825 fileio_close(&fileio
);
831 fileio_close(&fileio
);
836 static int mg_set_feature(mg_feature_id feature
, mg_feature_val config
)
838 struct target
*target
= mflash_bank
->target
;
839 uint32_t mg_task_reg
= mflash_bank
->base
+ MG_REG_OFFSET
;
842 if ((ret
= mg_dsk_wait(mg_io_wait_rdy_noerr
, MG_OEM_DISK_WAIT_TIME_NORMAL
))
846 ret
= target_write_u8(target
, mg_task_reg
+ MG_REG_FEATURE
, feature
);
847 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_SECT_CNT
, config
);
848 ret
|= target_write_u8(target
, mg_task_reg
+ MG_REG_COMMAND
,
849 mg_io_cmd_set_feature
);
854 static int mg_is_valid_pll(double XIN
, int N
, double CLK_OUT
, int NO
)
857 double v2
= CLK_OUT
* NO
;
859 if (v1
<1000000 || v1
> 15000000 || v2
< 100000000 || v2
> 500000000)
860 return ERROR_MG_INVALID_PLL
;
865 static int mg_pll_get_M(unsigned short feedback_div
)
869 for (i
= 1, M
= 0; i
< 512; i
<<= 1, feedback_div
>>= 1)
870 M
+= (feedback_div
& 1) * i
;
875 static int mg_pll_get_N(unsigned char input_div
)
879 for (i
= 1, N
= 0; i
< 32; i
<<= 1, input_div
>>= 1)
880 N
+= (input_div
& 1) * i
;
885 static int mg_pll_get_NO(unsigned char output_div
)
889 for (i
= 0, NO
= 1; i
< 2; ++i
, output_div
>>= 1)
896 static double mg_do_calc_pll(double XIN
, mg_pll_t
* p_pll_val
, int is_approximate
)
905 if (is_approximate
) {
910 for (i
= 0; i
< MG_PLL_MAX_FEEDBACKDIV_VAL
; ++i
) {
913 for (j
= 0; j
< MG_PLL_MAX_INPUTDIV_VAL
; ++j
) {
916 for (k
= 0; k
< MG_PLL_MAX_OUTPUTDIV_VAL
; ++k
) {
917 NO
= mg_pll_get_NO(k
);
919 CLK_OUT
= XIN
* ((double)M
/ N
) / NO
;
921 if ((int)((CLK_OUT
+ ROUND
) / DIV
)
922 == (int)(MG_PLL_CLK_OUT
/ DIV
)) {
923 if (mg_is_valid_pll(XIN
, N
, CLK_OUT
, NO
) == ERROR_OK
)
925 p_pll_val
->lock_cyc
= (int)(XIN
* MG_PLL_STD_LOCKCYCLE
/ MG_PLL_STD_INPUTCLK
);
926 p_pll_val
->feedback_div
= i
;
927 p_pll_val
->input_div
= j
;
928 p_pll_val
->output_div
= k
;
940 static double mg_calc_pll(double XIN
, mg_pll_t
*p_pll_val
)
944 CLK_OUT
= mg_do_calc_pll(XIN
, p_pll_val
, 0);
947 return mg_do_calc_pll(XIN
, p_pll_val
, 1);
952 static int mg_verify_interface(void)
954 uint16_t buff
[MG_MFLASH_SECTOR_SIZE
>> 1];
956 uint32_t address
= mflash_bank
->base
+ MG_BUFFER_OFFSET
;
957 struct target
*target
= mflash_bank
->target
;
960 for (j
= 0; j
< 10; j
++) {
961 for (i
= 0; i
< MG_MFLASH_SECTOR_SIZE
>> 1; i
++)
964 ret
= target_write_memory(target
, address
, 2,
965 MG_MFLASH_SECTOR_SIZE
/ 2, (uint8_t *)buff
);
969 memset(buff
, 0xff, MG_MFLASH_SECTOR_SIZE
);
971 ret
= target_read_memory(target
, address
, 2,
972 MG_MFLASH_SECTOR_SIZE
/ 2, (uint8_t *)buff
);
976 for (i
= 0; i
< MG_MFLASH_SECTOR_SIZE
>> 1; i
++) {
978 LOG_ERROR("mflash: verify interface fail");
979 return ERROR_MG_INTERFACE
;
984 LOG_INFO("mflash: verify interface ok");
988 static const char g_strSEG_SerialNum
[20] = {
989 'G','m','n','i','-','e','e','S','g','a','e','l',
990 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
993 static const char g_strSEG_FWRev
[8] = {
994 'F','X','L','T','2','v','0','.'
997 static const char g_strSEG_ModelNum
[40] = {
998 'F','X','A','L','H','S','2',0x20,'0','0','s','7',
999 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
1000 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,
1001 0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20
1004 static void mg_gen_ataid(mg_io_type_drv_info
*pSegIdDrvInfo
)
1006 /* b15 is ATA device(0) , b7 is Removable Media Device */
1007 pSegIdDrvInfo
->general_configuration
= 0x045A;
1008 /* 128MB : Cylinder=> 977 , Heads=> 8 , Sectors=> 32
1009 * 256MB : Cylinder=> 980 , Heads=> 16 , Sectors=> 32
1010 * 384MB : Cylinder=> 745 , Heads=> 16 , Sectors=> 63
1012 pSegIdDrvInfo
->number_of_cylinders
= 0x02E9;
1013 pSegIdDrvInfo
->reserved1
= 0x0;
1014 pSegIdDrvInfo
->number_of_heads
= 0x10;
1015 pSegIdDrvInfo
->unformatted_bytes_per_track
= 0x0;
1016 pSegIdDrvInfo
->unformatted_bytes_per_sector
= 0x0;
1017 pSegIdDrvInfo
->sectors_per_track
= 0x3F;
1018 pSegIdDrvInfo
->vendor_unique1
[0] = 0x000B;
1019 pSegIdDrvInfo
->vendor_unique1
[1] = 0x7570;
1020 pSegIdDrvInfo
->vendor_unique1
[2] = 0x8888;
1022 memcpy(pSegIdDrvInfo
->serial_number
, (void *)g_strSEG_SerialNum
,20);
1023 /* 0x2 : dual buffer */
1024 pSegIdDrvInfo
->buffer_type
= 0x2;
1025 /* buffer size : 2KB */
1026 pSegIdDrvInfo
->buffer_sector_size
= 0x800;
1027 pSegIdDrvInfo
->number_of_ecc_bytes
= 0;
1029 memcpy(pSegIdDrvInfo
->firmware_revision
, (void *)g_strSEG_FWRev
,8);
1031 memcpy(pSegIdDrvInfo
->model_number
, (void *)g_strSEG_ModelNum
,40);
1033 pSegIdDrvInfo
->maximum_block_transfer
= 0x4;
1034 pSegIdDrvInfo
->vendor_unique2
= 0x0;
1035 pSegIdDrvInfo
->dword_io
= 0x00;
1036 /* b11 : IORDY support(PIO Mode 4), b10 : Disable/Enbale IORDY
1037 * b9 : LBA support, b8 : DMA mode support
1039 pSegIdDrvInfo
->capabilities
= 0x1 << 9;
1041 pSegIdDrvInfo
->reserved2
= 0x4000;
1042 pSegIdDrvInfo
->vendor_unique3
= 0x00;
1043 /* PIOMode-2 support */
1044 pSegIdDrvInfo
->pio_cycle_timing_mode
= 0x02;
1045 pSegIdDrvInfo
->vendor_unique4
= 0x00;
1046 /* MultiWord-2 support */
1047 pSegIdDrvInfo
->dma_cycle_timing_mode
= 0x00;
1048 /* b1 : word64~70 is valid
1049 * b0 : word54~58 are valid and reflect the current numofcyls,heads,sectors
1050 * b2 : If device supports Ultra DMA , set to one to vaildate word88
1052 pSegIdDrvInfo
->translation_fields_valid
= (0x1 << 1) | (0x1 << 0);
1053 pSegIdDrvInfo
->number_of_current_cylinders
= 0x02E9;
1054 pSegIdDrvInfo
->number_of_current_heads
= 0x10;
1055 pSegIdDrvInfo
->current_sectors_per_track
= 0x3F;
1056 pSegIdDrvInfo
->current_sector_capacity_lo
= 0x7570;
1057 pSegIdDrvInfo
->current_sector_capacity_hi
= 0x000B;
1059 pSegIdDrvInfo
->multi_sector_count
= 0x04;
1060 /* b8 : Multiple secotr setting valid , b[7:0] num of secotrs per block */
1061 pSegIdDrvInfo
->multi_sector_setting_valid
= 0x01;
1062 pSegIdDrvInfo
->total_user_addressable_sectors_lo
= 0x7570;
1063 pSegIdDrvInfo
->total_user_addressable_sectors_hi
= 0x000B;
1064 pSegIdDrvInfo
->single_dma_modes_supported
= 0x00;
1065 pSegIdDrvInfo
->single_dma_transfer_active
= 0x00;
1066 /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
1067 pSegIdDrvInfo
->multi_dma_modes_supported
= (0x1 << 0);
1068 /* b2 :Multi-word DMA mode 2, b1 : Multi-word DMA mode 1 */
1069 pSegIdDrvInfo
->multi_dma_transfer_active
= (0x1 << 0);
1070 /* b0 : PIO Mode-3 support, b1 : PIO Mode-4 support */
1071 pSegIdDrvInfo
->adv_pio_mode
= 0x00;
1072 /* 480(0x1E0)nsec for Multi-word DMA mode0
1073 * 150(0x96) nsec for Multi-word DMA mode1
1074 * 120(0x78) nsec for Multi-word DMA mode2
1076 pSegIdDrvInfo
->min_dma_cyc
= 0x1E0;
1077 pSegIdDrvInfo
->recommend_dma_cyc
= 0x1E0;
1078 pSegIdDrvInfo
->min_pio_cyc_no_iordy
= 0x1E0;
1079 pSegIdDrvInfo
->min_pio_cyc_with_iordy
= 0x1E0;
1080 memset((void *)pSegIdDrvInfo
->reserved3
, 0x00, 22);
1081 /* b7 : ATA/ATAPI-7 ,b6 : ATA/ATAPI-6 ,b5 : ATA/ATAPI-5,b4 : ATA/ATAPI-4 */
1082 pSegIdDrvInfo
->major_ver_num
= 0x7E;
1083 /* 0x1C : ATA/ATAPI-6 T13 1532D revision1 */
1084 pSegIdDrvInfo
->minor_ver_num
= 0x19;
1085 /* NOP/READ BUFFER/WRITE BUFFER/Power management feature set support */
1086 pSegIdDrvInfo
->feature_cmd_set_suprt0
= 0x7068;
1087 /* Features/command set is valid/Advanced Pwr management/CFA feature set
1090 pSegIdDrvInfo
->feature_cmd_set_suprt1
= 0x400C;
1091 pSegIdDrvInfo
->feature_cmd_set_suprt2
= 0x4000;
1092 /* READ/WRITE BUFFER/PWR Management enable */
1093 pSegIdDrvInfo
->feature_cmd_set_en0
= 0x7000;
1094 /* CFA feature is disabled / Advancde power management disable */
1095 pSegIdDrvInfo
->feature_cmd_set_en1
= 0x0;
1096 pSegIdDrvInfo
->feature_cmd_set_en2
= 0x4000;
1097 pSegIdDrvInfo
->reserved4
= 0x0;
1098 /* 0x1 * 2minutes */
1099 pSegIdDrvInfo
->req_time_for_security_er_done
= 0x19;
1100 pSegIdDrvInfo
->req_time_for_enhan_security_er_done
= 0x19;
1101 /* Advanced power management level 1 */
1102 pSegIdDrvInfo
->adv_pwr_mgm_lvl_val
= 0x0;
1103 pSegIdDrvInfo
->reserved5
= 0x0;
1104 memset((void *)pSegIdDrvInfo
->reserved6
, 0x00, 68);
1105 /* Security mode feature is disabled */
1106 pSegIdDrvInfo
->security_stas
= 0x0;
1107 memset((void *)pSegIdDrvInfo
->vendor_uniq_bytes
, 0x00, 62);
1108 /* CFA power mode 1 support in maximum 200mA */
1109 pSegIdDrvInfo
->cfa_pwr_mode
= 0x0100;
1110 memset((void *)pSegIdDrvInfo
->reserved7
, 0x00, 190);
1113 static int mg_storage_config(void)
1118 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1122 mg_gen_ataid((mg_io_type_drv_info
*)buff
);
1124 if ((ret
= mg_mflash_do_write_sects(buff
, 0, 1, mg_vcmd_update_stgdrvinfo
))
1128 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1132 LOG_INFO("mflash: storage config ok");
1136 static int mg_boot_config(void)
1141 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1145 memset(buff
, 0xff, 512);
1147 buff
[0] = mg_op_mode_snd
; /* operation mode */
1148 buff
[1] = MG_UNLOCK_OTP_AREA
;
1149 buff
[2] = 4; /* boot size */
1150 *((uint32_t *)(buff
+ 4)) = 0; /* XIP size */
1152 if ((ret
= mg_mflash_do_write_sects(buff
, 0, 1, mg_vcmd_update_xipinfo
))
1156 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1160 LOG_INFO("mflash: boot config ok");
1164 static int mg_set_pll(mg_pll_t
*pll
)
1169 memset(buff
, 0xff, 512);
1170 /* PLL Lock cycle and Feedback 9bit Divider */
1171 memcpy(buff
, &pll
->lock_cyc
, sizeof(uint32_t));
1172 memcpy(buff
+ 4, &pll
->feedback_div
, sizeof(uint16_t));
1173 buff
[6] = pll
->input_div
; /* PLL Input 5bit Divider */
1174 buff
[7] = pll
->output_div
; /* PLL Output Divider */
1176 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1180 if ((ret
= mg_mflash_do_write_sects(buff
, 0, 1, mg_vcmd_wr_pll
))
1184 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1188 LOG_INFO("mflash: set pll ok");
1192 static int mg_erase_nand(void)
1196 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_vcmd
))
1200 if ((ret
= mg_mflash_do_write_sects(NULL
, 0, 0, mg_vcmd_purge_nand
))
1204 if ((ret
= mg_set_feature(mg_feature_id_transmode
, mg_feature_val_trans_default
))
1208 LOG_INFO("mflash: erase nand ok");
1212 COMMAND_HANDLER(mg_config_cmd
)
1218 if ((ret
= mg_verify_interface()) != ERROR_OK
)
1221 if ((ret
= mg_mflash_rst()) != ERROR_OK
)
1226 if (!strcmp(CMD_ARGV
[1], "boot"))
1227 return mg_boot_config();
1228 else if (!strcmp(CMD_ARGV
[1], "storage"))
1229 return mg_storage_config();
1231 return ERROR_COMMAND_NOTFOUND
;
1234 if (!strcmp(CMD_ARGV
[1], "pll")) {
1236 COMMAND_PARSE_NUMBER(ulong
, CMD_ARGV
[2], freq
);
1239 if (fin
> MG_PLL_CLK_OUT
) {
1240 LOG_ERROR("mflash: input freq. is too large");
1241 return ERROR_MG_INVALID_OSC
;
1244 fout
= mg_calc_pll(fin
, &pll
);
1247 LOG_ERROR("mflash: cannot generate valid pll");
1248 return ERROR_MG_INVALID_PLL
;
1251 LOG_INFO("mflash: Fout=%" PRIu32
" Hz, feedback=%u,"
1252 "indiv=%u, outdiv=%u, lock=%u",
1253 (uint32_t)fout
, pll
.feedback_div
,
1254 pll
.input_div
, pll
.output_div
,
1257 if ((ret
= mg_erase_nand()) != ERROR_OK
)
1260 return mg_set_pll(&pll
);
1262 return ERROR_COMMAND_NOTFOUND
;
1265 return ERROR_COMMAND_SYNTAX_ERROR
;
1269 static const struct command_registration mflash_exec_command_handlers
[] = {
1272 .handler
= &mg_probe_cmd
,
1273 .mode
= COMMAND_EXEC
,
1274 .help
= "Detect bank configuration information",
1278 .handler
= &mg_write_cmd
,
1279 .mode
= COMMAND_EXEC
,
1280 .usage
= "<num> <file> <address>",
1281 .help
= "Write a file at the specified address",
1285 .handler
= &mg_dump_cmd
,
1286 .mode
= COMMAND_EXEC
,
1287 .usage
= "<num> <file> <address> <size>",
1288 .help
= "Dump to a file from the specified address",
1292 .handler
= &mg_config_cmd
,
1293 .mode
= COMMAND_EXEC
,
1294 .usage
= "<num> <stage>",
1295 .help
= "Dump to a file from the specified address",
1297 COMMAND_REGISTRATION_DONE
1300 int mflash_init_drivers(struct command_context
*cmd_ctx
)
1304 return register_commands(cmd_ctx
, NULL
, mflash_exec_command_handlers
);
1307 COMMAND_HANDLER(mg_bank_cmd
)
1309 struct target
*target
;
1314 return ERROR_COMMAND_SYNTAX_ERROR
;
1317 if ((target
= get_target(CMD_ARGV
[3])) == NULL
)
1319 LOG_ERROR("target '%s' not defined", CMD_ARGV
[3]);
1323 mflash_bank
= calloc(sizeof(struct mflash_bank
), 1);
1324 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], mflash_bank
->base
);
1325 /// @todo Verify how this parsing should work, then document it.
1327 mflash_bank
->rst_pin
.num
= strtoul(CMD_ARGV
[2], &str
, 0);
1329 mflash_bank
->rst_pin
.port
[0] = (uint16_t)tolower(str
[0]);
1331 mflash_bank
->target
= target
;
1333 for (i
= 0; mflash_gpio
[i
] ; i
++) {
1334 if (! strcmp(mflash_gpio
[i
]->name
, CMD_ARGV
[0])) {
1335 mflash_bank
->gpio_drv
= mflash_gpio
[i
];
1339 if (! mflash_bank
->gpio_drv
) {
1340 LOG_ERROR("%s is unsupported soc", CMD_ARGV
[0]);
1341 return ERROR_MG_UNSUPPORTED_SOC
;
1347 static const struct command_registration mflash_config_command_handlers
[] = {
1350 .handler
= &mg_bank_cmd
,
1351 .mode
= COMMAND_CONFIG
,
1352 .help
= "configure a mflash device bank",
1353 .usage
= "<soc> <base> <RST pin> <target #>",
1355 COMMAND_REGISTRATION_DONE
1357 static const struct command_registration mflash_command_handler
[] = {
1360 .mode
= COMMAND_ANY
,
1361 .help
= "mflash command group",
1362 .chain
= mflash_config_command_handlers
,
1364 COMMAND_REGISTRATION_DONE
1366 int mflash_register_commands(struct command_context
*cmd_ctx
)
1368 return register_commands(cmd_ctx
, NULL
, mflash_command_handler
);