1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
6 * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
29 #include <target/target.h>
32 static int lpc3180_reset(struct nand_device
*nand
);
33 static int lpc3180_controller_ready(struct nand_device
*nand
, int timeout
);
34 static int lpc3180_tc_ready(struct nand_device
*nand
, int timeout
);
37 #define ECC_OFFS 0x120
38 #define SPARE_OFFS 0x140
39 #define DATA_OFFS 0x200
42 /* nand device lpc3180 <target#> <oscillator_frequency>
44 NAND_DEVICE_COMMAND_HANDLER(lpc3180_nand_device_command
)
48 LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
49 return ERROR_FLASH_BANK_INVALID
;
52 struct target
*target
= get_target(CMD_ARGV
[1]);
55 LOG_ERROR("target '%s' not defined", CMD_ARGV
[1]);
56 return ERROR_NAND_DEVICE_INVALID
;
60 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], osc_freq
);
62 struct lpc3180_nand_controller
*lpc3180_info
;
63 lpc3180_info
= malloc(sizeof(struct lpc3180_nand_controller
));
64 nand
->controller_priv
= lpc3180_info
;
66 lpc3180_info
->target
= target
;
67 lpc3180_info
->osc_freq
= osc_freq
;
69 if ((lpc3180_info
->osc_freq
< 1000) || (lpc3180_info
->osc_freq
> 20000))
71 LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info
->osc_freq
);
73 lpc3180_info
->selected_controller
= LPC3180_NO_CONTROLLER
;
74 lpc3180_info
->sw_write_protection
= 0;
75 lpc3180_info
->sw_wp_lower_bound
= 0x0;
76 lpc3180_info
->sw_wp_upper_bound
= 0x0;
81 static int lpc3180_pll(int fclkin
, uint32_t pll_ctrl
)
83 int bypass
= (pll_ctrl
& 0x8000) >> 15;
84 int direct
= (pll_ctrl
& 0x4000) >> 14;
85 int feedback
= (pll_ctrl
& 0x2000) >> 13;
86 int p
= (1 << ((pll_ctrl
& 0x1800) >> 11) * 2);
87 int n
= ((pll_ctrl
& 0x0600) >> 9) + 1;
88 int m
= ((pll_ctrl
& 0x01fe) >> 1) + 1;
89 int lock
= (pll_ctrl
& 0x1);
92 LOG_WARNING("PLL is not locked");
94 if (!bypass
&& direct
) /* direct mode */
95 return (m
* fclkin
) / n
;
97 if (bypass
&& !direct
) /* bypass mode */
98 return fclkin
/ (2 * p
);
100 if (bypass
& direct
) /* direct bypass mode */
103 if (feedback
) /* integer mode */
104 return m
* (fclkin
/ n
);
105 else /* non-integer mode */
106 return (m
/ (2 * p
)) * (fclkin
/ n
);
109 static float lpc3180_cycle_time(struct lpc3180_nand_controller
*lpc3180_info
)
111 struct target
*target
= lpc3180_info
->target
;
112 uint32_t sysclk_ctrl
, pwr_ctrl
, hclkdiv_ctrl
, hclkpll_ctrl
;
118 /* calculate timings */
120 /* determine current SYSCLK (13'MHz or main oscillator) */
121 target_read_u32(target
, 0x40004050, &sysclk_ctrl
);
123 if ((sysclk_ctrl
& 1) == 0)
124 sysclk
= lpc3180_info
->osc_freq
;
128 /* determine selected HCLK source */
129 target_read_u32(target
, 0x40004044, &pwr_ctrl
);
131 if ((pwr_ctrl
& (1 << 2)) == 0) /* DIRECT RUN mode */
137 target_read_u32(target
, 0x40004058, &hclkpll_ctrl
);
138 hclk_pll
= lpc3180_pll(sysclk
, hclkpll_ctrl
);
140 target_read_u32(target
, 0x40004040, &hclkdiv_ctrl
);
142 if (pwr_ctrl
& (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
144 hclk
= hclk_pll
/ (((hclkdiv_ctrl
& 0x7c) >> 2) + 1);
146 else /* HCLK uses HCLK_PLL */
148 hclk
= hclk_pll
/ (1 << (hclkdiv_ctrl
& 0x3));
152 LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk
);
154 cycle
= (1.0 / hclk
) * 1000000.0;
159 static int lpc3180_init(struct nand_device
*nand
)
161 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
162 struct target
*target
= lpc3180_info
->target
;
163 int bus_width
= nand
->bus_width
? : 8;
164 int address_cycles
= nand
->address_cycles
? : 3;
165 int page_size
= nand
->page_size
? : 512;
167 if (target
->state
!= TARGET_HALTED
)
169 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
170 return ERROR_NAND_OPERATION_FAILED
;
173 /* sanitize arguments */
174 if ((bus_width
!= 8) && (bus_width
!= 16))
176 LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width
);
177 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
180 /* The LPC3180 only brings out 8 bit NAND data bus, but the controller
181 * would support 16 bit, too, so we just warn about this for now
185 LOG_WARNING("LPC3180 only supports 8 bit bus width");
188 /* inform calling code about selected bus width */
189 nand
->bus_width
= bus_width
;
191 if ((address_cycles
!= 3) && (address_cycles
!= 4))
193 LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles
);
194 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
197 if ((page_size
!= 512) && (page_size
!= 2048))
199 LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size
);
200 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
203 /* select MLC controller if none is currently selected */
204 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
206 LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
207 lpc3180_info
->selected_controller
= LPC3180_MLC_CONTROLLER
;
210 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
212 uint32_t mlc_icr_value
= 0x0;
214 int twp
, twh
, trp
, treh
, trhz
, trbwb
, tcea
;
216 /* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
217 target_write_u32(target
, 0x400040c8, 0x22);
219 /* MLC_CEH = 0x0 (Force nCE assert) */
220 target_write_u32(target
, 0x200b804c, 0x0);
222 /* MLC_LOCK = 0xa25e (unlock protected registers) */
223 target_write_u32(target
, 0x200b8044, 0xa25e);
225 /* MLC_ICR = configuration */
226 if (lpc3180_info
->sw_write_protection
)
227 mlc_icr_value
|= 0x8;
228 if (page_size
== 2048)
229 mlc_icr_value
|= 0x4;
230 if (address_cycles
== 4)
231 mlc_icr_value
|= 0x2;
233 mlc_icr_value
|= 0x1;
234 target_write_u32(target
, 0x200b8030, mlc_icr_value
);
236 /* calculate NAND controller timings */
237 cycle
= lpc3180_cycle_time(lpc3180_info
);
239 twp
= ((40 / cycle
) + 1);
240 twh
= ((20 / cycle
) + 1);
241 trp
= ((30 / cycle
) + 1);
242 treh
= ((15 / cycle
) + 1);
243 trhz
= ((30 / cycle
) + 1);
244 trbwb
= ((100 / cycle
) + 1);
245 tcea
= ((45 / cycle
) + 1);
247 /* MLC_LOCK = 0xa25e (unlock protected registers) */
248 target_write_u32(target
, 0x200b8044, 0xa25e);
251 target_write_u32(target
, 0x200b8034, (twp
& 0xf) | ((twh
& 0xf) << 4) |
252 ((trp
& 0xf) << 8) | ((treh
& 0xf) << 12) | ((trhz
& 0x7) << 16) |
253 ((trbwb
& 0x1f) << 19) | ((tcea
& 0x3) << 24));
257 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
260 int r_setup
, r_hold
, r_width
, r_rdy
;
261 int w_setup
, w_hold
, w_width
, w_rdy
;
263 /* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
264 target_write_u32(target
, 0x400040c8, 0x05);
266 /* after reset set other registers of SLC so reset calling is here at the begining*/
269 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
270 target_write_u32(target
, 0x20020014, 0x3e | (bus_width
== 16) ? 1 : 0);
272 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
273 target_write_u32(target
, 0x20020020, 0x03);
275 /* DMA configuration */
276 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
277 target_write_u32(target
, 0x400040e8, 0x01);
278 /* DMACConfig = DMA enabled*/
279 target_write_u32(target
, 0x31000030, 0x01);
282 /* calculate NAND controller timings */
283 cycle
= lpc3180_cycle_time(lpc3180_info
);
285 r_setup
= w_setup
= 0;
286 r_hold
= w_hold
= 10 / cycle
;
287 r_width
= 30 / cycle
;
288 w_width
= 40 / cycle
;
289 r_rdy
= w_rdy
= 100 / cycle
;
291 /* SLC_TAC: SLC timing arcs register */
292 target_write_u32(target
, 0x2002002c, (r_setup
& 0xf) | ((r_hold
& 0xf) << 4) |
293 ((r_width
& 0xf) << 8) | ((r_rdy
& 0xf) << 12) | ((w_setup
& 0xf) << 16) |
294 ((w_hold
& 0xf) << 20) | ((w_width
& 0xf) << 24) | ((w_rdy
& 0xf) << 28));
301 static int lpc3180_reset(struct nand_device
*nand
)
303 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
304 struct target
*target
= lpc3180_info
->target
;
306 if (target
->state
!= TARGET_HALTED
)
308 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
309 return ERROR_NAND_OPERATION_FAILED
;
312 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
314 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
315 return ERROR_NAND_OPERATION_FAILED
;
317 else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
319 /* MLC_CMD = 0xff (reset controller and NAND device) */
320 target_write_u32(target
, 0x200b8000, 0xff);
322 if (!lpc3180_controller_ready(nand
, 100))
324 LOG_ERROR("LPC3180 NAND controller timed out after reset");
325 return ERROR_NAND_OPERATION_TIMEOUT
;
328 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
330 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
331 target_write_u32(target
, 0x20020010, 0x6);
333 if (!lpc3180_controller_ready(nand
, 100))
335 LOG_ERROR("LPC3180 NAND controller timed out after reset");
336 return ERROR_NAND_OPERATION_TIMEOUT
;
343 static int lpc3180_command(struct nand_device
*nand
, uint8_t command
)
345 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
346 struct target
*target
= lpc3180_info
->target
;
348 if (target
->state
!= TARGET_HALTED
)
350 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
351 return ERROR_NAND_OPERATION_FAILED
;
354 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
356 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
357 return ERROR_NAND_OPERATION_FAILED
;
359 else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
361 /* MLC_CMD = command */
362 target_write_u32(target
, 0x200b8000, command
);
364 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
366 /* SLC_CMD = command */
367 target_write_u32(target
, 0x20020008, command
);
373 static int lpc3180_address(struct nand_device
*nand
, uint8_t address
)
375 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
376 struct target
*target
= lpc3180_info
->target
;
378 if (target
->state
!= TARGET_HALTED
)
380 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
381 return ERROR_NAND_OPERATION_FAILED
;
384 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
386 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
387 return ERROR_NAND_OPERATION_FAILED
;
389 else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
391 /* MLC_ADDR = address */
392 target_write_u32(target
, 0x200b8004, address
);
394 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
396 /* SLC_ADDR = address */
397 target_write_u32(target
, 0x20020004, address
);
403 static int lpc3180_write_data(struct nand_device
*nand
, uint16_t data
)
405 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
406 struct target
*target
= lpc3180_info
->target
;
408 if (target
->state
!= TARGET_HALTED
)
410 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
411 return ERROR_NAND_OPERATION_FAILED
;
414 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
416 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
417 return ERROR_NAND_OPERATION_FAILED
;
419 else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
421 /* MLC_DATA = data */
422 target_write_u32(target
, 0x200b0000, data
);
424 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
426 /* SLC_DATA = data */
427 target_write_u32(target
, 0x20020000, data
);
433 static int lpc3180_read_data(struct nand_device
*nand
, void *data
)
435 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
436 struct target
*target
= lpc3180_info
->target
;
438 if (target
->state
!= TARGET_HALTED
)
440 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
441 return ERROR_NAND_OPERATION_FAILED
;
444 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
446 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
447 return ERROR_NAND_OPERATION_FAILED
;
449 else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
451 /* data = MLC_DATA, use sized access */
452 if (nand
->bus_width
== 8)
454 uint8_t *data8
= data
;
455 target_read_u8(target
, 0x200b0000, data8
);
457 else if (nand
->bus_width
== 16)
459 uint16_t *data16
= data
;
460 target_read_u16(target
, 0x200b0000, data16
);
464 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
465 return ERROR_NAND_OPERATION_FAILED
;
468 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
472 /* data = SLC_DATA, must use 32-bit access */
473 target_read_u32(target
, 0x20020000, &data32
);
475 if (nand
->bus_width
== 8)
477 uint8_t *data8
= data
;
478 *data8
= data32
& 0xff;
480 else if (nand
->bus_width
== 16)
482 uint16_t *data16
= data
;
483 *data16
= data32
& 0xffff;
487 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
488 return ERROR_NAND_OPERATION_FAILED
;
495 static int lpc3180_write_page(struct nand_device
*nand
, uint32_t page
, uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
497 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
498 struct target
*target
= lpc3180_info
->target
;
501 uint8_t *page_buffer
;
503 if (target
->state
!= TARGET_HALTED
)
505 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
506 return ERROR_NAND_OPERATION_FAILED
;
509 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
511 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
512 return ERROR_NAND_OPERATION_FAILED
;
514 else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
517 int quarter
, num_quarters
;
521 LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
522 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
525 if (oob
&& (oob_size
> 24))
527 LOG_ERROR("LPC3180 MLC controller can't write more "
528 "than 6 bytes for each quarter's OOB data");
529 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
532 if (data_size
> (uint32_t)nand
->page_size
)
534 LOG_ERROR("data size exceeds page size");
535 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
538 /* MLC_CMD = sequential input */
539 target_write_u32(target
, 0x200b8000, NAND_CMD_SEQIN
);
541 page_buffer
= malloc(512);
542 oob_buffer
= malloc(6);
544 if (nand
->page_size
== 512)
546 /* MLC_ADDR = 0x0 (one column cycle) */
547 target_write_u32(target
, 0x200b8004, 0x0);
550 target_write_u32(target
, 0x200b8004, page
& 0xff);
551 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
553 if (nand
->address_cycles
== 4)
554 target_write_u32(target
, 0x200b8004, (page
>> 16) & 0xff);
558 /* MLC_ADDR = 0x0 (two column cycles) */
559 target_write_u32(target
, 0x200b8004, 0x0);
560 target_write_u32(target
, 0x200b8004, 0x0);
563 target_write_u32(target
, 0x200b8004, page
& 0xff);
564 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
567 /* when using the MLC controller, we have to treat a large page device
568 * as being made out of four quarters, each the size of a small page device
570 num_quarters
= (nand
->page_size
== 2048) ? 4 : 1;
572 for (quarter
= 0; quarter
< num_quarters
; quarter
++)
574 int thisrun_data_size
= (data_size
> 512) ? 512 : data_size
;
575 int thisrun_oob_size
= (oob_size
> 6) ? 6 : oob_size
;
577 memset(page_buffer
, 0xff, 512);
580 memcpy(page_buffer
, data
, thisrun_data_size
);
581 data_size
-= thisrun_data_size
;
582 data
+= thisrun_data_size
;
585 memset(oob_buffer
, 0xff, 6);
588 memcpy(oob_buffer
, oob
, thisrun_oob_size
);
589 oob_size
-= thisrun_oob_size
;
590 oob
+= thisrun_oob_size
;
593 /* write MLC_ECC_ENC_REG to start encode cycle */
594 target_write_u32(target
, 0x200b8008, 0x0);
596 target_write_memory(target
, 0x200a8000,
597 4, 128, page_buffer
);
598 target_write_memory(target
, 0x200a8000,
601 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
602 target_write_u32(target
, 0x200b8010, 0x0);
604 if (!lpc3180_controller_ready(nand
, 1000))
606 LOG_ERROR("timeout while waiting for completion of auto encode cycle");
607 return ERROR_NAND_OPERATION_FAILED
;
611 /* MLC_CMD = auto program command */
612 target_write_u32(target
, 0x200b8000, NAND_CMD_PAGEPROG
);
614 if ((retval
= nand_read_status(nand
, &status
)) != ERROR_OK
)
616 LOG_ERROR("couldn't read status");
617 return ERROR_NAND_OPERATION_FAILED
;
620 if (status
& NAND_STATUS_FAIL
)
622 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status
);
623 return ERROR_NAND_OPERATION_FAILED
;
629 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
632 /**********************************************************************
633 * Write both SLC NAND flash page main area and spare area.
635 * ------------------------------------------
636 * | 512 bytes main | 16 bytes spare |
637 * ------------------------------------------
639 * ------------------------------------------
640 * | 2048 bytes main | 64 bytes spare |
641 * ------------------------------------------
642 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
643 * data is written to the 3rd word of the spare area. The ECC
644 * generated for the 2nd 256-byte data is written to the 4th word
645 * of the spare area. The ECC generated for the 3rd 256-byte data is
646 * written to the 7th word of the spare area. The ECC generated
647 * for the 4th 256-byte data is written to the 8th word of the
648 * spare area and so on.
650 **********************************************************************/
652 int retval
,i
=0,target_mem_base
;
653 uint8_t *ecc_flash_buffer
;
654 struct working_area
*pworking_area
;
657 if(lpc3180_info
->is_bulk
){
660 /*if oob only mode is active original method is used as SLC controller hangs during DMA interworking. Anyway the code supports the oob only mode below. */
661 return nand_write_page_raw(nand
, page
, data
, data_size
, oob
, oob_size
);
663 retval
= nand_page_command(nand
, page
, NAND_CMD_SEQIN
, !data
);
664 if (ERROR_OK
!= retval
)
667 /* allocate a working area */
668 if (target
->working_area_size
< (uint32_t) nand
->page_size
+ 0x200){
669 LOG_ERROR("Reserve at least 0x%x physical target working area",nand
->page_size
+ 0x200);
670 return ERROR_FLASH_OPERATION_FAILED
;
672 if (target
->working_area_phys
%4){
673 LOG_ERROR("Reserve the physical target working area at word boundary");
674 return ERROR_FLASH_OPERATION_FAILED
;
676 if (target_alloc_working_area(target
, target
->working_area_size
, &pworking_area
) != ERROR_OK
)
678 LOG_ERROR("no working area specified, can't read LPC internal flash");
679 return ERROR_FLASH_OPERATION_FAILED
;
681 target_mem_base
= target
->working_area_phys
;
684 if (nand
->page_size
== 2048)
686 page_buffer
= malloc(2048);
690 page_buffer
= malloc(512);
693 ecc_flash_buffer
= malloc(64);
695 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA write to SLC, WIDTH = bus_width) */
696 target_write_u32(target
, 0x20020014, 0x3c);
699 /* set DMA LLI-s in target memory and in DMA*/
700 for(i
=0;i
<nand
->page_size
/0x100;i
++){
703 /* -------LLI for 256 byte block---------*/
704 /* DMACC0SrcAddr = SRAM */
705 target_write_u32(target
,target_mem_base
+0+i
*32,target_mem_base
+DATA_OFFS
+i
*256 );
706 if(i
==0) target_write_u32(target
,0x31000100,target_mem_base
+DATA_OFFS
);
707 /* DMACCxDestAddr = SLC_DMA_DATA */
708 target_write_u32(target
,target_mem_base
+4+i
*32,0x20020038 );
709 if(i
==0) target_write_u32(target
,0x31000104,0x20020038 );
710 /* DMACCxLLI = next element */
711 tmp
= (target_mem_base
+(1+i
*2)*16)&0xfffffffc;
712 target_write_u32(target
,target_mem_base
+8+i
*32, tmp
);
713 if(i
==0) target_write_u32(target
,0x31000108, tmp
);
714 /* DMACCxControl = TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
715 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
716 Destination increment = 0, Terminal count interrupt enable bit = 0*/
717 target_write_u32(target
,target_mem_base
+12+i
*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
718 if(i
==0) target_write_u32(target
,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
720 /* -------LLI for 3 byte ECC---------*/
721 /* DMACC0SrcAddr = SLC_ECC*/
722 target_write_u32(target
,target_mem_base
+16+i
*32,0x20020034 );
723 /* DMACCxDestAddr = SRAM */
724 target_write_u32(target
,target_mem_base
+20+i
*32,target_mem_base
+SPARE_OFFS
+8+16*(i
>>1)+(i
%2)*4 );
725 /* DMACCxLLI = next element */
726 tmp
= (target_mem_base
+(2+i
*2)*16)&0xfffffffc;
727 target_write_u32(target
,target_mem_base
+24+i
*32, tmp
);
728 /* DMACCxControl = TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
729 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
730 Destination increment = 1, Terminal count interrupt enable bit = 0*/
731 target_write_u32(target
,target_mem_base
+28+i
*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
734 else if (data
&& oob
){
735 /* -------LLI for 512 or 2048 bytes page---------*/
736 /* DMACC0SrcAddr = SRAM */
737 target_write_u32(target
,target_mem_base
,target_mem_base
+DATA_OFFS
);
738 target_write_u32(target
,0x31000100,target_mem_base
+DATA_OFFS
);
739 /* DMACCxDestAddr = SLC_DMA_DATA */
740 target_write_u32(target
,target_mem_base
+4,0x20020038 );
741 target_write_u32(target
,0x31000104,0x20020038 );
742 /* DMACCxLLI = next element */
743 target_write_u32(target
,target_mem_base
+8, (target_mem_base
+32)&0xfffffffc );
744 target_write_u32(target
,0x31000108, (target_mem_base
+32)&0xfffffffc );
745 /* DMACCxControl = TransferSize =512 or 128, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
746 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
747 Destination increment = 0, Terminal count interrupt enable bit = 0*/
748 target_write_u32(target
,target_mem_base
+12,(nand
->page_size
==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
749 target_write_u32(target
,0x3100010c,(nand
->page_size
==2048?512:128) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
752 else if (!data
&& oob
){
756 /* -------LLI for spare area---------*/
757 /* DMACC0SrcAddr = SRAM*/
758 target_write_u32(target
,target_mem_base
+0+i
*32,target_mem_base
+SPARE_OFFS
);
759 if(i
==0) target_write_u32(target
,0x31000100,target_mem_base
+SPARE_OFFS
);
760 /* DMACCxDestAddr = SLC_DMA_DATA */
761 target_write_u32(target
,target_mem_base
+4+i
*32,0x20020038 );
762 if(i
==0) target_write_u32(target
,0x31000104,0x20020038 );
763 /* DMACCxLLI = next element = NULL */
764 target_write_u32(target
,target_mem_base
+8+i
*32, 0 );
765 if(i
==0) target_write_u32(target
,0x31000108,0 );
766 /* DMACCxControl = TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
767 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 1,
768 Destination increment = 0, Terminal count interrupt enable bit = 0*/
769 target_write_u32(target
,target_mem_base
+12+i
*32, (nand
->page_size
==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31);
770 if(i
==0) target_write_u32(target
,0x3100010c,(nand
->page_size
==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 1<<26 | 0<<27| 0<<31 );
774 memset(ecc_flash_buffer
, 0xff, 64);
776 memcpy(ecc_flash_buffer
,oob
, oob_size
);
778 target_write_memory(target
, target_mem_base
+SPARE_OFFS
, 4, 16, ecc_flash_buffer
);
781 memset(page_buffer
, 0xff, nand
->page_size
== 2048?2048:512);
782 memcpy(page_buffer
,data
, data_size
);
783 target_write_memory(target
, target_mem_base
+DATA_OFFS
, 4, nand
->page_size
== 2048?512:128, page_buffer
);
787 free(ecc_flash_buffer
);
789 /* Enable DMA after channel set up !
790 LLI only works when DMA is the flow controller!
792 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher -> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
793 target_write_u32(target
,0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
797 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
798 target_write_u32(target
, 0x20020010, 0x3);
800 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
801 target_write_u32(target
, 0x20020028, 2);
805 target_write_u32(target
, 0x20020030, (nand
->page_size
==2048?0x10:0x04));
807 target_write_u32(target
, 0x20020030, (nand
->page_size
==2048?0x840:0x210));
809 nand_write_finish(nand
);
812 if (!lpc3180_tc_ready(nand
, 1000))
814 LOG_ERROR("timeout while waiting for completion of DMA");
815 return ERROR_NAND_OPERATION_FAILED
;
818 target_free_working_area(target
,pworking_area
);
820 LOG_INFO("Page = 0x%" PRIx32
" was written.",page
);
824 return nand_write_page_raw(nand
, page
, data
, data_size
, oob
, oob_size
);
831 static int lpc3180_read_page(struct nand_device
*nand
, uint32_t page
, uint8_t *data
, uint32_t data_size
, uint8_t *oob
, uint32_t oob_size
)
833 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
834 struct target
*target
= lpc3180_info
->target
;
835 uint8_t *page_buffer
;
837 if (target
->state
!= TARGET_HALTED
)
839 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
840 return ERROR_NAND_OPERATION_FAILED
;
843 if (lpc3180_info
->selected_controller
== LPC3180_NO_CONTROLLER
)
845 LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
846 return ERROR_NAND_OPERATION_FAILED
;
848 else if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
851 uint32_t page_bytes_done
= 0;
852 uint32_t oob_bytes_done
= 0;
856 if (oob
&& (oob_size
> 6))
858 LOG_ERROR("LPC3180 MLC controller can't read more than 6 bytes of OOB data");
859 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
863 if (data_size
> (uint32_t)nand
->page_size
)
865 LOG_ERROR("data size exceeds page size");
866 return ERROR_NAND_OPERATION_NOT_SUPPORTED
;
869 if (nand
->page_size
== 2048)
871 page_buffer
= malloc(2048);
872 oob_buffer
= malloc(64);
876 page_buffer
= malloc(512);
877 oob_buffer
= malloc(16);
882 /* MLC_CMD = Read OOB
883 * we can use the READOOB command on both small and large page devices,
884 * as the controller translates the 0x50 command to a 0x0 with appropriate
885 * positioning of the serial buffer read pointer
887 target_write_u32(target
, 0x200b8000, NAND_CMD_READOOB
);
891 /* MLC_CMD = Read0 */
892 target_write_u32(target
, 0x200b8000, NAND_CMD_READ0
);
895 if (nand
->page_size
== 512)
897 /* small page device */
898 /* MLC_ADDR = 0x0 (one column cycle) */
899 target_write_u32(target
, 0x200b8004, 0x0);
902 target_write_u32(target
, 0x200b8004, page
& 0xff);
903 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
905 if (nand
->address_cycles
== 4)
906 target_write_u32(target
, 0x200b8004, (page
>> 16) & 0xff);
910 /* large page device */
911 /* MLC_ADDR = 0x0 (two column cycles) */
912 target_write_u32(target
, 0x200b8004, 0x0);
913 target_write_u32(target
, 0x200b8004, 0x0);
916 target_write_u32(target
, 0x200b8004, page
& 0xff);
917 target_write_u32(target
, 0x200b8004, (page
>> 8) & 0xff);
919 /* MLC_CMD = Read Start */
920 target_write_u32(target
, 0x200b8000, NAND_CMD_READSTART
);
923 while (page_bytes_done
< (uint32_t)nand
->page_size
)
925 /* MLC_ECC_AUTO_DEC_REG = dummy */
926 target_write_u32(target
, 0x200b8014, 0xaa55aa55);
928 if (!lpc3180_controller_ready(nand
, 1000))
930 LOG_ERROR("timeout while waiting for completion of auto decode cycle");
931 return ERROR_NAND_OPERATION_FAILED
;
934 target_read_u32(target
, 0x200b8048, &mlc_isr
);
940 LOG_ERROR("uncorrectable error detected: 0x%2.2x", (unsigned)mlc_isr
);
941 return ERROR_NAND_OPERATION_FAILED
;
944 LOG_WARNING("%i symbol error detected and corrected", ((int)(((mlc_isr
& 0x30) >> 4) + 1)));
949 target_read_memory(target
, 0x200a8000, 4, 128, page_buffer
+ page_bytes_done
);
954 target_read_memory(target
, 0x200a8000, 4, 4, oob_buffer
+ oob_bytes_done
);
957 page_bytes_done
+= 512;
958 oob_bytes_done
+= 16;
962 memcpy(data
, page_buffer
, data_size
);
965 memcpy(oob
, oob_buffer
, oob_size
);
970 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
973 /**********************************************************************
974 * Read both SLC NAND flash page main area and spare area.
976 * ------------------------------------------
977 * | 512 bytes main | 16 bytes spare |
978 * ------------------------------------------
980 * ------------------------------------------
981 * | 2048 bytes main | 64 bytes spare |
982 * ------------------------------------------
983 * If DMA & ECC enabled, then the ECC generated for the 1st 256-byte
984 * data is compared with the 3rd word of the spare area. The ECC
985 * generated for the 2nd 256-byte data is compared with the 4th word
986 * of the spare area. The ECC generated for the 3rd 256-byte data is
987 * compared with the 7th word of the spare area. The ECC generated
988 * for the 4th 256-byte data is compared with the 8th word of the
989 * spare area and so on.
991 **********************************************************************/
993 int retval
,i
,target_mem_base
;
994 uint8_t *ecc_hw_buffer
;
995 uint8_t *ecc_flash_buffer
;
996 struct working_area
*pworking_area
;
998 if(lpc3180_info
->is_bulk
){
1000 /* read always the data and also oob areas*/
1002 retval
= nand_page_command(nand
, page
, NAND_CMD_READ0
, 0);
1003 if (ERROR_OK
!= retval
)
1006 /* allocate a working area */
1007 if (target
->working_area_size
< (uint32_t) nand
->page_size
+ 0x200){
1008 LOG_ERROR("Reserve at least 0x%x physical target working area",nand
->page_size
+ 0x200);
1009 return ERROR_FLASH_OPERATION_FAILED
;
1011 if (target
->working_area_phys
%4){
1012 LOG_ERROR("Reserve the physical target working area at word boundary");
1013 return ERROR_FLASH_OPERATION_FAILED
;
1015 if (target_alloc_working_area(target
, target
->working_area_size
, &pworking_area
) != ERROR_OK
)
1017 LOG_ERROR("no working area specified, can't read LPC internal flash");
1018 return ERROR_FLASH_OPERATION_FAILED
;
1020 target_mem_base
= target
->working_area_phys
;
1022 if (nand
->page_size
== 2048)
1024 page_buffer
= malloc(2048);
1028 page_buffer
= malloc(512);
1031 ecc_hw_buffer
= malloc(32);
1032 ecc_flash_buffer
= malloc(64);
1034 /* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled, DMA read from SLC, WIDTH = bus_width) */
1035 target_write_u32(target
, 0x20020014, 0x3e);
1037 /* set DMA LLI-s in target memory and in DMA*/
1038 for(i
=0;i
<nand
->page_size
/0x100;i
++){
1040 /* -------LLI for 256 byte block---------*/
1041 /* DMACC0SrcAddr = SLC_DMA_DATA*/
1042 target_write_u32(target
,target_mem_base
+0+i
*32,0x20020038 );
1043 if(i
==0) target_write_u32(target
,0x31000100,0x20020038 );
1044 /* DMACCxDestAddr = SRAM */
1045 target_write_u32(target
,target_mem_base
+4+i
*32,target_mem_base
+DATA_OFFS
+i
*256 );
1046 if(i
==0) target_write_u32(target
,0x31000104,target_mem_base
+DATA_OFFS
);
1047 /* DMACCxLLI = next element */
1048 tmp
= (target_mem_base
+(1+i
*2)*16)&0xfffffffc;
1049 target_write_u32(target
,target_mem_base
+8+i
*32, tmp
);
1050 if(i
==0) target_write_u32(target
,0x31000108, tmp
);
1051 /* DMACCxControl = TransferSize =64, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1052 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1053 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1054 target_write_u32(target
,target_mem_base
+12+i
*32,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1055 if(i
==0) target_write_u32(target
,0x3100010c,0x40 | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1057 /* -------LLI for 3 byte ECC---------*/
1058 /* DMACC0SrcAddr = SLC_ECC*/
1059 target_write_u32(target
,target_mem_base
+16+i
*32,0x20020034 );
1060 /* DMACCxDestAddr = SRAM */
1061 target_write_u32(target
,target_mem_base
+20+i
*32,target_mem_base
+ECC_OFFS
+i
*4 );
1062 /* DMACCxLLI = next element */
1063 tmp
= (target_mem_base
+(2+i
*2)*16)&0xfffffffc;
1064 target_write_u32(target
,target_mem_base
+24+i
*32, tmp
);
1065 /* DMACCxControl = TransferSize =1, Source burst size =4, Destination burst size = 4, Source transfer width = 32 bit,
1066 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1067 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1068 target_write_u32(target
,target_mem_base
+28+i
*32,0x01 | 1<<12 | 1<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1073 /* -------LLI for spare area---------*/
1074 /* DMACC0SrcAddr = SLC_DMA_DATA*/
1075 target_write_u32(target
,target_mem_base
+0+i
*32,0x20020038 );
1076 /* DMACCxDestAddr = SRAM */
1077 target_write_u32(target
,target_mem_base
+4+i
*32,target_mem_base
+SPARE_OFFS
);
1078 /* DMACCxLLI = next element = NULL */
1079 target_write_u32(target
,target_mem_base
+8+i
*32, 0 );
1080 /* DMACCxControl = TransferSize =16 for large page or 4 for small page, Source burst size =16, Destination burst size = 16, Source transfer width = 32 bit,
1081 Destination transfer width = 32 bit, Source AHB master select = M0, Destination AHB master select = M0, Source increment = 0,
1082 Destination increment = 1, Terminal count interrupt enable bit = 0*/
1083 target_write_u32(target
,target_mem_base
+12+i
*32, (nand
->page_size
==2048?0x10:0x04) | 3<<12 | 3<<15 | 2<<18 | 2<<21 | 0<<24 | 0<<25 | 0<<26 | 1<<27| 0<<31);
1085 /* Enable DMA after channel set up !
1086 LLI only works when DMA is the flow controller!
1088 /* DMACCxConfig= E=1, SrcPeripheral = 1 (SLC), DestPeripheral = 1 (SLC), FlowCntrl = 2 (Pher-> Mem, DMA), IE = 0, ITC = 0, L= 0, H=0*/
1089 target_write_u32(target
,0x31000110, 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14 | 0<<15 | 0<<16 | 0<<18);
1092 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
1093 target_write_u32(target
, 0x20020010, 0x3);
1095 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
1096 target_write_u32(target
, 0x20020028, 2);
1099 target_write_u32(target
, 0x20020030, (nand
->page_size
==2048?0x840:0x210));
1101 if (!lpc3180_tc_ready(nand
, 1000))
1103 LOG_ERROR("timeout while waiting for completion of DMA");
1105 free(ecc_hw_buffer
);
1106 free(ecc_flash_buffer
);
1107 target_free_working_area(target
,pworking_area
);
1108 return ERROR_NAND_OPERATION_FAILED
;
1112 target_read_memory(target
, target_mem_base
+DATA_OFFS
, 4, nand
->page_size
== 2048?512:128, page_buffer
);
1113 memcpy(data
, page_buffer
, data_size
);
1115 LOG_INFO("Page = 0x%" PRIx32
" was read.",page
);
1117 /* check hw generated ECC for each 256 bytes block with the saved ECC in flash spare area*/
1118 int idx
= nand
->page_size
/0x200 ;
1119 target_read_memory(target
, target_mem_base
+SPARE_OFFS
, 4, 16, ecc_flash_buffer
);
1120 target_read_memory(target
, target_mem_base
+ECC_OFFS
, 4, 8, ecc_hw_buffer
);
1122 if( (0x00ffffff&*(uint32_t *)(ecc_hw_buffer
+i
*8)) != (0x00ffffff&*(uint32_t *)(ecc_flash_buffer
+8+i
*16)) )
1123 LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32
,i
*2+1,page
);
1124 if( (0x00ffffff&*(uint32_t *)(ecc_hw_buffer
+4+i
*8)) != (0x00ffffff&*(uint32_t *)(ecc_flash_buffer
+12+i
*16)) )
1125 LOG_WARNING("ECC mismatch at 256 bytes size block= %d at page= 0x%" PRIx32
,i
*2+2,page
);
1130 memcpy(oob
, ecc_flash_buffer
, oob_size
);
1133 free(ecc_hw_buffer
);
1134 free(ecc_flash_buffer
);
1136 target_free_working_area(target
,pworking_area
);
1140 return nand_read_page_raw(nand
, page
, data
, data_size
, oob
, oob_size
);
1146 static int lpc3180_controller_ready(struct nand_device
*nand
, int timeout
)
1148 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
1149 struct target
*target
= lpc3180_info
->target
;
1151 if (target
->state
!= TARGET_HALTED
)
1153 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1154 return ERROR_NAND_OPERATION_FAILED
;
1157 LOG_DEBUG("lpc3180_controller_ready count start=%d", timeout
);
1161 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
1165 /* Read MLC_ISR, wait for controller to become ready */
1166 target_read_u8(target
, 0x200b8048, &status
);
1169 LOG_DEBUG("lpc3180_controller_ready count=%d",
1174 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
1178 /* Read SLC_STAT and check READY bit */
1179 target_read_u32(target
, 0x20020018, &status
);
1182 LOG_DEBUG("lpc3180_controller_ready count=%d",
1189 } while (timeout
-- > 0);
1194 static int lpc3180_nand_ready(struct nand_device
*nand
, int timeout
)
1196 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
1197 struct target
*target
= lpc3180_info
->target
;
1199 if (target
->state
!= TARGET_HALTED
)
1201 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1202 return ERROR_NAND_OPERATION_FAILED
;
1205 LOG_DEBUG("lpc3180_nand_ready count start=%d", timeout
);
1209 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
1211 uint8_t status
= 0x0;
1213 /* Read MLC_ISR, wait for NAND flash device to become ready */
1214 target_read_u8(target
, 0x200b8048, &status
);
1217 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1222 else if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
1224 uint32_t status
= 0x0;
1226 /* Read SLC_STAT and check READY bit */
1227 target_read_u32(target
, 0x20020018, &status
);
1230 LOG_DEBUG("lpc3180_nand_ready count end=%d",
1237 } while (timeout
-- > 0);
1242 static int lpc3180_tc_ready(struct nand_device
*nand
, int timeout
)
1244 struct lpc3180_nand_controller
*lpc3180_info
= nand
->controller_priv
;
1245 struct target
*target
= lpc3180_info
->target
;
1247 if (target
->state
!= TARGET_HALTED
)
1249 LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
1250 return ERROR_NAND_OPERATION_FAILED
;
1253 LOG_DEBUG("lpc3180_tc_ready count start=%d",
1258 if (lpc3180_info
->selected_controller
== LPC3180_SLC_CONTROLLER
)
1260 uint32_t status
= 0x0;
1261 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1262 target_read_u32(target
, 0x2002001c, &status
);
1265 LOG_DEBUG("lpc3180_tc_ready count=%d",
1272 } while (timeout
-- > 0);
1278 COMMAND_HANDLER(handle_lpc3180_select_command
)
1280 struct lpc3180_nand_controller
*lpc3180_info
= NULL
;
1286 if ((CMD_ARGC
< 1) || (CMD_ARGC
> 3))
1288 return ERROR_COMMAND_SYNTAX_ERROR
;
1292 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], num
);
1293 struct nand_device
*nand
= get_nand_device_by_num(num
);
1296 command_print(CMD_CTX
, "nand device '#%s' is out of bounds", CMD_ARGV
[0]);
1300 lpc3180_info
= nand
->controller_priv
;
1304 if (strcmp(CMD_ARGV
[1], "mlc") == 0)
1306 lpc3180_info
->selected_controller
= LPC3180_MLC_CONTROLLER
;
1308 else if (strcmp(CMD_ARGV
[1], "slc") == 0)
1310 lpc3180_info
->selected_controller
= LPC3180_SLC_CONTROLLER
;
1311 if (CMD_ARGC
== 3 && strcmp(CMD_ARGV
[2], "bulk") == 0){
1312 lpc3180_info
->is_bulk
= 1;
1315 lpc3180_info
->is_bulk
= 0;
1320 return ERROR_COMMAND_SYNTAX_ERROR
;
1324 if (lpc3180_info
->selected_controller
== LPC3180_MLC_CONTROLLER
)
1325 command_print(CMD_CTX
, "%s controller selected", selected
[lpc3180_info
->selected_controller
]);
1327 command_print(CMD_CTX
, lpc3180_info
->is_bulk
?"%s controller selected bulk mode is avaliable":"%s controller selected bulk mode is not avaliable", selected
[lpc3180_info
->selected_controller
]);
1334 static const struct command_registration lpc3180_exec_command_handlers
[] = {
1337 .handler
= handle_lpc3180_select_command
,
1338 .mode
= COMMAND_EXEC
,
1339 .help
= "select MLC or SLC controller (default is MLC), SLC can be set to bulk mode",
1340 .usage
= "bank_id ['mlc'|'slc' ['bulk'] ]",
1342 COMMAND_REGISTRATION_DONE
1344 static const struct command_registration lpc3180_command_handler
[] = {
1347 .mode
= COMMAND_ANY
,
1348 .help
= "LPC3180 NAND flash controller commands",
1349 .chain
= lpc3180_exec_command_handlers
,
1351 COMMAND_REGISTRATION_DONE
1354 struct nand_flash_controller lpc3180_nand_controller
= {
1356 .commands
= lpc3180_command_handler
,
1357 .nand_device_command
= lpc3180_nand_device_command
,
1358 .init
= lpc3180_init
,
1359 .reset
= lpc3180_reset
,
1360 .command
= lpc3180_command
,
1361 .address
= lpc3180_address
,
1362 .write_data
= lpc3180_write_data
,
1363 .read_data
= lpc3180_read_data
,
1364 .write_page
= lpc3180_write_page
,
1365 .read_page
= lpc3180_read_page
,
1366 .controller_ready
= lpc3180_controller_ready
,
1367 .nand_ready
= lpc3180_nand_ready
,
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