1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * Copyright (C) 2010 by Olaf Lüke (at91sam3s* support) *
6 * olaf@uni-paderborn.de *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
17 * GNU General public License for more details. *
19 * You should have received a copy of the GNU General public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ****************************************************************************/
25 /* Some of the the lower level code was based on code supplied by
26 * ATMEL under this copyright. */
28 /* BEGIN ATMEL COPYRIGHT */
29 /* ----------------------------------------------------------------------------
30 * ATMEL Microcontroller Software Support
31 * ----------------------------------------------------------------------------
32 * Copyright (c) 2009, Atmel Corporation
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions are met:
39 * - Redistributions of source code must retain the above copyright notice,
40 * this list of conditions and the disclaimer below.
42 * Atmel's name may not be used to endorse or promote products derived from
43 * this software without specific prior written permission.
45 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
47 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
48 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
49 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
50 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
51 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
52 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
53 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
54 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
55 * ----------------------------------------------------------------------------
57 /* END ATMEL COPYRIGHT */
65 #include <helper/time_support.h>
67 #define REG_NAME_WIDTH (12)
69 // at91sam3u series (has one or two flash banks)
70 #define FLASH_BANK0_BASE_U 0x00080000
71 #define FLASH_BANK1_BASE_U 0x00100000
73 // at91sam3s series (has always one flash bank)
74 #define FLASH_BANK_BASE_S 0x00400000
76 // at91sam3n series (has always one flash bank)
77 #define FLASH_BANK_BASE_N 0x00400000
79 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
80 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
81 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
82 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
83 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
84 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
85 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
86 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
87 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
88 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
89 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
90 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
91 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
92 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
93 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
94 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
95 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
96 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
98 #define offset_EFC_FMR 0
99 #define offset_EFC_FCR 4
100 #define offset_EFC_FSR 8
101 #define offset_EFC_FRR 12
104 extern struct flash_driver at91sam3_flash
;
107 _tomhz(uint32_t freq_hz
)
111 f
= ((float)(freq_hz
)) / 1000000.0;
115 // How the chip is configured.
117 uint32_t unique_id
[4];
121 uint32_t mainosc_freq
;
131 #define SAM3_CHIPID_CIDR (0x400E0740)
132 uint32_t CHIPID_CIDR
;
133 #define SAM3_CHIPID_EXID (0x400E0744)
134 uint32_t CHIPID_EXID
;
136 #define SAM3_SUPC_CR (0x400E1210)
139 #define SAM3_PMC_BASE (0x400E0400)
140 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
142 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
144 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
146 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
148 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
150 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
152 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
154 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
156 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
158 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
160 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
162 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
164 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
166 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
171 * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
172 * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
173 * the flash wait state (FWS) should be set to 6. It seems like that the
174 * cause of the problem is not the flash itself, but the flash write
175 * buffer. Ie the wait states have to be set before writing into the
177 * Tested and confirmed with SAM3N and SAM3U
180 struct sam3_bank_private
{
182 // DANGER: THERE ARE DRAGONS HERE..
183 // NOTE: If you add more 'ghost' pointers
184 // be aware that you must *manually* update
185 // these pointers in the function sam3_GetDetails()
186 // See the comment "Here there be dragons"
188 // so we can find the chip we belong to
189 struct sam3_chip
*pChip
;
190 // so we can find the orginal bank pointer
191 struct flash_bank
*pBank
;
192 unsigned bank_number
;
193 uint32_t controller_address
;
194 uint32_t base_address
;
195 uint32_t flash_wait_states
;
199 unsigned sector_size
;
203 struct sam3_chip_details
{
204 // THERE ARE DRAGONS HERE..
205 // note: If you add pointers here
206 // becareful about them as they
207 // may need to be updated inside
208 // the function: "sam3_GetDetails()
209 // which copy/overwrites the
210 // 'runtime' copy of this structure
211 uint32_t chipid_cidr
;
215 #define SAM3_N_NVM_BITS 3
216 unsigned gpnvm
[SAM3_N_NVM_BITS
];
217 unsigned total_flash_size
;
218 unsigned total_sram_size
;
220 #define SAM3_MAX_FLASH_BANKS 2
221 // these are "initialized" from the global const data
222 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
227 struct sam3_chip
*next
;
230 // this is "initialized" from the global const structure
231 struct sam3_chip_details details
;
232 struct target
*target
;
237 struct sam3_reg_list
{
238 uint32_t address
; size_t struct_offset
; const char *name
;
239 void (*explain_func
)(struct sam3_chip
*pInfo
);
243 static struct sam3_chip
*all_sam3_chips
;
245 static struct sam3_chip
*
246 get_current_sam3(struct command_context
*cmd_ctx
)
249 static struct sam3_chip
*p
;
251 t
= get_current_target(cmd_ctx
);
253 command_print(cmd_ctx
, "No current target?");
259 // this should not happen
260 // the command is not registered until the chip is created?
261 command_print(cmd_ctx
, "No SAM3 chips exist?");
266 if (p
->target
== t
) {
271 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
276 // these are used to *initialize* the "pChip->details" structure.
277 static const struct sam3_chip_details all_sam3_details
[] = {
278 // Start at91sam3u* series
280 .chipid_cidr
= 0x28100960,
281 .name
= "at91sam3u4e",
282 .total_flash_size
= 256 * 1024,
283 .total_sram_size
= 52 * 1024,
287 // System boots at address 0x0
288 // gpnvm[1] = selects boot code
290 // boot is via "SAMBA" (rom)
293 // Selection is via gpnvm[2]
296 // NOTE: banks 0 & 1 switch places
298 // Bank0 is the boot rom
300 // Bank1 is the boot rom
309 .base_address
= FLASH_BANK0_BASE_U
,
310 .controller_address
= 0x400e0800,
311 .flash_wait_states
= 6, /* workaround silicon bug */
313 .size_bytes
= 128 * 1024,
325 .base_address
= FLASH_BANK1_BASE_U
,
326 .controller_address
= 0x400e0a00,
327 .flash_wait_states
= 6, /* workaround silicon bug */
329 .size_bytes
= 128 * 1024,
338 .chipid_cidr
= 0x281a0760,
339 .name
= "at91sam3u2e",
340 .total_flash_size
= 128 * 1024,
341 .total_sram_size
= 36 * 1024,
345 // System boots at address 0x0
346 // gpnvm[1] = selects boot code
348 // boot is via "SAMBA" (rom)
351 // Selection is via gpnvm[2]
360 .base_address
= FLASH_BANK0_BASE_U
,
361 .controller_address
= 0x400e0800,
362 .flash_wait_states
= 6, /* workaround silicon bug */
364 .size_bytes
= 128 * 1024,
378 .chipid_cidr
= 0x28190560,
379 .name
= "at91sam3u1e",
380 .total_flash_size
= 64 * 1024,
381 .total_sram_size
= 20 * 1024,
385 // System boots at address 0x0
386 // gpnvm[1] = selects boot code
388 // boot is via "SAMBA" (rom)
391 // Selection is via gpnvm[2]
402 .base_address
= FLASH_BANK0_BASE_U
,
403 .controller_address
= 0x400e0800,
404 .flash_wait_states
= 6, /* workaround silicon bug */
406 .size_bytes
= 64 * 1024,
422 .chipid_cidr
= 0x28000960,
423 .name
= "at91sam3u4c",
424 .total_flash_size
= 256 * 1024,
425 .total_sram_size
= 52 * 1024,
429 // System boots at address 0x0
430 // gpnvm[1] = selects boot code
432 // boot is via "SAMBA" (rom)
435 // Selection is via gpnvm[2]
438 // NOTE: banks 0 & 1 switch places
440 // Bank0 is the boot rom
442 // Bank1 is the boot rom
451 .base_address
= FLASH_BANK0_BASE_U
,
452 .controller_address
= 0x400e0800,
453 .flash_wait_states
= 6, /* workaround silicon bug */
455 .size_bytes
= 128 * 1024,
466 .base_address
= FLASH_BANK1_BASE_U
,
467 .controller_address
= 0x400e0a00,
468 .flash_wait_states
= 6, /* workaround silicon bug */
470 .size_bytes
= 128 * 1024,
479 .chipid_cidr
= 0x280a0760,
480 .name
= "at91sam3u2c",
481 .total_flash_size
= 128 * 1024,
482 .total_sram_size
= 36 * 1024,
486 // System boots at address 0x0
487 // gpnvm[1] = selects boot code
489 // boot is via "SAMBA" (rom)
492 // Selection is via gpnvm[2]
501 .base_address
= FLASH_BANK0_BASE_U
,
502 .controller_address
= 0x400e0800,
503 .flash_wait_states
= 6, /* workaround silicon bug */
505 .size_bytes
= 128 * 1024,
519 .chipid_cidr
= 0x28090560,
520 .name
= "at91sam3u1c",
521 .total_flash_size
= 64 * 1024,
522 .total_sram_size
= 20 * 1024,
526 // System boots at address 0x0
527 // gpnvm[1] = selects boot code
529 // boot is via "SAMBA" (rom)
532 // Selection is via gpnvm[2]
543 .base_address
= FLASH_BANK0_BASE_U
,
544 .controller_address
= 0x400e0800,
545 .flash_wait_states
= 6, /* workaround silicon bug */
547 .size_bytes
= 64 * 1024,
562 // Start at91sam3s* series
564 // Note: The preliminary at91sam3s datasheet says on page 302
565 // that the flash controller is at address 0x400E0800.
566 // This is _not_ the case, the controller resides at address 0x400e0a0.
568 .chipid_cidr
= 0x28A00960,
569 .name
= "at91sam3s4c",
570 .total_flash_size
= 256 * 1024,
571 .total_sram_size
= 48 * 1024,
581 .base_address
= FLASH_BANK_BASE_S
,
582 .controller_address
= 0x400e0a00,
583 .flash_wait_states
= 6, /* workaround silicon bug */
585 .size_bytes
= 256 * 1024,
601 .chipid_cidr
= 0x28900960,
602 .name
= "at91sam3s4b",
603 .total_flash_size
= 256 * 1024,
604 .total_sram_size
= 48 * 1024,
614 .base_address
= FLASH_BANK_BASE_S
,
615 .controller_address
= 0x400e0a00,
616 .flash_wait_states
= 6, /* workaround silicon bug */
618 .size_bytes
= 256 * 1024,
633 .chipid_cidr
= 0x28800960,
634 .name
= "at91sam3s4a",
635 .total_flash_size
= 256 * 1024,
636 .total_sram_size
= 48 * 1024,
646 .base_address
= FLASH_BANK_BASE_S
,
647 .controller_address
= 0x400e0a00,
648 .flash_wait_states
= 6, /* workaround silicon bug */
650 .size_bytes
= 256 * 1024,
665 .chipid_cidr
= 0x28AA0760,
666 .name
= "at91sam3s2c",
667 .total_flash_size
= 128 * 1024,
668 .total_sram_size
= 32 * 1024,
678 .base_address
= FLASH_BANK_BASE_S
,
679 .controller_address
= 0x400e0a00,
680 .flash_wait_states
= 6, /* workaround silicon bug */
682 .size_bytes
= 128 * 1024,
697 .chipid_cidr
= 0x289A0760,
698 .name
= "at91sam3s2b",
699 .total_flash_size
= 128 * 1024,
700 .total_sram_size
= 32 * 1024,
710 .base_address
= FLASH_BANK_BASE_S
,
711 .controller_address
= 0x400e0a00,
712 .flash_wait_states
= 6, /* workaround silicon bug */
714 .size_bytes
= 128 * 1024,
729 .chipid_cidr
= 0x288A0760,
730 .name
= "at91sam3s2a",
731 .total_flash_size
= 128 * 1024,
732 .total_sram_size
= 32 * 1024,
742 .base_address
= FLASH_BANK_BASE_S
,
743 .controller_address
= 0x400e0a00,
744 .flash_wait_states
= 6, /* workaround silicon bug */
746 .size_bytes
= 128 * 1024,
761 .chipid_cidr
= 0x28A90560,
762 .name
= "at91sam3s1c",
763 .total_flash_size
= 64 * 1024,
764 .total_sram_size
= 16 * 1024,
774 .base_address
= FLASH_BANK_BASE_S
,
775 .controller_address
= 0x400e0a00,
776 .flash_wait_states
= 6, /* workaround silicon bug */
778 .size_bytes
= 64 * 1024,
793 .chipid_cidr
= 0x28990560,
794 .name
= "at91sam3s1b",
795 .total_flash_size
= 64 * 1024,
796 .total_sram_size
= 16 * 1024,
806 .base_address
= FLASH_BANK_BASE_S
,
807 .controller_address
= 0x400e0a00,
808 .flash_wait_states
= 6, /* workaround silicon bug */
810 .size_bytes
= 64 * 1024,
825 .chipid_cidr
= 0x28890560,
826 .name
= "at91sam3s1a",
827 .total_flash_size
= 64 * 1024,
828 .total_sram_size
= 16 * 1024,
838 .base_address
= FLASH_BANK_BASE_S
,
839 .controller_address
= 0x400e0a00,
840 .flash_wait_states
= 6, /* workaround silicon bug */
842 .size_bytes
= 64 * 1024,
857 // Start at91sam3n* series
859 .chipid_cidr
= 0x29540960,
860 .name
= "at91sam3n4c",
861 .total_flash_size
= 256 * 1024,
862 .total_sram_size
= 24 * 1024,
866 // System boots at address 0x0
867 // gpnvm[1] = selects boot code
869 // boot is via "SAMBA" (rom)
872 // Selection is via gpnvm[2]
875 // NOTE: banks 0 & 1 switch places
877 // Bank0 is the boot rom
879 // Bank1 is the boot rom
888 .base_address
= FLASH_BANK_BASE_N
,
889 .controller_address
= 0x400e0A00,
890 .flash_wait_states
= 6, /* workaround silicon bug */
892 .size_bytes
= 256 * 1024,
894 .sector_size
= 16384,
908 .chipid_cidr
= 0x29440960,
909 .name
= "at91sam3n4b",
910 .total_flash_size
= 256 * 1024,
911 .total_sram_size
= 24 * 1024,
915 // System boots at address 0x0
916 // gpnvm[1] = selects boot code
918 // boot is via "SAMBA" (rom)
921 // Selection is via gpnvm[2]
924 // NOTE: banks 0 & 1 switch places
926 // Bank0 is the boot rom
928 // Bank1 is the boot rom
937 .base_address
= FLASH_BANK_BASE_N
,
938 .controller_address
= 0x400e0A00,
939 .flash_wait_states
= 6, /* workaround silicon bug */
941 .size_bytes
= 256 * 1024,
943 .sector_size
= 16384,
957 .chipid_cidr
= 0x29340960,
958 .name
= "at91sam3n4a",
959 .total_flash_size
= 256 * 1024,
960 .total_sram_size
= 24 * 1024,
964 // System boots at address 0x0
965 // gpnvm[1] = selects boot code
967 // boot is via "SAMBA" (rom)
970 // Selection is via gpnvm[2]
973 // NOTE: banks 0 & 1 switch places
975 // Bank0 is the boot rom
977 // Bank1 is the boot rom
986 .base_address
= FLASH_BANK_BASE_N
,
987 .controller_address
= 0x400e0A00,
988 .flash_wait_states
= 6, /* workaround silicon bug */
990 .size_bytes
= 256 * 1024,
992 .sector_size
= 16384,
1006 .chipid_cidr
= 0x29590760,
1007 .name
= "at91sam3n2c",
1008 .total_flash_size
= 128 * 1024,
1009 .total_sram_size
= 16 * 1024,
1013 // System boots at address 0x0
1014 // gpnvm[1] = selects boot code
1016 // boot is via "SAMBA" (rom)
1018 // boot is via FLASH
1019 // Selection is via gpnvm[2]
1022 // NOTE: banks 0 & 1 switch places
1024 // Bank0 is the boot rom
1026 // Bank1 is the boot rom
1035 .base_address
= FLASH_BANK_BASE_N
,
1036 .controller_address
= 0x400e0A00,
1037 .flash_wait_states
= 6, /* workaround silicon bug */
1039 .size_bytes
= 128 * 1024,
1041 .sector_size
= 16384,
1055 .chipid_cidr
= 0x29490760,
1056 .name
= "at91sam3n2b",
1057 .total_flash_size
= 128 * 1024,
1058 .total_sram_size
= 16 * 1024,
1062 // System boots at address 0x0
1063 // gpnvm[1] = selects boot code
1065 // boot is via "SAMBA" (rom)
1067 // boot is via FLASH
1068 // Selection is via gpnvm[2]
1071 // NOTE: banks 0 & 1 switch places
1073 // Bank0 is the boot rom
1075 // Bank1 is the boot rom
1084 .base_address
= FLASH_BANK_BASE_N
,
1085 .controller_address
= 0x400e0A00,
1086 .flash_wait_states
= 6, /* workaround silicon bug */
1088 .size_bytes
= 128 * 1024,
1090 .sector_size
= 16384,
1104 .chipid_cidr
= 0x29390760,
1105 .name
= "at91sam3n2a",
1106 .total_flash_size
= 128 * 1024,
1107 .total_sram_size
= 16 * 1024,
1111 // System boots at address 0x0
1112 // gpnvm[1] = selects boot code
1114 // boot is via "SAMBA" (rom)
1116 // boot is via FLASH
1117 // Selection is via gpnvm[2]
1120 // NOTE: banks 0 & 1 switch places
1122 // Bank0 is the boot rom
1124 // Bank1 is the boot rom
1133 .base_address
= FLASH_BANK_BASE_N
,
1134 .controller_address
= 0x400e0A00,
1135 .flash_wait_states
= 6, /* workaround silicon bug */
1137 .size_bytes
= 128 * 1024,
1139 .sector_size
= 16384,
1153 .chipid_cidr
= 0x29580560,
1154 .name
= "at91sam3n1c",
1155 .total_flash_size
= 64 * 1024,
1156 .total_sram_size
= 8 * 1024,
1160 // System boots at address 0x0
1161 // gpnvm[1] = selects boot code
1163 // boot is via "SAMBA" (rom)
1165 // boot is via FLASH
1166 // Selection is via gpnvm[2]
1169 // NOTE: banks 0 & 1 switch places
1171 // Bank0 is the boot rom
1173 // Bank1 is the boot rom
1182 .base_address
= FLASH_BANK_BASE_N
,
1183 .controller_address
= 0x400e0A00,
1184 .flash_wait_states
= 6, /* workaround silicon bug */
1186 .size_bytes
= 64 * 1024,
1188 .sector_size
= 16384,
1202 .chipid_cidr
= 0x29480560,
1203 .name
= "at91sam3n1b",
1204 .total_flash_size
= 64 * 1024,
1205 .total_sram_size
= 8 * 1024,
1209 // System boots at address 0x0
1210 // gpnvm[1] = selects boot code
1212 // boot is via "SAMBA" (rom)
1214 // boot is via FLASH
1215 // Selection is via gpnvm[2]
1218 // NOTE: banks 0 & 1 switch places
1220 // Bank0 is the boot rom
1222 // Bank1 is the boot rom
1231 .base_address
= FLASH_BANK_BASE_N
,
1232 .controller_address
= 0x400e0A00,
1233 .flash_wait_states
= 6, /* workaround silicon bug */
1235 .size_bytes
= 64 * 1024,
1237 .sector_size
= 16384,
1251 .chipid_cidr
= 0x29380560,
1252 .name
= "at91sam3n1a",
1253 .total_flash_size
= 64 * 1024,
1254 .total_sram_size
= 8 * 1024,
1258 // System boots at address 0x0
1259 // gpnvm[1] = selects boot code
1261 // boot is via "SAMBA" (rom)
1263 // boot is via FLASH
1264 // Selection is via gpnvm[2]
1267 // NOTE: banks 0 & 1 switch places
1269 // Bank0 is the boot rom
1271 // Bank1 is the boot rom
1280 .base_address
= FLASH_BANK_BASE_N
,
1281 .controller_address
= 0x400e0A00,
1282 .flash_wait_states
= 6, /* workaround silicon bug */
1284 .size_bytes
= 64 * 1024,
1286 .sector_size
= 16384,
1307 /***********************************************************************
1308 **********************************************************************
1309 **********************************************************************
1310 **********************************************************************
1311 **********************************************************************
1312 **********************************************************************/
1313 /* *ATMEL* style code - from the SAM3 driver code */
1316 * Get the current status of the EEFC and
1317 * the value of some status bits (LOCKE, PROGE).
1318 * @param pPrivate - info about the bank
1319 * @param v - result goes here
1322 EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1325 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FSR
, v
);
1326 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1328 ((unsigned int)((*v
>> 2) & 1)),
1329 ((unsigned int)((*v
>> 1) & 1)),
1330 ((unsigned int)((*v
>> 0) & 1)));
1336 * Get the result of the last executed command.
1337 * @param pPrivate - info about the bank
1338 * @param v - result goes here
1341 EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1345 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FRR
, &rv
);
1349 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
1354 EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
1355 unsigned command
, unsigned argument
)
1364 // Check command & argument
1367 case AT91C_EFC_FCMD_WP
:
1368 case AT91C_EFC_FCMD_WPL
:
1369 case AT91C_EFC_FCMD_EWP
:
1370 case AT91C_EFC_FCMD_EWPL
:
1371 // case AT91C_EFC_FCMD_EPL:
1372 // case AT91C_EFC_FCMD_EPA:
1373 case AT91C_EFC_FCMD_SLB
:
1374 case AT91C_EFC_FCMD_CLB
:
1375 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
1376 if (argument
>= n
) {
1377 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
1381 case AT91C_EFC_FCMD_SFB
:
1382 case AT91C_EFC_FCMD_CFB
:
1383 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1384 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1385 pPrivate
->pChip
->details
.n_gpnvms
);
1389 case AT91C_EFC_FCMD_GETD
:
1390 case AT91C_EFC_FCMD_EA
:
1391 case AT91C_EFC_FCMD_GLB
:
1392 case AT91C_EFC_FCMD_GFB
:
1393 case AT91C_EFC_FCMD_STUI
:
1394 case AT91C_EFC_FCMD_SPUI
:
1395 if (argument
!= 0) {
1396 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
1400 LOG_ERROR("Unknown command %d", command
);
1404 if (command
== AT91C_EFC_FCMD_SPUI
) {
1405 // this is a very special situation.
1406 // Situation (1) - error/retry - see below
1407 // And we are being called recursively
1408 // Situation (2) - normal, finished reading unique id
1410 // it should be "ready"
1411 EFC_GetStatus(pPrivate
, &v
);
1417 // we have done this before
1418 // the controller is not responding.
1419 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate
->bank_number
);
1423 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1424 pPrivate
->bank_number
);
1425 // we do that by issuing the *STOP* command
1426 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
1427 // above is recursive, and further recursion is blocked by
1428 // if (command == AT91C_EFC_FCMD_SPUI) above
1434 v
= (0x5A << 24) | (argument
<< 8) | command
;
1435 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
1436 r
= target_write_u32(pPrivate
->pBank
->target
,
1437 pPrivate
->controller_address
+ offset_EFC_FCR
,
1439 if (r
!= ERROR_OK
) {
1440 LOG_DEBUG("Error Write failed");
1446 * Performs the given command and wait until its completion (or an error).
1447 * @param pPrivate - info about the bank
1448 * @param command - Command to perform.
1449 * @param argument - Optional command argument.
1450 * @param status - put command status bits here
1453 EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
1461 long long ms_now
, ms_end
;
1468 r
= EFC_StartCommand(pPrivate
, command
, argument
);
1469 if (r
!= ERROR_OK
) {
1473 ms_end
= 500 + timeval_ms();
1477 r
= EFC_GetStatus(pPrivate
, &v
);
1478 if (r
!= ERROR_OK
) {
1481 ms_now
= timeval_ms();
1482 if (ms_now
> ms_end
) {
1484 LOG_ERROR("Command timeout");
1488 while ((v
& 1) == 0)
1493 *status
= (v
& 0x6);
1504 * Read the unique ID.
1505 * @param pPrivate - info about the bank
1506 * The unique ID is stored in the 'pPrivate' structure.
1509 FLASHD_ReadUniqueID (struct sam3_bank_private
*pPrivate
)
1515 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
1516 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
1517 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
1518 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
1521 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
1526 for (x
= 0 ; x
< 4 ; x
++) {
1527 r
= target_read_u32(pPrivate
->pChip
->target
,
1528 pPrivate
->pBank
->base
+ (x
* 4),
1533 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
1536 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
1537 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
1539 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
1540 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
1541 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
1542 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
1548 * Erases the entire flash.
1549 * @param pPrivate - the info about the bank.
1552 FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
1555 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
1561 * Gets current GPNVM state.
1562 * @param pPrivate - info about the bank.
1563 * @param gpnvm - GPNVM bit index.
1564 * @param puthere - result stored here.
1566 //------------------------------------------------------------------------------
1568 FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
1574 if (pPrivate
->bank_number
!= 0) {
1575 LOG_ERROR("GPNVM only works with Bank0");
1579 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1580 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1581 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1585 // Get GPNVMs status
1586 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
1587 if (r
!= ERROR_OK
) {
1588 LOG_ERROR("Failed");
1592 r
= EFC_GetResult(pPrivate
, &v
);
1595 // Check if GPNVM is set
1596 // get the bit and make it a 0/1
1597 *puthere
= (v
>> gpnvm
) & 1;
1607 * Clears the selected GPNVM bit.
1608 * @param pPrivate info about the bank
1609 * @param gpnvm GPNVM index.
1610 * @returns 0 if successful; otherwise returns an error code.
1613 FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1619 if (pPrivate
->bank_number
!= 0) {
1620 LOG_ERROR("GPNVM only works with Bank0");
1624 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1625 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1626 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1630 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1631 if (r
!= ERROR_OK
) {
1632 LOG_DEBUG("Failed: %d",r
);
1635 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
1636 LOG_DEBUG("End: %d",r
);
1643 * Sets the selected GPNVM bit.
1644 * @param pPrivate info about the bank
1645 * @param gpnvm GPNVM index.
1648 FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
1653 if (pPrivate
->bank_number
!= 0) {
1654 LOG_ERROR("GPNVM only works with Bank0");
1658 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
1659 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
1660 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
1664 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
1665 if (r
!= ERROR_OK
) {
1673 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
1680 * Returns a bit field (at most 64) of locked regions within a page.
1681 * @param pPrivate info about the bank
1682 * @param v where to store locked bits
1685 FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
1689 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
1690 if (r
== ERROR_OK
) {
1691 r
= EFC_GetResult(pPrivate
, v
);
1693 LOG_DEBUG("End: %d",r
);
1699 * Unlocks all the regions in the given address range.
1700 * @param pPrivate info about the bank
1701 * @param start_sector first sector to unlock
1702 * @param end_sector last (inclusive) to unlock
1706 FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
1707 unsigned start_sector
,
1708 unsigned end_sector
)
1713 uint32_t pages_per_sector
;
1715 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1717 /* Unlock all pages */
1718 while (start_sector
<= end_sector
) {
1719 pg
= start_sector
* pages_per_sector
;
1721 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
1722 if (r
!= ERROR_OK
) {
1734 * @param pPrivate - info about the bank
1735 * @param start_sector - first sector to lock
1736 * @param end_sector - last sector (inclusive) to lock
1739 FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
1740 unsigned start_sector
,
1741 unsigned end_sector
)
1745 uint32_t pages_per_sector
;
1748 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
1750 /* Lock all pages */
1751 while (start_sector
<= end_sector
) {
1752 pg
= start_sector
* pages_per_sector
;
1754 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1755 if (r
!= ERROR_OK
) {
1764 /****** END SAM3 CODE ********/
1766 /* begin helpful debug code */
1767 // print the fieldname, the field value, in dec & hex, and return field value
1769 sam3_reg_fieldname(struct sam3_chip
*pChip
,
1770 const char *regname
,
1779 // extract the field
1781 v
= v
& ((1 << width
)-1);
1791 LOG_USER_N("\t%*s: %*d [0x%0*x] ",
1792 REG_NAME_WIDTH
, regname
,
1799 static const char _unknown
[] = "unknown";
1800 static const char * const eproc_names
[] = {
1819 #define nvpsize2 nvpsize // these two tables are identical
1820 static const char * const nvpsize
[] = {
1833 "1024K bytes", // 12
1835 "2048K bytes", // 14
1840 static const char * const sramsize
[] = {
1860 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1861 { 0x19, "AT91SAM9xx Series" },
1862 { 0x29, "AT91SAM9XExx Series" },
1863 { 0x34, "AT91x34 Series" },
1864 { 0x37, "CAP7 Series" },
1865 { 0x39, "CAP9 Series" },
1866 { 0x3B, "CAP11 Series" },
1867 { 0x40, "AT91x40 Series" },
1868 { 0x42, "AT91x42 Series" },
1869 { 0x55, "AT91x55 Series" },
1870 { 0x60, "AT91SAM7Axx Series" },
1871 { 0x61, "AT91SAM7AQxx Series" },
1872 { 0x63, "AT91x63 Series" },
1873 { 0x70, "AT91SAM7Sxx Series" },
1874 { 0x71, "AT91SAM7XCxx Series" },
1875 { 0x72, "AT91SAM7SExx Series" },
1876 { 0x73, "AT91SAM7Lxx Series" },
1877 { 0x75, "AT91SAM7Xxx Series" },
1878 { 0x76, "AT91SAM7SLxx Series" },
1879 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1880 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1881 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1882 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1883 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1884 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1885 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1886 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1887 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1888 { 0x92, "AT91x92 Series" },
1889 { 0xF0, "AT75Cxx Series" },
1894 static const char * const nvptype
[] = {
1896 "romless or onchip flash", // 1
1897 "embedded flash memory", // 2
1898 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1899 "sram emulating flash", // 4
1906 static const char *_yes_or_no(uint32_t v
)
1915 static const char * const _rc_freq
[] = {
1916 "4 MHz", "8 MHz", "12 MHz", "reserved"
1920 sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
1925 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
1926 LOG_USER("(main xtal enabled: %s)",
1928 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
1929 LOG_USER("(main osc bypass: %s)",
1931 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 3, 1);
1932 LOG_USER("(onchip RC-OSC enabled: %s)",
1934 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
1935 LOG_USER("(onchip RC-OSC freq: %s)",
1938 pChip
->cfg
.rc_freq
= 0;
1942 pChip
->cfg
.rc_freq
= 0;
1945 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1948 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1951 pChip
->cfg
.rc_freq
= 12* 1000 * 1000;
1956 v
= sam3_reg_fieldname(pChip
,"MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
1957 LOG_USER("(startup clks, time= %f uSecs)",
1958 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1959 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
1960 LOG_USER("(mainosc source: %s)",
1961 v
? "external xtal" : "internal RC");
1963 v
= sam3_reg_fieldname(pChip
,"CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
1964 LOG_USER("(clock failure enabled: %s)",
1971 sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
1977 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
1980 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
1981 LOG_USER("%s", eproc_names
[v
]);
1983 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
1984 LOG_USER("%s", nvpsize
[v
]);
1986 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
1987 LOG_USER("%s", nvpsize2
[v
]);
1989 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16,4);
1990 LOG_USER("%s", sramsize
[ v
]);
1992 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
1994 for (x
= 0 ; archnames
[x
].name
; x
++) {
1995 if (v
== archnames
[x
].value
) {
1996 cp
= archnames
[x
].name
;
2003 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
2004 LOG_USER("%s", nvptype
[ v
]);
2006 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
2007 LOG_USER("(exists: %s)", _yes_or_no(v
));
2011 sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
2016 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
2017 LOG_USER("(main ready: %s)", _yes_or_no(v
));
2019 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
2021 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
2022 pChip
->cfg
.mainosc_freq
= v
;
2024 LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2026 pChip
->cfg
.slow_freq
/ 1000,
2027 pChip
->cfg
.slow_freq
% 1000);
2032 sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
2036 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
2038 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
2040 pChip
->cfg
.plla_freq
= 0;
2042 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2043 } else if (diva
== 0) {
2044 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2045 } else if (diva
== 1) {
2046 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1));
2047 LOG_USER("\tPLLA Freq: %3.03f MHz",
2048 _tomhz(pChip
->cfg
.plla_freq
));
2054 sam3_explain_mckr(struct sam3_chip
*pChip
)
2056 uint32_t css
, pres
, fin
= 0;
2058 const char *cp
= NULL
;
2060 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
2063 fin
= pChip
->cfg
.slow_freq
;
2067 fin
= pChip
->cfg
.mainosc_freq
;
2071 fin
= pChip
->cfg
.plla_freq
;
2075 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
2076 fin
= 480 * 1000 * 1000;
2080 cp
= "upll (*ERROR* UPLL is disabled)";
2088 LOG_USER("%s (%3.03f Mhz)",
2091 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
2092 switch (pres
& 0x07) {
2095 cp
= "selected clock";
2129 LOG_USER("(%s)", cp
);
2131 // sam3 has a *SINGLE* clock -
2132 // other at91 series parts have divisors for these.
2133 pChip
->cfg
.cpu_freq
= fin
;
2134 pChip
->cfg
.mclk_freq
= fin
;
2135 pChip
->cfg
.fclk_freq
= fin
;
2136 LOG_USER("\t\tResult CPU Freq: %3.03f",
2141 static struct sam3_chip
*
2142 target2sam3(struct target
*pTarget
)
2144 struct sam3_chip
*pChip
;
2146 if (pTarget
== NULL
) {
2150 pChip
= all_sam3_chips
;
2152 if (pChip
->target
== pTarget
) {
2153 break; // return below
2155 pChip
= pChip
->next
;
2163 sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
2165 // this function exists to help
2166 // keep funky offsetof() errors
2167 // and casting from causing bugs
2169 // By using prototypes - we can detect what would
2170 // be casting errors.
2172 return ((uint32_t *)(void *)(((char *)(pCfg
)) + pList
->struct_offset
));
2176 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
2177 static const struct sam3_reg_list sam3_all_regs
[] = {
2178 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
2179 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
2180 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
2181 SAM3_ENTRY(CKGR_UCKR
, NULL
),
2182 SAM3_ENTRY(PMC_FSMR
, NULL
),
2183 SAM3_ENTRY(PMC_FSPR
, NULL
),
2184 SAM3_ENTRY(PMC_IMR
, NULL
),
2185 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
2186 SAM3_ENTRY(PMC_PCK0
, NULL
),
2187 SAM3_ENTRY(PMC_PCK1
, NULL
),
2188 SAM3_ENTRY(PMC_PCK2
, NULL
),
2189 SAM3_ENTRY(PMC_PCSR
, NULL
),
2190 SAM3_ENTRY(PMC_SCSR
, NULL
),
2191 SAM3_ENTRY(PMC_SR
, NULL
),
2192 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
2193 SAM3_ENTRY(CHIPID_EXID
, NULL
),
2194 SAM3_ENTRY(SUPC_CR
, NULL
),
2196 // TERMINATE THE LIST
2204 static struct sam3_bank_private
*
2205 get_sam3_bank_private(struct flash_bank
*bank
)
2207 return (struct sam3_bank_private
*)(bank
->driver_priv
);
2211 * Given a pointer to where it goes in the structure,
2212 * determine the register name, address from the all registers table.
2214 static const struct sam3_reg_list
*
2215 sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2217 const struct sam3_reg_list
*pReg
;
2219 pReg
= &(sam3_all_regs
[0]);
2220 while (pReg
->name
) {
2221 uint32_t *pPossible
;
2223 // calculate where this one go..
2224 // it is "possibly" this register.
2226 pPossible
= ((uint32_t *)(void *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
2228 // well? Is it this register
2229 if (pPossible
== goes_here
) {
2237 // This is *TOTAL*PANIC* - we are totally screwed.
2238 LOG_ERROR("INVALID SAM3 REGISTER");
2244 sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
2246 const struct sam3_reg_list
*pReg
;
2249 pReg
= sam3_GetReg(pChip
, goes_here
);
2254 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
2255 if (r
!= ERROR_OK
) {
2256 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2257 pReg
->name
, (unsigned)(pReg
->address
), r
);
2265 sam3_ReadAllRegs(struct sam3_chip
*pChip
)
2268 const struct sam3_reg_list
*pReg
;
2270 pReg
= &(sam3_all_regs
[0]);
2271 while (pReg
->name
) {
2272 r
= sam3_ReadThisReg(pChip
,
2273 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
2274 if (r
!= ERROR_OK
) {
2275 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d",
2276 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
2288 sam3_GetInfo(struct sam3_chip
*pChip
)
2290 const struct sam3_reg_list
*pReg
;
2293 pReg
= &(sam3_all_regs
[0]);
2294 while (pReg
->name
) {
2296 LOG_DEBUG("Start: %s", pReg
->name
);
2297 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
2298 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2303 if (pReg
->explain_func
) {
2304 (*(pReg
->explain_func
))(pChip
);
2306 LOG_DEBUG("End: %s", pReg
->name
);
2309 LOG_USER(" rc-osc: %3.03f MHz", _tomhz(pChip
->cfg
.rc_freq
));
2310 LOG_USER(" mainosc: %3.03f MHz", _tomhz(pChip
->cfg
.mainosc_freq
));
2311 LOG_USER(" plla: %3.03f MHz", _tomhz(pChip
->cfg
.plla_freq
));
2312 LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip
->cfg
.cpu_freq
));
2313 LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip
->cfg
.mclk_freq
));
2316 LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2317 pChip
->cfg
.unique_id
[0],
2318 pChip
->cfg
.unique_id
[1],
2319 pChip
->cfg
.unique_id
[2],
2320 pChip
->cfg
.unique_id
[3]);
2328 sam3_erase_check(struct flash_bank
*bank
)
2333 if (bank
->target
->state
!= TARGET_HALTED
) {
2334 LOG_ERROR("Target not halted");
2335 return ERROR_TARGET_NOT_HALTED
;
2337 if (0 == bank
->num_sectors
) {
2338 LOG_ERROR("Target: not supported/not probed");
2342 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2343 for (x
= 0 ; x
< bank
->num_sectors
; x
++) {
2344 bank
->sectors
[x
].is_erased
= 1;
2352 sam3_protect_check(struct flash_bank
*bank
)
2357 struct sam3_bank_private
*pPrivate
;
2360 if (bank
->target
->state
!= TARGET_HALTED
) {
2361 LOG_ERROR("Target not halted");
2362 return ERROR_TARGET_NOT_HALTED
;
2365 pPrivate
= get_sam3_bank_private(bank
);
2367 LOG_ERROR("no private for this bank?");
2370 if (!(pPrivate
->probed
)) {
2371 return ERROR_FLASH_BANK_NOT_PROBED
;
2374 r
= FLASHD_GetLockBits(pPrivate
, &v
);
2375 if (r
!= ERROR_OK
) {
2376 LOG_DEBUG("Failed: %d",r
);
2380 for (x
= 0 ; x
< pPrivate
->nsectors
; x
++) {
2381 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
2387 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
2389 struct sam3_chip
*pChip
;
2391 pChip
= all_sam3_chips
;
2393 // is this an existing chip?
2395 if (pChip
->target
== bank
->target
) {
2398 pChip
= pChip
->next
;
2402 // this is a *NEW* chip
2403 pChip
= calloc(1, sizeof(struct sam3_chip
));
2405 LOG_ERROR("NO RAM!");
2408 pChip
->target
= bank
->target
;
2410 pChip
->next
= all_sam3_chips
;
2411 all_sam3_chips
= pChip
;
2412 pChip
->target
= bank
->target
;
2413 // assumption is this runs at 32khz
2414 pChip
->cfg
.slow_freq
= 32768;
2418 switch (bank
->base
) {
2420 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x \
2421 [at91sam3u series] or 0x%08x [at91sam3s series] or \
2422 0x%08x [at91sam3n series])",
2423 ((unsigned int)(bank
->base
)),
2424 ((unsigned int)(FLASH_BANK0_BASE_U
)),
2425 ((unsigned int)(FLASH_BANK1_BASE_U
)),
2426 ((unsigned int)(FLASH_BANK_BASE_S
)),
2427 ((unsigned int)(FLASH_BANK_BASE_N
)));
2432 case FLASH_BANK0_BASE_U
:
2433 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2434 bank
->bank_number
= 0;
2435 pChip
->details
.bank
[0].pChip
= pChip
;
2436 pChip
->details
.bank
[0].pBank
= bank
;
2438 case FLASH_BANK1_BASE_U
:
2439 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
2440 bank
->bank_number
= 1;
2441 pChip
->details
.bank
[1].pChip
= pChip
;
2442 pChip
->details
.bank
[1].pBank
= bank
;
2445 /* at91sam3s and at91sam3n series */
2446 case FLASH_BANK_BASE_S
:
2447 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
2448 bank
->bank_number
= 0;
2449 pChip
->details
.bank
[0].pChip
= pChip
;
2450 pChip
->details
.bank
[0].pBank
= bank
;
2454 // we initialize after probing.
2459 sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
2461 const struct sam3_chip_details
*pDetails
;
2462 struct sam3_chip
*pChip
;
2463 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
2467 pDetails
= all_sam3_details
;
2468 while (pDetails
->name
) {
2469 // Compare cidr without version bits
2470 if (pDetails
->chipid_cidr
== (pPrivate
->pChip
->cfg
.CHIPID_CIDR
& 0xFFFFFFE0)) {
2476 if (pDetails
->name
== NULL
) {
2477 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
2478 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
2479 // Help the victim, print details about the chip
2480 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2481 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
2482 sam3_explain_chipid_cidr(pPrivate
->pChip
);
2486 // DANGER: THERE ARE DRAGONS HERE
2488 // get our pChip - it is going
2489 // to be over-written shortly
2490 pChip
= pPrivate
->pChip
;
2492 // Note that, in reality:
2494 // pPrivate = &(pChip->details.bank[0])
2495 // or pPrivate = &(pChip->details.bank[1])
2498 // save the "bank" pointers
2499 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2500 saved_banks
[ x
] = pChip
->details
.bank
[x
].pBank
;
2503 // Overwrite the "details" structure.
2504 memcpy(&(pPrivate
->pChip
->details
),
2506 sizeof(pPrivate
->pChip
->details
));
2508 // now fix the ghosted pointers
2509 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2510 pChip
->details
.bank
[x
].pChip
= pChip
;
2511 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
2514 // update the *BANK*SIZE*
2523 _sam3_probe(struct flash_bank
*bank
, int noise
)
2527 struct sam3_bank_private
*pPrivate
;
2530 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
2531 if (bank
->target
->state
!= TARGET_HALTED
)
2533 LOG_ERROR("Target not halted");
2534 return ERROR_TARGET_NOT_HALTED
;
2537 pPrivate
= get_sam3_bank_private(bank
);
2539 LOG_ERROR("Invalid/unknown bank number");
2543 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
2544 if (r
!= ERROR_OK
) {
2550 if (pPrivate
->pChip
->probed
) {
2551 r
= sam3_GetInfo(pPrivate
->pChip
);
2553 r
= sam3_GetDetails(pPrivate
);
2555 if (r
!= ERROR_OK
) {
2559 // update the flash bank size
2560 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2561 if (bank
->base
== pPrivate
->pChip
->details
.bank
[x
].base_address
) {
2562 bank
->size
= pPrivate
->pChip
->details
.bank
[x
].size_bytes
;
2567 if (bank
->sectors
== NULL
) {
2568 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
2569 if (bank
->sectors
== NULL
) {
2570 LOG_ERROR("No memory!");
2573 bank
->num_sectors
= pPrivate
->nsectors
;
2575 for (x
= 0 ; ((int)(x
)) < bank
->num_sectors
; x
++) {
2576 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
2577 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
2579 bank
->sectors
[x
].is_erased
= -1;
2580 bank
->sectors
[x
].is_protected
= -1;
2584 pPrivate
->probed
= 1;
2586 r
= sam3_protect_check(bank
);
2587 if (r
!= ERROR_OK
) {
2591 LOG_DEBUG("Bank = %d, nbanks = %d",
2592 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
2593 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
2595 // it appears to be associated with the *last* flash bank.
2596 FLASHD_ReadUniqueID(pPrivate
);
2603 sam3_probe(struct flash_bank
*bank
)
2605 return _sam3_probe(bank
, 1);
2609 sam3_auto_probe(struct flash_bank
*bank
)
2611 return _sam3_probe(bank
, 0);
2617 sam3_erase(struct flash_bank
*bank
, int first
, int last
)
2619 struct sam3_bank_private
*pPrivate
;
2623 if (bank
->target
->state
!= TARGET_HALTED
) {
2624 LOG_ERROR("Target not halted");
2625 return ERROR_TARGET_NOT_HALTED
;
2628 r
= sam3_auto_probe(bank
);
2629 if (r
!= ERROR_OK
) {
2630 LOG_DEBUG("Here,r=%d",r
);
2634 pPrivate
= get_sam3_bank_private(bank
);
2635 if (!(pPrivate
->probed
)) {
2636 return ERROR_FLASH_BANK_NOT_PROBED
;
2639 if ((first
== 0) && ((last
+ 1)== ((int)(pPrivate
->nsectors
)))) {
2642 return FLASHD_EraseEntireBank(pPrivate
);
2644 LOG_INFO("sam3 auto-erases while programing (request ignored)");
2649 sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
2651 struct sam3_bank_private
*pPrivate
;
2655 if (bank
->target
->state
!= TARGET_HALTED
) {
2656 LOG_ERROR("Target not halted");
2657 return ERROR_TARGET_NOT_HALTED
;
2660 pPrivate
= get_sam3_bank_private(bank
);
2661 if (!(pPrivate
->probed
)) {
2662 return ERROR_FLASH_BANK_NOT_PROBED
;
2666 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2668 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
2670 LOG_DEBUG("End: r=%d",r
);
2678 sam3_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2680 if (bank
->target
->state
!= TARGET_HALTED
) {
2681 LOG_ERROR("Target not halted");
2682 return ERROR_TARGET_NOT_HALTED
;
2689 sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2694 adr
= pagenum
* pPrivate
->page_size
;
2695 adr
+= adr
+ pPrivate
->base_address
;
2697 r
= target_read_memory(pPrivate
->pChip
->target
,
2699 4, /* THIS*MUST*BE* in 32bit values */
2700 pPrivate
->page_size
/ 4,
2702 if (r
!= ERROR_OK
) {
2703 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr
));
2708 // The code below is basically this:
2710 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
2712 // Only the *CPU* can write to the flash buffer.
2713 // the DAP cannot... so - we download this 28byte thing
2714 // Run the algorithm - (below)
2715 // to program the device
2717 // ========================================
2718 // #include <stdint.h>
2722 // const uint32_t *src;
2724 // volatile uint32_t *base;
2729 // uint32_t sam3_function(struct foo *p)
2731 // volatile uint32_t *v;
2733 // const uint32_t *s;
2755 // ========================================
2759 static const uint8_t
2760 sam3_page_write_opcodes
[] = {
2761 // 24 0000 0446 mov r4, r0
2763 // 25 0002 6168 ldr r1, [r4, #4]
2765 // 26 0004 0068 ldr r0, [r0, #0]
2767 // 27 0006 A268 ldr r2, [r4, #8]
2769 // 28 @ lr needed for prologue
2771 // 30 0008 51F8043B ldr r3, [r1], #4
2772 0x51,0xf8,0x04,0x3b,
2773 // 31 000c 12F1FF32 adds r2, r2, #-1
2774 0x12,0xf1,0xff,0x32,
2775 // 32 0010 40F8043B str r3, [r0], #4
2776 0x40,0xf8,0x04,0x3b,
2777 // 33 0014 F8D1 bne .L2
2779 // 34 0016 E268 ldr r2, [r4, #12]
2781 // 35 0018 2369 ldr r3, [r4, #16]
2783 // 36 001a 5360 str r3, [r2, #4]
2785 // 37 001c 0832 adds r2, r2, #8
2788 // 39 001e 1068 ldr r0, [r2, #0]
2790 // 40 0020 10F0010F tst r0, #1
2791 0x10,0xf0,0x01,0x0f,
2792 // 41 0024 FBD0 beq .L4
2794 0x00,0xBE /* bkpt #0 */
2799 sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2803 uint32_t fmr
; /* EEFC Flash Mode Register */
2806 adr
= pagenum
* pPrivate
->page_size
;
2807 adr
+= (adr
+ pPrivate
->base_address
);
2809 /* Get flash mode register value */
2810 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
, &fmr
);
2812 LOG_DEBUG("Error Read failed: read flash mode register");
2814 /* Clear flash wait state field */
2817 /* set FWS (flash wait states) field in the FMR (flash mode register) */
2818 fmr
|= (pPrivate
->flash_wait_states
<< 8);
2820 LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr
)));
2821 r
= target_write_u32(pPrivate
->pBank
->target
, pPrivate
->controller_address
, fmr
);
2823 LOG_DEBUG("Error Write failed: set flash mode register");
2825 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2826 r
= target_write_memory(pPrivate
->pChip
->target
,
2828 4, /* THIS*MUST*BE* in 32bit values */
2829 pPrivate
->page_size
/ 4,
2831 if (r
!= ERROR_OK
) {
2832 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr
));
2836 r
= EFC_PerformCommand(pPrivate
,
2837 // send Erase & Write Page
2842 if (r
!= ERROR_OK
) {
2843 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr
));
2845 if (status
& (1 << 2)) {
2846 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2849 if (status
& (1 << 1)) {
2850 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2861 sam3_write(struct flash_bank
*bank
,
2870 unsigned page_offset
;
2871 struct sam3_bank_private
*pPrivate
;
2872 uint8_t *pagebuffer
;
2874 // incase we bail further below, set this to null
2877 // ignore dumb requests
2883 if (bank
->target
->state
!= TARGET_HALTED
) {
2884 LOG_ERROR("Target not halted");
2885 r
= ERROR_TARGET_NOT_HALTED
;
2889 pPrivate
= get_sam3_bank_private(bank
);
2890 if (!(pPrivate
->probed
)) {
2891 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2896 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2897 LOG_ERROR("Flash write error - past end of bank");
2898 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2899 (unsigned int)(offset
),
2900 (unsigned int)(count
),
2901 (unsigned int)(pPrivate
->size_bytes
));
2906 pagebuffer
= malloc(pPrivate
->page_size
);
2908 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2913 // what page do we start & end in?
2914 page_cur
= offset
/ pPrivate
->page_size
;
2915 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2917 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2918 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2920 // Special case: all one page
2923 // (1) non-aligned start
2925 // (3) non-aligned end.
2927 // Handle special case - all one page.
2928 if (page_cur
== page_end
) {
2929 LOG_DEBUG("Special case, all in one page");
2930 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2931 if (r
!= ERROR_OK
) {
2935 page_offset
= (offset
& (pPrivate
->page_size
-1));
2936 memcpy(pagebuffer
+ page_offset
,
2940 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2941 if (r
!= ERROR_OK
) {
2948 // non-aligned start
2949 page_offset
= offset
& (pPrivate
->page_size
- 1);
2951 LOG_DEBUG("Not-Aligned start");
2953 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2954 if (r
!= ERROR_OK
) {
2958 // over-write with new data
2959 n
= (pPrivate
->page_size
- page_offset
);
2960 memcpy(pagebuffer
+ page_offset
,
2964 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2965 if (r
!= ERROR_OK
) {
2975 /* By checking that offset is correct here, we also
2976 fix a clang warning */
2977 assert(offset
== pPrivate
->page_size
);
2979 // intermediate large pages
2980 // also - the final *terminal*
2981 // if that terminal page is a full page
2982 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2983 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
2985 while ((page_cur
< page_end
) &&
2986 (count
>= pPrivate
->page_size
)) {
2987 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
2988 if (r
!= ERROR_OK
) {
2991 count
-= pPrivate
->page_size
;
2992 buffer
+= pPrivate
->page_size
;
2996 // terminal partial page?
2998 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
2999 // we have a partial page
3000 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
3001 if (r
!= ERROR_OK
) {
3004 // data goes at start
3005 memcpy(pagebuffer
, buffer
, count
);
3006 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
3007 if (r
!= ERROR_OK
) {
3022 COMMAND_HANDLER(sam3_handle_info_command
)
3024 struct sam3_chip
*pChip
;
3025 pChip
= get_current_sam3(CMD_CTX
);
3034 // bank0 must exist before we can do anything
3035 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3038 command_print(CMD_CTX
,
3039 "Please define bank %d via command: flash bank %s ... ",
3041 at91sam3_flash
.name
);
3045 // if bank 0 is not probed, then probe it
3046 if (!(pChip
->details
.bank
[0].probed
)) {
3047 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3048 if (r
!= ERROR_OK
) {
3052 // above guarantees the "chip details" structure is valid
3053 // and thus, bank private areas are valid
3054 // and we have a SAM3 chip, what a concept!
3057 // auto-probe other banks, 0 done above
3058 for (x
= 1 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
3059 // skip banks not present
3060 if (!(pChip
->details
.bank
[x
].present
)) {
3064 if (pChip
->details
.bank
[x
].pBank
== NULL
) {
3068 if (pChip
->details
.bank
[x
].probed
) {
3072 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
3073 if (r
!= ERROR_OK
) {
3079 r
= sam3_GetInfo(pChip
);
3080 if (r
!= ERROR_OK
) {
3081 LOG_DEBUG("Sam3Info, Failed %d",r
);
3088 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
3092 struct sam3_chip
*pChip
;
3094 pChip
= get_current_sam3(CMD_CTX
);
3099 if (pChip
->target
->state
!= TARGET_HALTED
) {
3100 LOG_ERROR("sam3 - target not halted");
3101 return ERROR_TARGET_NOT_HALTED
;
3105 if (pChip
->details
.bank
[0].pBank
== NULL
) {
3106 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
3107 at91sam3_flash
.name
);
3110 if (!pChip
->details
.bank
[0].probed
) {
3111 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
3112 if (r
!= ERROR_OK
) {
3120 return ERROR_COMMAND_SYNTAX_ERROR
;
3130 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all"))) {
3134 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
3140 if (0 == strcmp("show", CMD_ARGV
[0])) {
3144 for (x
= 0 ; x
< pChip
->details
.n_gpnvms
; x
++) {
3145 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
3146 if (r
!= ERROR_OK
) {
3149 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
3153 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
3154 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
3155 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
3158 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
3159 return ERROR_COMMAND_SYNTAX_ERROR
;
3164 command_print(CMD_CTX
, "Missing GPNVM number");
3165 return ERROR_COMMAND_SYNTAX_ERROR
;
3168 if (0 == strcmp("set", CMD_ARGV
[0])) {
3169 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
3170 } else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
3171 (0 == strcmp("clear", CMD_ARGV
[0]))) { // quietly accept both
3172 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
3174 command_print(CMD_CTX
, "Unknown command: %s", CMD_ARGV
[0]);
3175 r
= ERROR_COMMAND_SYNTAX_ERROR
;
3180 COMMAND_HANDLER(sam3_handle_slowclk_command
)
3182 struct sam3_chip
*pChip
;
3184 pChip
= get_current_sam3(CMD_CTX
);
3198 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
3200 // absurd slow clock of 200Khz?
3201 command_print(CMD_CTX
,"Absurd/illegal slow clock freq: %d\n", (int)(v
));
3202 return ERROR_COMMAND_SYNTAX_ERROR
;
3204 pChip
->cfg
.slow_freq
= v
;
3209 command_print(CMD_CTX
,"Too many parameters");
3210 return ERROR_COMMAND_SYNTAX_ERROR
;
3213 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
3214 (int)(pChip
->cfg
.slow_freq
/ 1000),
3215 (int)(pChip
->cfg
.slow_freq
% 1000));
3219 static const struct command_registration at91sam3_exec_command_handlers
[] = {
3222 .handler
= sam3_handle_gpnvm_command
,
3223 .mode
= COMMAND_EXEC
,
3224 .usage
= "[('clr'|'set'|'show') bitnum]",
3225 .help
= "Without arguments, shows all bits in the gpnvm "
3226 "register. Otherwise, clears, sets, or shows one "
3227 "General Purpose Non-Volatile Memory (gpnvm) bit.",
3231 .handler
= sam3_handle_info_command
,
3232 .mode
= COMMAND_EXEC
,
3233 .help
= "Print information about the current at91sam3 chip"
3234 "and its flash configuration.",
3238 .handler
= sam3_handle_slowclk_command
,
3239 .mode
= COMMAND_EXEC
,
3240 .usage
= "[clock_hz]",
3241 .help
= "Display or set the slowclock frequency "
3242 "(default 32768 Hz).",
3244 COMMAND_REGISTRATION_DONE
3246 static const struct command_registration at91sam3_command_handlers
[] = {
3249 .mode
= COMMAND_ANY
,
3250 .help
= "at91sam3 flash command group",
3251 .chain
= at91sam3_exec_command_handlers
,
3253 COMMAND_REGISTRATION_DONE
3256 struct flash_driver at91sam3_flash
= {
3258 .commands
= at91sam3_command_handlers
,
3259 .flash_bank_command
= sam3_flash_bank_command
,
3260 .erase
= sam3_erase
,
3261 .protect
= sam3_protect
,
3262 .write
= sam3_write
,
3263 .read
= default_flash_read
,
3264 .probe
= sam3_probe
,
3265 .auto_probe
= sam3_auto_probe
,
3266 .erase_check
= sam3_erase_check
,
3267 .protect_check
= sam3_protect_check
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)