1 /***************************************************************************
2 * Copyright (C) 2009 by Duane Ellis *
3 * openocd@duaneellis.com *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
13 * GNU General public License for more details. *
15 * You should have received a copy of the GNU General public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ****************************************************************************/
21 /* Some of the the lower level code was based on code supplied by
22 * ATMEL under this copyright. */
24 /* BEGIN ATMEL COPYRIGHT */
25 /* ----------------------------------------------------------------------------
26 * ATMEL Microcontroller Software Support
27 * ----------------------------------------------------------------------------
28 * Copyright (c) 2009, Atmel Corporation
30 * All rights reserved.
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions are met:
35 * - Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the disclaimer below.
38 * Atmel's name may not be used to endorse or promote products derived from
39 * this software without specific prior written permission.
41 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
43 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
44 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
46 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
47 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
48 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
49 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
50 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 * ----------------------------------------------------------------------------
53 /* END ATMEL COPYRIGHT */
65 #include <helper/membuf.h>
67 #include <helper/time_support.h>
69 #define REG_NAME_WIDTH (12)
72 #define FLASH_BANK0_BASE 0x00080000
73 #define FLASH_BANK1_BASE 0x00100000
75 #define AT91C_EFC_FCMD_GETD (0x0) // (EFC) Get Flash Descriptor
76 #define AT91C_EFC_FCMD_WP (0x1) // (EFC) Write Page
77 #define AT91C_EFC_FCMD_WPL (0x2) // (EFC) Write Page and Lock
78 #define AT91C_EFC_FCMD_EWP (0x3) // (EFC) Erase Page and Write Page
79 #define AT91C_EFC_FCMD_EWPL (0x4) // (EFC) Erase Page and Write Page then Lock
80 #define AT91C_EFC_FCMD_EA (0x5) // (EFC) Erase All
81 // cmd6 is not present int he at91sam3u4/2/1 data sheet table 17-2
82 // #define AT91C_EFC_FCMD_EPL (0x6) // (EFC) Erase plane?
83 // cmd7 is not present int he at91sam3u4/2/1 data sheet table 17-2
84 // #define AT91C_EFC_FCMD_EPA (0x7) // (EFC) Erase pages?
85 #define AT91C_EFC_FCMD_SLB (0x8) // (EFC) Set Lock Bit
86 #define AT91C_EFC_FCMD_CLB (0x9) // (EFC) Clear Lock Bit
87 #define AT91C_EFC_FCMD_GLB (0xA) // (EFC) Get Lock Bit
88 #define AT91C_EFC_FCMD_SFB (0xB) // (EFC) Set Fuse Bit
89 #define AT91C_EFC_FCMD_CFB (0xC) // (EFC) Clear Fuse Bit
90 #define AT91C_EFC_FCMD_GFB (0xD) // (EFC) Get Fuse Bit
91 #define AT91C_EFC_FCMD_STUI (0xE) // (EFC) Start Read Unique ID
92 #define AT91C_EFC_FCMD_SPUI (0xF) // (EFC) Stop Read Unique ID
94 #define offset_EFC_FMR 0
95 #define offset_EFC_FCR 4
96 #define offset_EFC_FSR 8
97 #define offset_EFC_FRR 12
101 _tomhz(uint32_t freq_hz
)
105 f
= ((float)(freq_hz
)) / 1000000.0;
109 // How the chip is configured.
111 uint32_t unique_id
[4];
115 uint32_t mainosc_freq
;
125 #define SAM3_CHIPID_CIDR (0x400E0740)
126 uint32_t CHIPID_CIDR
;
127 #define SAM3_CHIPID_EXID (0x400E0744)
128 uint32_t CHIPID_EXID
;
130 #define SAM3_SUPC_CR (0x400E1210)
133 #define SAM3_PMC_BASE (0x400E0400)
134 #define SAM3_PMC_SCSR (SAM3_PMC_BASE + 0x0008)
136 #define SAM3_PMC_PCSR (SAM3_PMC_BASE + 0x0018)
138 #define SAM3_CKGR_UCKR (SAM3_PMC_BASE + 0x001c)
140 #define SAM3_CKGR_MOR (SAM3_PMC_BASE + 0x0020)
142 #define SAM3_CKGR_MCFR (SAM3_PMC_BASE + 0x0024)
144 #define SAM3_CKGR_PLLAR (SAM3_PMC_BASE + 0x0028)
146 #define SAM3_PMC_MCKR (SAM3_PMC_BASE + 0x0030)
148 #define SAM3_PMC_PCK0 (SAM3_PMC_BASE + 0x0040)
150 #define SAM3_PMC_PCK1 (SAM3_PMC_BASE + 0x0044)
152 #define SAM3_PMC_PCK2 (SAM3_PMC_BASE + 0x0048)
154 #define SAM3_PMC_SR (SAM3_PMC_BASE + 0x0068)
156 #define SAM3_PMC_IMR (SAM3_PMC_BASE + 0x006c)
158 #define SAM3_PMC_FSMR (SAM3_PMC_BASE + 0x0070)
160 #define SAM3_PMC_FSPR (SAM3_PMC_BASE + 0x0074)
165 struct sam3_bank_private
{
167 // DANGER: THERE ARE DRAGONS HERE..
168 // NOTE: If you add more 'ghost' pointers
169 // be aware that you must *manually* update
170 // these pointers in the function sam3_GetDetails()
171 // See the comment "Here there be dragons"
173 // so we can find the chip we belong to
174 struct sam3_chip
*pChip
;
175 // so we can find the orginal bank pointer
176 struct flash_bank
*pBank
;
177 unsigned bank_number
;
178 uint32_t controller_address
;
179 uint32_t base_address
;
183 unsigned sector_size
;
187 struct sam3_chip_details
{
188 // THERE ARE DRAGONS HERE..
189 // note: If you add pointers here
190 // becareful about them as they
191 // may need to be updated inside
192 // the function: "sam3_GetDetails()
193 // which copy/overwrites the
194 // 'runtime' copy of this structure
195 uint32_t chipid_cidr
;
199 #define SAM3_N_NVM_BITS 3
200 unsigned gpnvm
[SAM3_N_NVM_BITS
];
201 unsigned total_flash_size
;
202 unsigned total_sram_size
;
204 #define SAM3_MAX_FLASH_BANKS 2
205 // these are "initialized" from the global const data
206 struct sam3_bank_private bank
[SAM3_MAX_FLASH_BANKS
];
211 struct sam3_chip
*next
;
214 // this is "initialized" from the global const structure
215 struct sam3_chip_details details
;
216 struct target
*target
;
223 struct sam3_reg_list
{
224 uint32_t address
; size_t struct_offset
; const char *name
;
225 void (*explain_func
)(struct sam3_chip
*pInfo
);
229 static struct sam3_chip
*all_sam3_chips
;
231 static struct sam3_chip
*
232 get_current_sam3(struct command_context
*cmd_ctx
)
235 static struct sam3_chip
*p
;
237 t
= get_current_target(cmd_ctx
);
239 command_print(cmd_ctx
, "No current target?");
245 // this should not happen
246 // the command is not registered until the chip is created?
247 command_print(cmd_ctx
, "No SAM3 chips exist?");
252 if (p
->target
== t
) {
257 command_print(cmd_ctx
, "Cannot find SAM3 chip?");
262 // these are used to *initialize* the "pChip->details" structure.
263 static const struct sam3_chip_details all_sam3_details
[] = {
265 .chipid_cidr
= 0x28100960,
266 .name
= "at91sam3u4e",
267 .total_flash_size
= 256 * 1024,
268 .total_sram_size
= 52 * 1024,
272 // System boots at address 0x0
273 // gpnvm[1] = selects boot code
275 // boot is via "SAMBA" (rom)
278 // Selection is via gpnvm[2]
281 // NOTE: banks 0 & 1 switch places
283 // Bank0 is the boot rom
285 // Bank1 is the boot rom
294 .base_address
= FLASH_BANK0_BASE
,
295 .controller_address
= 0x400e0800,
297 .size_bytes
= 128 * 1024,
309 .base_address
= FLASH_BANK1_BASE
,
310 .controller_address
= 0x400e0a00,
312 .size_bytes
= 128 * 1024,
321 .chipid_cidr
= 0x281a0760,
322 .name
= "at91sam3u2e",
323 .total_flash_size
= 128 * 1024,
324 .total_sram_size
= 36 * 1024,
328 // System boots at address 0x0
329 // gpnvm[1] = selects boot code
331 // boot is via "SAMBA" (rom)
334 // Selection is via gpnvm[2]
343 .base_address
= FLASH_BANK0_BASE
,
344 .controller_address
= 0x400e0800,
346 .size_bytes
= 128 * 1024,
360 .chipid_cidr
= 0x28190560,
361 .name
= "at91sam3u1e",
362 .total_flash_size
= 64 * 1024,
363 .total_sram_size
= 20 * 1024,
367 // System boots at address 0x0
368 // gpnvm[1] = selects boot code
370 // boot is via "SAMBA" (rom)
373 // Selection is via gpnvm[2]
384 .base_address
= FLASH_BANK0_BASE
,
385 .controller_address
= 0x400e0800,
387 .size_bytes
= 64 * 1024,
403 .chipid_cidr
= 0x28000960,
404 .name
= "at91sam3u4c",
405 .total_flash_size
= 256 * 1024,
406 .total_sram_size
= 52 * 1024,
410 // System boots at address 0x0
411 // gpnvm[1] = selects boot code
413 // boot is via "SAMBA" (rom)
416 // Selection is via gpnvm[2]
419 // NOTE: banks 0 & 1 switch places
421 // Bank0 is the boot rom
423 // Bank1 is the boot rom
432 .base_address
= FLASH_BANK0_BASE
,
433 .controller_address
= 0x400e0800,
435 .size_bytes
= 128 * 1024,
446 .base_address
= FLASH_BANK1_BASE
,
447 .controller_address
= 0x400e0a00,
449 .size_bytes
= 128 * 1024,
458 .chipid_cidr
= 0x280a0760,
459 .name
= "at91sam3u2c",
460 .total_flash_size
= 128 * 1024,
461 .total_sram_size
= 36 * 1024,
465 // System boots at address 0x0
466 // gpnvm[1] = selects boot code
468 // boot is via "SAMBA" (rom)
471 // Selection is via gpnvm[2]
480 .base_address
= FLASH_BANK0_BASE
,
481 .controller_address
= 0x400e0800,
483 .size_bytes
= 128 * 1024,
497 .chipid_cidr
= 0x28090560,
498 .name
= "at91sam3u1c",
499 .total_flash_size
= 64 * 1024,
500 .total_sram_size
= 20 * 1024,
504 // System boots at address 0x0
505 // gpnvm[1] = selects boot code
507 // boot is via "SAMBA" (rom)
510 // Selection is via gpnvm[2]
521 .base_address
= FLASH_BANK0_BASE
,
522 .controller_address
= 0x400e0800,
524 .size_bytes
= 64 * 1024,
547 /***********************************************************************
548 **********************************************************************
549 **********************************************************************
550 **********************************************************************
551 **********************************************************************
552 **********************************************************************/
553 /* *ATMEL* style code - from the SAM3 driver code */
556 * Get the current status of the EEFC and
557 * the value of some status bits (LOCKE, PROGE).
558 * @param pPrivate - info about the bank
559 * @param v - result goes here
562 EFC_GetStatus(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
565 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FSR
, v
);
566 LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
568 ((unsigned int)((*v
>> 2) & 1)),
569 ((unsigned int)((*v
>> 1) & 1)),
570 ((unsigned int)((*v
>> 0) & 1)));
576 * Get the result of the last executed command.
577 * @param pPrivate - info about the bank
578 * @param v - result goes here
581 EFC_GetResult(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
585 r
= target_read_u32(pPrivate
->pChip
->target
, pPrivate
->controller_address
+ offset_EFC_FRR
, &rv
);
589 LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv
)));
594 EFC_StartCommand(struct sam3_bank_private
*pPrivate
,
595 unsigned command
, unsigned argument
)
604 // Check command & argument
607 case AT91C_EFC_FCMD_WP
:
608 case AT91C_EFC_FCMD_WPL
:
609 case AT91C_EFC_FCMD_EWP
:
610 case AT91C_EFC_FCMD_EWPL
:
611 // case AT91C_EFC_FCMD_EPL:
612 // case AT91C_EFC_FCMD_EPA:
613 case AT91C_EFC_FCMD_SLB
:
614 case AT91C_EFC_FCMD_CLB
:
615 n
= (pPrivate
->size_bytes
/ pPrivate
->page_size
);
617 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n
));
621 case AT91C_EFC_FCMD_SFB
:
622 case AT91C_EFC_FCMD_CFB
:
623 if (argument
>= pPrivate
->pChip
->details
.n_gpnvms
) {
624 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
625 pPrivate
->pChip
->details
.n_gpnvms
);
629 case AT91C_EFC_FCMD_GETD
:
630 case AT91C_EFC_FCMD_EA
:
631 case AT91C_EFC_FCMD_GLB
:
632 case AT91C_EFC_FCMD_GFB
:
633 case AT91C_EFC_FCMD_STUI
:
634 case AT91C_EFC_FCMD_SPUI
:
636 LOG_ERROR("Argument is meaningless for cmd: %d", command
);
640 LOG_ERROR("Unknown command %d", command
);
644 if (command
== AT91C_EFC_FCMD_SPUI
) {
645 // this is a very special situation.
646 // Situation (1) - error/retry - see below
647 // And we are being called recursively
648 // Situation (2) - normal, finished reading unique id
650 // it should be "ready"
651 EFC_GetStatus(pPrivate
, &v
);
657 // we have done this before
658 // the controller is not responding.
659 LOG_ERROR("flash controller(%d) is not ready! Error", pPrivate
->bank_number
);
663 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
664 pPrivate
->bank_number
);
665 // we do that by issuing the *STOP* command
666 EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0);
667 // above is recursive, and further recursion is blocked by
668 // if (command == AT91C_EFC_FCMD_SPUI) above
674 v
= (0x5A << 24) | (argument
<< 8) | command
;
675 LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v
)));
676 r
= target_write_u32(pPrivate
->pBank
->target
,
677 pPrivate
->controller_address
+ offset_EFC_FCR
,
680 LOG_DEBUG("Error Write failed");
686 * Performs the given command and wait until its completion (or an error).
687 * @param pPrivate - info about the bank
688 * @param command - Command to perform.
689 * @param argument - Optional command argument.
690 * @param status - put command status bits here
693 EFC_PerformCommand(struct sam3_bank_private
*pPrivate
,
701 long long ms_now
, ms_end
;
708 r
= EFC_StartCommand(pPrivate
, command
, argument
);
713 ms_end
= 500 + timeval_ms();
717 r
= EFC_GetStatus(pPrivate
, &v
);
721 ms_now
= timeval_ms();
722 if (ms_now
> ms_end
) {
724 LOG_ERROR("Command timeout");
744 * Read the unique ID.
745 * @param pPrivate - info about the bank
746 * The unique ID is stored in the 'pPrivate' structure.
749 FLASHD_ReadUniqueID (struct sam3_bank_private
*pPrivate
)
755 pPrivate
->pChip
->cfg
.unique_id
[0] = 0;
756 pPrivate
->pChip
->cfg
.unique_id
[1] = 0;
757 pPrivate
->pChip
->cfg
.unique_id
[2] = 0;
758 pPrivate
->pChip
->cfg
.unique_id
[3] = 0;
761 r
= EFC_StartCommand(pPrivate
, AT91C_EFC_FCMD_STUI
, 0);
766 for (x
= 0 ; x
< 4 ; x
++) {
767 r
= target_read_u32(pPrivate
->pChip
->target
,
768 pPrivate
->pBank
->base
+ (x
* 4),
773 pPrivate
->pChip
->cfg
.unique_id
[x
] = v
;
776 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SPUI
, 0, NULL
);
777 LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
779 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[0]),
780 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[1]),
781 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[2]),
782 (unsigned int)(pPrivate
->pChip
->cfg
.unique_id
[3]));
788 * Erases the entire flash.
789 * @param pPrivate - the info about the bank.
792 FLASHD_EraseEntireBank(struct sam3_bank_private
*pPrivate
)
795 return EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_EA
, 0, NULL
);
801 * Gets current GPNVM state.
802 * @param pPrivate - info about the bank.
803 * @param gpnvm - GPNVM bit index.
804 * @param puthere - result stored here.
806 //------------------------------------------------------------------------------
808 FLASHD_GetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
, unsigned *puthere
)
814 if (pPrivate
->bank_number
!= 0) {
815 LOG_ERROR("GPNVM only works with Bank0");
819 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
820 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
821 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
826 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GFB
, 0, NULL
);
832 r
= EFC_GetResult(pPrivate
, &v
);
835 // Check if GPNVM is set
836 // get the bit and make it a 0/1
837 *puthere
= (v
>> gpnvm
) & 1;
847 * Clears the selected GPNVM bit.
848 * @param pPrivate info about the bank
849 * @param gpnvm GPNVM index.
850 * @returns 0 if successful; otherwise returns an error code.
853 FLASHD_ClrGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
859 if (pPrivate
->bank_number
!= 0) {
860 LOG_ERROR("GPNVM only works with Bank0");
864 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
865 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
866 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
870 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
872 LOG_DEBUG("Failed: %d",r
);
875 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CFB
, gpnvm
, NULL
);
876 LOG_DEBUG("End: %d",r
);
883 * Sets the selected GPNVM bit.
884 * @param pPrivate info about the bank
885 * @param gpnvm GPNVM index.
888 FLASHD_SetGPNVM(struct sam3_bank_private
*pPrivate
, unsigned gpnvm
)
893 if (pPrivate
->bank_number
!= 0) {
894 LOG_ERROR("GPNVM only works with Bank0");
898 if (gpnvm
>= pPrivate
->pChip
->details
.n_gpnvms
) {
899 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
900 gpnvm
,pPrivate
->pChip
->details
.n_gpnvms
);
904 r
= FLASHD_GetGPNVM(pPrivate
, gpnvm
, &v
);
913 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SFB
, gpnvm
, NULL
);
920 * Returns a bit field (at most 64) of locked regions within a page.
921 * @param pPrivate info about the bank
922 * @param v where to store locked bits
925 FLASHD_GetLockBits(struct sam3_bank_private
*pPrivate
, uint32_t *v
)
929 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_GLB
, 0, NULL
);
931 r
= EFC_GetResult(pPrivate
, v
);
933 LOG_DEBUG("End: %d",r
);
939 * Unlocks all the regions in the given address range.
940 * @param pPrivate info about the bank
941 * @param start_sector first sector to unlock
942 * @param end_sector last (inclusive) to unlock
946 FLASHD_Unlock(struct sam3_bank_private
*pPrivate
,
947 unsigned start_sector
,
953 uint32_t pages_per_sector
;
955 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
957 /* Unlock all pages */
958 while (start_sector
<= end_sector
) {
959 pg
= start_sector
* pages_per_sector
;
961 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_CLB
, pg
, &status
);
974 * @param pPrivate - info about the bank
975 * @param start_sector - first sector to lock
976 * @param end_sector - last sector (inclusive) to lock
979 FLASHD_Lock(struct sam3_bank_private
*pPrivate
,
980 unsigned start_sector
,
985 uint32_t pages_per_sector
;
988 pages_per_sector
= pPrivate
->sector_size
/ pPrivate
->page_size
;
991 while (start_sector
<= end_sector
) {
992 pg
= start_sector
* pages_per_sector
;
994 r
= EFC_PerformCommand(pPrivate
, AT91C_EFC_FCMD_SLB
, pg
, &status
);
1004 /****** END SAM3 CODE ********/
1006 /* begin helpful debug code */
1009 sam3_sprintf(struct sam3_chip
*pChip
, const char *fmt
, ...)
1013 if (pChip
->mbuf
== NULL
) {
1017 membuf_vsprintf(pChip
->mbuf
, fmt
, ap
);
1021 // print the fieldname, the field value, in dec & hex, and return field value
1023 sam3_reg_fieldname(struct sam3_chip
*pChip
,
1024 const char *regname
,
1033 // extract the field
1035 v
= v
& ((1 << width
)-1);
1045 sam3_sprintf(pChip
, "\t%*s: %*d [0x%0*x] ",
1046 REG_NAME_WIDTH
, regname
,
1053 static const char _unknown
[] = "unknown";
1054 static const char * const eproc_names
[] = {
1073 #define nvpsize2 nvpsize // these two tables are identical
1074 static const char * const nvpsize
[] = {
1087 "1024K bytes", // 12
1089 "2048K bytes", // 14
1094 static const char * const sramsize
[] = {
1114 static const struct archnames
{ unsigned value
; const char *name
; } archnames
[] = {
1115 { 0x19, "AT91SAM9xx Series" },
1116 { 0x29, "AT91SAM9XExx Series" },
1117 { 0x34, "AT91x34 Series" },
1118 { 0x37, "CAP7 Series" },
1119 { 0x39, "CAP9 Series" },
1120 { 0x3B, "CAP11 Series" },
1121 { 0x40, "AT91x40 Series" },
1122 { 0x42, "AT91x42 Series" },
1123 { 0x55, "AT91x55 Series" },
1124 { 0x60, "AT91SAM7Axx Series" },
1125 { 0x61, "AT91SAM7AQxx Series" },
1126 { 0x63, "AT91x63 Series" },
1127 { 0x70, "AT91SAM7Sxx Series" },
1128 { 0x71, "AT91SAM7XCxx Series" },
1129 { 0x72, "AT91SAM7SExx Series" },
1130 { 0x73, "AT91SAM7Lxx Series" },
1131 { 0x75, "AT91SAM7Xxx Series" },
1132 { 0x76, "AT91SAM7SLxx Series" },
1133 { 0x80, "ATSAM3UxC Series (100-pin version)" },
1134 { 0x81, "ATSAM3UxE Series (144-pin version)" },
1135 { 0x83, "ATSAM3AxC Series (100-pin version)" },
1136 { 0x84, "ATSAM3XxC Series (100-pin version)" },
1137 { 0x85, "ATSAM3XxE Series (144-pin version)" },
1138 { 0x86, "ATSAM3XxG Series (208/217-pin version)" },
1139 { 0x88, "ATSAM3SxA Series (48-pin version)" },
1140 { 0x89, "ATSAM3SxB Series (64-pin version)" },
1141 { 0x8A, "ATSAM3SxC Series (100-pin version)" },
1142 { 0x92, "AT91x92 Series" },
1143 { 0xF0, "AT75Cxx Series" },
1148 static const char * const nvptype
[] = {
1150 "romless or onchip flash", // 1
1151 "embedded flash memory", // 2
1152 "rom(nvpsiz) + embedded flash (nvpsiz2)", //3
1153 "sram emulating flash", // 4
1160 static const char *_yes_or_no(uint32_t v
)
1169 static const char * const _rc_freq
[] = {
1170 "4 MHz", "8 MHz", "12 MHz", "reserved"
1174 sam3_explain_ckgr_mor(struct sam3_chip
*pChip
)
1179 v
= sam3_reg_fieldname(pChip
, "MOSCXTEN", pChip
->cfg
.CKGR_MOR
, 0, 1);
1180 sam3_sprintf(pChip
, "(main xtal enabled: %s)\n",
1182 v
= sam3_reg_fieldname(pChip
, "MOSCXTBY", pChip
->cfg
.CKGR_MOR
, 1, 1);
1183 sam3_sprintf(pChip
, "(main osc bypass: %s)\n",
1185 rcen
= sam3_reg_fieldname(pChip
, "MOSCRCEN", pChip
->cfg
.CKGR_MOR
, 2, 1);
1186 sam3_sprintf(pChip
, "(onchip RC-OSC enabled: %s)\n",
1188 v
= sam3_reg_fieldname(pChip
, "MOSCRCF", pChip
->cfg
.CKGR_MOR
, 4, 3);
1189 sam3_sprintf(pChip
, "(onchip RC-OSC freq: %s)\n",
1192 pChip
->cfg
.rc_freq
= 0;
1196 pChip
->cfg
.rc_freq
= 0;
1198 pChip
->cfg
.rc_freq
= 4 * 1000 * 1000;
1201 pChip
->cfg
.rc_freq
= 8 * 1000 * 1000;
1204 pChip
->cfg
.rc_freq
= 12* 1000 * 1000;
1209 v
= sam3_reg_fieldname(pChip
,"MOSCXTST", pChip
->cfg
.CKGR_MOR
, 8, 8);
1210 sam3_sprintf(pChip
, "(startup clks, time= %f uSecs)\n",
1211 ((float)(v
* 1000000)) / ((float)(pChip
->cfg
.slow_freq
)));
1212 v
= sam3_reg_fieldname(pChip
, "MOSCSEL", pChip
->cfg
.CKGR_MOR
, 24, 1);
1213 sam3_sprintf(pChip
, "(mainosc source: %s)\n",
1214 v
? "external xtal" : "internal RC");
1216 v
= sam3_reg_fieldname(pChip
,"CFDEN", pChip
->cfg
.CKGR_MOR
, 25, 1);
1217 sam3_sprintf(pChip
, "(clock failure enabled: %s)\n",
1224 sam3_explain_chipid_cidr(struct sam3_chip
*pChip
)
1230 sam3_reg_fieldname(pChip
, "Version", pChip
->cfg
.CHIPID_CIDR
, 0, 5);
1231 sam3_sprintf(pChip
,"\n");
1233 v
= sam3_reg_fieldname(pChip
, "EPROC", pChip
->cfg
.CHIPID_CIDR
, 5, 3);
1234 sam3_sprintf(pChip
, "%s\n", eproc_names
[v
]);
1236 v
= sam3_reg_fieldname(pChip
, "NVPSIZE", pChip
->cfg
.CHIPID_CIDR
, 8, 4);
1237 sam3_sprintf(pChip
, "%s\n", nvpsize
[v
]);
1239 v
= sam3_reg_fieldname(pChip
, "NVPSIZE2", pChip
->cfg
.CHIPID_CIDR
, 12, 4);
1240 sam3_sprintf(pChip
, "%s\n", nvpsize2
[v
]);
1242 v
= sam3_reg_fieldname(pChip
, "SRAMSIZE", pChip
->cfg
.CHIPID_CIDR
, 16,4);
1243 sam3_sprintf(pChip
, "%s\n", sramsize
[ v
]);
1245 v
= sam3_reg_fieldname(pChip
, "ARCH", pChip
->cfg
.CHIPID_CIDR
, 20, 8);
1247 for (x
= 0 ; archnames
[x
].name
; x
++) {
1248 if (v
== archnames
[x
].value
) {
1249 cp
= archnames
[x
].name
;
1254 sam3_sprintf(pChip
, "%s\n", cp
);
1256 v
= sam3_reg_fieldname(pChip
, "NVPTYP", pChip
->cfg
.CHIPID_CIDR
, 28, 3);
1257 sam3_sprintf(pChip
, "%s\n", nvptype
[ v
]);
1259 v
= sam3_reg_fieldname(pChip
, "EXTID", pChip
->cfg
.CHIPID_CIDR
, 31, 1);
1260 sam3_sprintf(pChip
, "(exists: %s)\n", _yes_or_no(v
));
1264 sam3_explain_ckgr_mcfr(struct sam3_chip
*pChip
)
1269 v
= sam3_reg_fieldname(pChip
, "MAINFRDY", pChip
->cfg
.CKGR_MCFR
, 16, 1);
1270 sam3_sprintf(pChip
, "(main ready: %s)\n", _yes_or_no(v
));
1272 v
= sam3_reg_fieldname(pChip
, "MAINF", pChip
->cfg
.CKGR_MCFR
, 0, 16);
1274 v
= (v
* pChip
->cfg
.slow_freq
) / 16;
1275 pChip
->cfg
.mainosc_freq
= v
;
1277 sam3_sprintf(pChip
, "(%3.03f Mhz (%d.%03dkhz slowclk)\n",
1279 pChip
->cfg
.slow_freq
/ 1000,
1280 pChip
->cfg
.slow_freq
% 1000);
1285 sam3_explain_ckgr_plla(struct sam3_chip
*pChip
)
1289 diva
= sam3_reg_fieldname(pChip
, "DIVA", pChip
->cfg
.CKGR_PLLAR
, 0, 8);
1290 sam3_sprintf(pChip
,"\n");
1291 mula
= sam3_reg_fieldname(pChip
, "MULA", pChip
->cfg
.CKGR_PLLAR
, 16, 11);
1292 sam3_sprintf(pChip
,"\n");
1293 pChip
->cfg
.plla_freq
= 0;
1295 sam3_sprintf(pChip
,"\tPLLA Freq: (Disabled,mula = 0)\n");
1296 } else if (diva
== 0) {
1297 sam3_sprintf(pChip
,"\tPLLA Freq: (Disabled,diva = 0)\n");
1298 } else if (diva
== 1) {
1299 pChip
->cfg
.plla_freq
= (pChip
->cfg
.mainosc_freq
* (mula
+ 1));
1300 sam3_sprintf(pChip
,"\tPLLA Freq: %3.03f MHz\n",
1301 _tomhz(pChip
->cfg
.plla_freq
));
1307 sam3_explain_mckr(struct sam3_chip
*pChip
)
1309 uint32_t css
, pres
, fin
= 0;
1311 const char *cp
= NULL
;
1313 css
= sam3_reg_fieldname(pChip
, "CSS", pChip
->cfg
.PMC_MCKR
, 0, 2);
1316 fin
= pChip
->cfg
.slow_freq
;
1320 fin
= pChip
->cfg
.mainosc_freq
;
1324 fin
= pChip
->cfg
.plla_freq
;
1328 if (pChip
->cfg
.CKGR_UCKR
& (1 << 16)) {
1329 fin
= 480 * 1000 * 1000;
1333 cp
= "upll (*ERROR* UPLL is disabled)";
1341 sam3_sprintf(pChip
, "%s (%3.03f Mhz)\n",
1344 pres
= sam3_reg_fieldname(pChip
, "PRES", pChip
->cfg
.PMC_MCKR
, 4, 3);
1345 switch (pres
& 0x07) {
1348 cp
= "selected clock";
1381 sam3_sprintf(pChip
, "(%s)\n", cp
);
1383 // sam3 has a *SINGLE* clock -
1384 // other at91 series parts have divisors for these.
1385 pChip
->cfg
.cpu_freq
= fin
;
1386 pChip
->cfg
.mclk_freq
= fin
;
1387 pChip
->cfg
.fclk_freq
= fin
;
1388 sam3_sprintf(pChip
, "\t\tResult CPU Freq: %3.03f\n",
1393 static struct sam3_chip
*
1394 target2sam3(struct target
*pTarget
)
1396 struct sam3_chip
*pChip
;
1398 if (pTarget
== NULL
) {
1402 pChip
= all_sam3_chips
;
1404 if (pChip
->target
== pTarget
) {
1405 break; // return below
1407 pChip
= pChip
->next
;
1415 sam3_get_reg_ptr(struct sam3_cfg
*pCfg
, const struct sam3_reg_list
*pList
)
1417 // this function exists to help
1418 // keep funky offsetof() errors
1419 // and casting from causing bugs
1421 // By using prototypes - we can detect what would
1422 // be casting errors.
1424 return ((uint32_t *)(((char *)(pCfg
)) + pList
->struct_offset
));
1428 #define SAM3_ENTRY(NAME, FUNC) { .address = SAM3_ ## NAME, .struct_offset = offsetof(struct sam3_cfg, NAME), #NAME, FUNC }
1429 static const struct sam3_reg_list sam3_all_regs
[] = {
1430 SAM3_ENTRY(CKGR_MOR
, sam3_explain_ckgr_mor
),
1431 SAM3_ENTRY(CKGR_MCFR
, sam3_explain_ckgr_mcfr
),
1432 SAM3_ENTRY(CKGR_PLLAR
, sam3_explain_ckgr_plla
),
1433 SAM3_ENTRY(CKGR_UCKR
, NULL
),
1434 SAM3_ENTRY(PMC_FSMR
, NULL
),
1435 SAM3_ENTRY(PMC_FSPR
, NULL
),
1436 SAM3_ENTRY(PMC_IMR
, NULL
),
1437 SAM3_ENTRY(PMC_MCKR
, sam3_explain_mckr
),
1438 SAM3_ENTRY(PMC_PCK0
, NULL
),
1439 SAM3_ENTRY(PMC_PCK1
, NULL
),
1440 SAM3_ENTRY(PMC_PCK2
, NULL
),
1441 SAM3_ENTRY(PMC_PCSR
, NULL
),
1442 SAM3_ENTRY(PMC_SCSR
, NULL
),
1443 SAM3_ENTRY(PMC_SR
, NULL
),
1444 SAM3_ENTRY(CHIPID_CIDR
, sam3_explain_chipid_cidr
),
1445 SAM3_ENTRY(CHIPID_EXID
, NULL
),
1446 SAM3_ENTRY(SUPC_CR
, NULL
),
1448 // TERMINATE THE LIST
1456 static struct sam3_bank_private
*
1457 get_sam3_bank_private(struct flash_bank
*bank
)
1459 return (struct sam3_bank_private
*)(bank
->driver_priv
);
1463 * Given a pointer to where it goes in the structure,
1464 * determine the register name, address from the all registers table.
1466 static const struct sam3_reg_list
*
1467 sam3_GetReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
1469 const struct sam3_reg_list
*pReg
;
1471 pReg
= &(sam3_all_regs
[0]);
1472 while (pReg
->name
) {
1473 uint32_t *pPossible
;
1475 // calculate where this one go..
1476 // it is "possibly" this register.
1478 pPossible
= ((uint32_t *)(((char *)(&(pChip
->cfg
))) + pReg
->struct_offset
));
1480 // well? Is it this register
1481 if (pPossible
== goes_here
) {
1489 // This is *TOTAL*PANIC* - we are totally screwed.
1490 LOG_ERROR("INVALID SAM3 REGISTER");
1496 sam3_ReadThisReg(struct sam3_chip
*pChip
, uint32_t *goes_here
)
1498 const struct sam3_reg_list
*pReg
;
1501 pReg
= sam3_GetReg(pChip
, goes_here
);
1506 r
= target_read_u32(pChip
->target
, pReg
->address
, goes_here
);
1507 if (r
!= ERROR_OK
) {
1508 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d\n",
1509 pReg
->name
, (unsigned)(pReg
->address
), r
);
1517 sam3_ReadAllRegs(struct sam3_chip
*pChip
)
1520 const struct sam3_reg_list
*pReg
;
1522 pReg
= &(sam3_all_regs
[0]);
1523 while (pReg
->name
) {
1524 r
= sam3_ReadThisReg(pChip
,
1525 sam3_get_reg_ptr(&(pChip
->cfg
), pReg
));
1526 if (r
!= ERROR_OK
) {
1527 LOG_ERROR("Cannot read SAM3 registere: %s @ 0x%08x, Error: %d\n",
1528 pReg
->name
, ((unsigned)(pReg
->address
)), r
);
1540 sam3_GetInfo(struct sam3_chip
*pChip
)
1542 const struct sam3_reg_list
*pReg
;
1545 membuf_reset(pChip
->mbuf
);
1548 pReg
= &(sam3_all_regs
[0]);
1549 while (pReg
->name
) {
1551 LOG_DEBUG("Start: %s", pReg
->name
);
1552 regval
= *sam3_get_reg_ptr(&(pChip
->cfg
), pReg
);
1553 sam3_sprintf(pChip
, "%*s: [0x%08x] -> 0x%08x\n",
1558 if (pReg
->explain_func
) {
1559 (*(pReg
->explain_func
))(pChip
);
1561 LOG_DEBUG("End: %s", pReg
->name
);
1564 sam3_sprintf(pChip
," rc-osc: %3.03f MHz\n", _tomhz(pChip
->cfg
.rc_freq
));
1565 sam3_sprintf(pChip
," mainosc: %3.03f MHz\n", _tomhz(pChip
->cfg
.mainosc_freq
));
1566 sam3_sprintf(pChip
," plla: %3.03f MHz\n", _tomhz(pChip
->cfg
.plla_freq
));
1567 sam3_sprintf(pChip
," cpu-freq: %3.03f MHz\n", _tomhz(pChip
->cfg
.cpu_freq
));
1568 sam3_sprintf(pChip
,"mclk-freq: %3.03f MHz\n", _tomhz(pChip
->cfg
.mclk_freq
));
1571 sam3_sprintf(pChip
, " UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1572 pChip
->cfg
.unique_id
[0],
1573 pChip
->cfg
.unique_id
[1],
1574 pChip
->cfg
.unique_id
[2],
1575 pChip
->cfg
.unique_id
[3]);
1583 sam3_erase_check(struct flash_bank
*bank
)
1588 if (bank
->target
->state
!= TARGET_HALTED
) {
1589 LOG_ERROR("Target not halted");
1590 return ERROR_TARGET_NOT_HALTED
;
1592 if (0 == bank
->num_sectors
) {
1593 LOG_ERROR("Target: not supported/not probed\n");
1597 LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
1598 for (x
= 0 ; x
< bank
->num_sectors
; x
++) {
1599 bank
->sectors
[x
].is_erased
= 1;
1607 sam3_protect_check(struct flash_bank
*bank
)
1612 struct sam3_bank_private
*pPrivate
;
1615 if (bank
->target
->state
!= TARGET_HALTED
) {
1616 LOG_ERROR("Target not halted");
1617 return ERROR_TARGET_NOT_HALTED
;
1620 pPrivate
= get_sam3_bank_private(bank
);
1622 LOG_ERROR("no private for this bank?");
1625 if (!(pPrivate
->probed
)) {
1626 return ERROR_FLASH_BANK_NOT_PROBED
;
1629 r
= FLASHD_GetLockBits(pPrivate
, &v
);
1630 if (r
!= ERROR_OK
) {
1631 LOG_DEBUG("Failed: %d",r
);
1635 for (x
= 0 ; x
< pPrivate
->nsectors
; x
++) {
1636 bank
->sectors
[x
].is_protected
= (!!(v
& (1 << x
)));
1642 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command
)
1644 struct sam3_chip
*pChip
;
1646 pChip
= all_sam3_chips
;
1648 // is this an existing chip?
1650 if (pChip
->target
== bank
->target
) {
1653 pChip
= pChip
->next
;
1657 // this is a *NEW* chip
1658 pChip
= calloc(1, sizeof(struct sam3_chip
));
1660 LOG_ERROR("NO RAM!");
1663 pChip
->target
= bank
->target
;
1665 pChip
->next
= all_sam3_chips
;
1666 all_sam3_chips
= pChip
;
1667 pChip
->target
= bank
->target
;
1668 // assumption is this runs at 32khz
1669 pChip
->cfg
.slow_freq
= 32768;
1671 pChip
->mbuf
= membuf_new();
1672 if (!(pChip
->mbuf
)) {
1673 LOG_ERROR("no memory");
1678 switch (bank
->base
) {
1680 LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x)",
1681 ((unsigned int)(bank
->base
)),
1682 ((unsigned int)(FLASH_BANK0_BASE
)),
1683 ((unsigned int)(FLASH_BANK1_BASE
)));
1686 case FLASH_BANK0_BASE
:
1687 bank
->driver_priv
= &(pChip
->details
.bank
[0]);
1688 bank
->bank_number
= 0;
1689 pChip
->details
.bank
[0].pChip
= pChip
;
1690 pChip
->details
.bank
[0].pBank
= bank
;
1692 case FLASH_BANK1_BASE
:
1693 bank
->driver_priv
= &(pChip
->details
.bank
[1]);
1694 bank
->bank_number
= 1;
1695 pChip
->details
.bank
[1].pChip
= pChip
;
1696 pChip
->details
.bank
[1].pBank
= bank
;
1700 // we initialize after probing.
1705 sam3_GetDetails(struct sam3_bank_private
*pPrivate
)
1707 const struct sam3_chip_details
*pDetails
;
1708 struct sam3_chip
*pChip
;
1710 struct flash_bank
*saved_banks
[SAM3_MAX_FLASH_BANKS
];
1716 pDetails
= all_sam3_details
;
1717 while (pDetails
->name
) {
1718 if (pDetails
->chipid_cidr
== pPrivate
->pChip
->cfg
.CHIPID_CIDR
) {
1724 if (pDetails
->name
== NULL
) {
1725 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can this chip?)",
1726 (unsigned int)(pPrivate
->pChip
->cfg
.CHIPID_CIDR
));
1727 // Help the victim, print details about the chip
1728 membuf_reset(pPrivate
->pChip
->mbuf
);
1729 membuf_sprintf(pPrivate
->pChip
->mbuf
,
1730 "SAM3 CHIPID_CIDR: 0x%08x decodes as follows\n",
1731 pPrivate
->pChip
->cfg
.CHIPID_CIDR
);
1732 sam3_explain_chipid_cidr(pPrivate
->pChip
);
1733 cp
= membuf_strtok(pPrivate
->pChip
->mbuf
, "\n", &vp
);
1736 cp
= membuf_strtok(NULL
, "\n", &vp
);
1741 // DANGER: THERE ARE DRAGONS HERE
1743 // get our pChip - it is going
1744 // to be over-written shortly
1745 pChip
= pPrivate
->pChip
;
1747 // Note that, in reality:
1749 // pPrivate = &(pChip->details.bank[0])
1750 // or pPrivate = &(pChip->details.bank[1])
1753 // save the "bank" pointers
1754 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
1755 saved_banks
[ x
] = pChip
->details
.bank
[x
].pBank
;
1758 // Overwrite the "details" structure.
1759 memcpy(&(pPrivate
->pChip
->details
),
1761 sizeof(pPrivate
->pChip
->details
));
1763 // now fix the ghosted pointers
1764 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
1765 pChip
->details
.bank
[x
].pChip
= pChip
;
1766 pChip
->details
.bank
[x
].pBank
= saved_banks
[x
];
1769 // update the *BANK*SIZE*
1778 _sam3_probe(struct flash_bank
*bank
, int noise
)
1782 struct sam3_bank_private
*pPrivate
;
1785 LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank
->bank_number
, noise
);
1786 if (bank
->target
->state
!= TARGET_HALTED
)
1788 LOG_ERROR("Target not halted");
1789 return ERROR_TARGET_NOT_HALTED
;
1792 pPrivate
= get_sam3_bank_private(bank
);
1794 LOG_ERROR("Invalid/unknown bank number\n");
1798 r
= sam3_ReadAllRegs(pPrivate
->pChip
);
1799 if (r
!= ERROR_OK
) {
1805 r
= sam3_GetInfo(pPrivate
->pChip
);
1806 if (r
!= ERROR_OK
) {
1809 if (!(pPrivate
->pChip
->probed
)) {
1810 pPrivate
->pChip
->probed
= 1;
1812 r
= sam3_GetDetails(pPrivate
);
1813 if (r
!= ERROR_OK
) {
1818 // update the flash bank size
1819 for (x
= 0 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
1820 if (bank
->base
== pPrivate
->pChip
->details
.bank
[0].base_address
) {
1821 bank
->size
= pPrivate
->pChip
->details
.bank
[0].size_bytes
;
1826 if (bank
->sectors
== NULL
) {
1827 bank
->sectors
= calloc(pPrivate
->nsectors
, (sizeof((bank
->sectors
)[0])));
1828 if (bank
->sectors
== NULL
) {
1829 LOG_ERROR("No memory!");
1832 bank
->num_sectors
= pPrivate
->nsectors
;
1834 for (x
= 0 ; ((int)(x
)) < bank
->num_sectors
; x
++) {
1835 bank
->sectors
[x
].size
= pPrivate
->sector_size
;
1836 bank
->sectors
[x
].offset
= x
* (pPrivate
->sector_size
);
1838 bank
->sectors
[x
].is_erased
= -1;
1839 bank
->sectors
[x
].is_protected
= -1;
1843 pPrivate
->probed
= 1;
1845 r
= sam3_protect_check(bank
);
1846 if (r
!= ERROR_OK
) {
1850 LOG_DEBUG("Bank = %d, nbanks = %d",
1851 pPrivate
->bank_number
, pPrivate
->pChip
->details
.n_banks
);
1852 if ((pPrivate
->bank_number
+ 1) == pPrivate
->pChip
->details
.n_banks
) {
1854 // it appears to be associated with the *last* flash bank.
1855 FLASHD_ReadUniqueID(pPrivate
);
1862 sam3_probe(struct flash_bank
*bank
)
1864 return _sam3_probe(bank
, 1);
1868 sam3_auto_probe(struct flash_bank
*bank
)
1870 return _sam3_probe(bank
, 0);
1876 sam3_erase(struct flash_bank
*bank
, int first
, int last
)
1878 struct sam3_bank_private
*pPrivate
;
1882 if (bank
->target
->state
!= TARGET_HALTED
) {
1883 LOG_ERROR("Target not halted");
1884 return ERROR_TARGET_NOT_HALTED
;
1887 r
= sam3_auto_probe(bank
);
1888 if (r
!= ERROR_OK
) {
1889 LOG_DEBUG("Here,r=%d",r
);
1893 pPrivate
= get_sam3_bank_private(bank
);
1894 if (!(pPrivate
->probed
)) {
1895 return ERROR_FLASH_BANK_NOT_PROBED
;
1898 if ((first
== 0) && ((last
+ 1)== ((int)(pPrivate
->nsectors
)))) {
1901 return FLASHD_EraseEntireBank(pPrivate
);
1903 LOG_INFO("sam3 auto-erases while programing (request ignored)");
1908 sam3_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
1910 struct sam3_bank_private
*pPrivate
;
1914 if (bank
->target
->state
!= TARGET_HALTED
) {
1915 LOG_ERROR("Target not halted");
1916 return ERROR_TARGET_NOT_HALTED
;
1919 pPrivate
= get_sam3_bank_private(bank
);
1920 if (!(pPrivate
->probed
)) {
1921 return ERROR_FLASH_BANK_NOT_PROBED
;
1925 r
= FLASHD_Lock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
1927 r
= FLASHD_Unlock(pPrivate
, (unsigned)(first
), (unsigned)(last
));
1929 LOG_DEBUG("End: r=%d",r
);
1937 sam3_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
1939 if (bank
->target
->state
!= TARGET_HALTED
) {
1940 LOG_ERROR("Target not halted");
1941 return ERROR_TARGET_NOT_HALTED
;
1948 sam3_page_read(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
1953 adr
= pagenum
* pPrivate
->page_size
;
1954 adr
+= adr
+ pPrivate
->base_address
;
1956 r
= target_read_memory(pPrivate
->pChip
->target
,
1958 4, /* THIS*MUST*BE* in 32bit values */
1959 pPrivate
->page_size
/ 4,
1961 if (r
!= ERROR_OK
) {
1962 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x", (unsigned int)(adr
));
1967 // The code below is basically this:
1969 // arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s
1971 // Only the *CPU* can write to the flash buffer.
1972 // the DAP cannot... so - we download this 28byte thing
1973 // Run the algorithm - (below)
1974 // to program the device
1976 // ========================================
1977 // #include <stdint.h>
1981 // const uint32_t *src;
1983 // volatile uint32_t *base;
1988 // uint32_t sam3_function(struct foo *p)
1990 // volatile uint32_t *v;
1992 // const uint32_t *s;
2014 // ========================================
2018 static const uint8_t
2019 sam3_page_write_opcodes
[] = {
2020 // 24 0000 0446 mov r4, r0
2022 // 25 0002 6168 ldr r1, [r4, #4]
2024 // 26 0004 0068 ldr r0, [r0, #0]
2026 // 27 0006 A268 ldr r2, [r4, #8]
2028 // 28 @ lr needed for prologue
2030 // 30 0008 51F8043B ldr r3, [r1], #4
2031 0x51,0xf8,0x04,0x3b,
2032 // 31 000c 12F1FF32 adds r2, r2, #-1
2033 0x12,0xf1,0xff,0x32,
2034 // 32 0010 40F8043B str r3, [r0], #4
2035 0x40,0xf8,0x04,0x3b,
2036 // 33 0014 F8D1 bne .L2
2038 // 34 0016 E268 ldr r2, [r4, #12]
2040 // 35 0018 2369 ldr r3, [r4, #16]
2042 // 36 001a 5360 str r3, [r2, #4]
2044 // 37 001c 0832 adds r2, r2, #8
2047 // 39 001e 1068 ldr r0, [r2, #0]
2049 // 40 0020 10F0010F tst r0, #1
2050 0x10,0xf0,0x01,0x0f,
2051 // 41 0024 FBD0 beq .L4
2054 // 43 0026 FEE7 b .done
2060 sam3_page_write(struct sam3_bank_private
*pPrivate
, unsigned pagenum
, uint8_t *buf
)
2066 adr
= pagenum
* pPrivate
->page_size
;
2067 adr
+= (adr
+ pPrivate
->base_address
);
2069 LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum
, (unsigned int)(adr
));
2070 r
= target_write_memory(pPrivate
->pChip
->target
,
2072 4, /* THIS*MUST*BE* in 32bit values */
2073 pPrivate
->page_size
/ 4,
2075 if (r
!= ERROR_OK
) {
2076 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x", (unsigned int)(adr
));
2080 r
= EFC_PerformCommand(pPrivate
,
2081 // send Erase & Write Page
2086 if (r
!= ERROR_OK
) {
2087 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x", (unsigned int)(adr
));
2089 if (status
& (1 << 2)) {
2090 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr
));
2093 if (status
& (1 << 1)) {
2094 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr
));
2105 sam3_write(struct flash_bank
*bank
,
2114 unsigned page_offset
;
2115 struct sam3_bank_private
*pPrivate
;
2116 uint8_t *pagebuffer
;
2118 // incase we bail further below, set this to null
2121 // ignore dumb requests
2127 if (bank
->target
->state
!= TARGET_HALTED
) {
2128 LOG_ERROR("Target not halted");
2129 r
= ERROR_TARGET_NOT_HALTED
;
2133 pPrivate
= get_sam3_bank_private(bank
);
2134 if (!(pPrivate
->probed
)) {
2135 r
= ERROR_FLASH_BANK_NOT_PROBED
;
2140 if ((offset
+ count
) > pPrivate
->size_bytes
) {
2141 LOG_ERROR("Flash write error - past end of bank");
2142 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
2143 (unsigned int)(offset
),
2144 (unsigned int)(count
),
2145 (unsigned int)(pPrivate
->size_bytes
));
2150 pagebuffer
= malloc(pPrivate
->page_size
);
2152 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate
->page_size
));
2157 // what page do we start & end in?
2158 page_cur
= offset
/ pPrivate
->page_size
;
2159 page_end
= (offset
+ count
- 1) / pPrivate
->page_size
;
2161 LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset
), (unsigned int)(count
));
2162 LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur
), (int)(page_end
));
2164 // Special case: all one page
2167 // (1) non-aligned start
2169 // (3) non-aligned end.
2171 // Handle special case - all one page.
2172 if (page_cur
== page_end
) {
2173 LOG_DEBUG("Special case, all in one page");
2174 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2175 if (r
!= ERROR_OK
) {
2179 page_offset
= (offset
& (pPrivate
->page_size
-1));
2180 memcpy(pagebuffer
+ page_offset
,
2184 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2185 if (r
!= ERROR_OK
) {
2192 // non-aligned start
2193 page_offset
= offset
& (pPrivate
->page_size
- 1);
2195 LOG_DEBUG("Not-Aligned start");
2197 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2198 if (r
!= ERROR_OK
) {
2202 // over-write with new data
2203 n
= (pPrivate
->page_size
- page_offset
);
2204 memcpy(pagebuffer
+ page_offset
,
2208 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2209 if (r
!= ERROR_OK
) {
2219 // intermediate large pages
2220 // also - the final *terminal*
2221 // if that terminal page is a full page
2222 LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
2223 (int)page_cur
, (int)page_end
, (unsigned int)(count
));
2225 while ((page_cur
< page_end
) &&
2226 (count
>= pPrivate
->page_size
)) {
2227 r
= sam3_page_write(pPrivate
, page_cur
, buffer
);
2228 if (r
!= ERROR_OK
) {
2231 count
-= pPrivate
->page_size
;
2232 buffer
+= pPrivate
->page_size
;
2236 // terminal partial page?
2238 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count
));
2239 // we have a partial page
2240 r
= sam3_page_read(pPrivate
, page_cur
, pagebuffer
);
2241 if (r
!= ERROR_OK
) {
2244 // data goes at start
2245 memcpy(pagebuffer
, buffer
, count
);
2246 r
= sam3_page_write(pPrivate
, page_cur
, pagebuffer
);
2247 if (r
!= ERROR_OK
) {
2262 COMMAND_HANDLER(sam3_handle_info_command
)
2264 struct sam3_chip
*pChip
;
2270 pChip
= get_current_sam3(CMD_CTX
);
2277 // bank0 must exist before we can do anything
2278 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2281 command_print(CMD_CTX
,
2282 "Please define bank %d via command: flash bank %s ... ",
2284 at91sam3_flash
.name
);
2288 // if bank 0 is not probed, then probe it
2289 if (!(pChip
->details
.bank
[0].probed
)) {
2290 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
2291 if (r
!= ERROR_OK
) {
2295 // above garentees the "chip details" structure is valid
2296 // and thus, bank private areas are valid
2297 // and we have a SAM3 chip, what a concept!
2300 // auto-probe other banks, 0 done above
2301 for (x
= 1 ; x
< SAM3_MAX_FLASH_BANKS
; x
++) {
2302 // skip banks not present
2303 if (!(pChip
->details
.bank
[x
].present
)) {
2307 if (pChip
->details
.bank
[x
].pBank
== NULL
) {
2311 if (pChip
->details
.bank
[x
].probed
) {
2315 r
= sam3_auto_probe(pChip
->details
.bank
[x
].pBank
);
2316 if (r
!= ERROR_OK
) {
2322 r
= sam3_GetInfo(pChip
);
2323 if (r
!= ERROR_OK
) {
2324 LOG_DEBUG("Sam3Info, Failed %d\n",r
);
2330 cp
= membuf_strtok(pChip
->mbuf
, "\n", &vp
);
2332 command_print(CMD_CTX
,"%s", cp
);
2333 cp
= membuf_strtok(NULL
, "\n", &vp
);
2338 COMMAND_HANDLER(sam3_handle_gpnvm_command
)
2342 struct sam3_chip
*pChip
;
2344 pChip
= get_current_sam3(CMD_CTX
);
2349 if (pChip
->target
->state
!= TARGET_HALTED
) {
2350 LOG_ERROR("sam3 - target not halted");
2351 return ERROR_TARGET_NOT_HALTED
;
2355 if (pChip
->details
.bank
[0].pBank
== NULL
) {
2356 command_print(CMD_CTX
, "Bank0 must be defined first via: flash bank %s ...",
2357 at91sam3_flash
.name
);
2360 if (!pChip
->details
.bank
[0].probed
) {
2361 r
= sam3_auto_probe(pChip
->details
.bank
[0].pBank
);
2362 if (r
!= ERROR_OK
) {
2370 command_print(CMD_CTX
,"Too many parameters\n");
2371 return ERROR_COMMAND_SYNTAX_ERROR
;
2381 if ((0 == strcmp(CMD_ARGV
[0], "show")) && (0 == strcmp(CMD_ARGV
[1], "all"))) {
2385 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], v32
);
2391 if (0 == strcmp("show", CMD_ARGV
[0])) {
2395 for (x
= 0 ; x
< pChip
->details
.n_gpnvms
; x
++) {
2396 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), x
, &v
);
2397 if (r
!= ERROR_OK
) {
2400 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", x
, v
);
2404 if ((who
>= 0) && (((unsigned)(who
)) < pChip
->details
.n_gpnvms
)) {
2405 r
= FLASHD_GetGPNVM(&(pChip
->details
.bank
[0]), who
, &v
);
2406 command_print(CMD_CTX
, "sam3-gpnvm%u: %u", who
, v
);
2409 command_print(CMD_CTX
, "sam3-gpnvm invalid GPNVM: %u", who
);
2410 return ERROR_COMMAND_SYNTAX_ERROR
;
2415 command_print(CMD_CTX
, "Missing GPNVM number");
2416 return ERROR_COMMAND_SYNTAX_ERROR
;
2419 if (0 == strcmp("set", CMD_ARGV
[0])) {
2420 r
= FLASHD_SetGPNVM(&(pChip
->details
.bank
[0]), who
);
2421 } else if ((0 == strcmp("clr", CMD_ARGV
[0])) ||
2422 (0 == strcmp("clear", CMD_ARGV
[0]))) { // quietly accept both
2423 r
= FLASHD_ClrGPNVM(&(pChip
->details
.bank
[0]), who
);
2425 command_print(CMD_CTX
, "Unkown command: %s", CMD_ARGV
[0]);
2426 r
= ERROR_COMMAND_SYNTAX_ERROR
;
2431 COMMAND_HANDLER(sam3_handle_slowclk_command
)
2433 struct sam3_chip
*pChip
;
2435 pChip
= get_current_sam3(CMD_CTX
);
2449 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], v
);
2451 // absurd slow clock of 200Khz?
2452 command_print(CMD_CTX
,"Absurd/illegal slow clock freq: %d\n", (int)(v
));
2453 return ERROR_COMMAND_SYNTAX_ERROR
;
2455 pChip
->cfg
.slow_freq
= v
;
2460 command_print(CMD_CTX
,"Too many parameters");
2461 return ERROR_COMMAND_SYNTAX_ERROR
;
2464 command_print(CMD_CTX
, "Slowclk freq: %d.%03dkhz",
2465 (int)(pChip
->cfg
.slow_freq
/ 1000),
2466 (int)(pChip
->cfg
.slow_freq
% 1000));
2470 static const struct command_registration at91sam3_exec_command_handlers
[] = {
2473 .handler
= &sam3_handle_gpnvm_command
,
2474 .mode
= COMMAND_EXEC
,
2475 .usage
= "[(set|clear) [<bit_id>]]",
2476 .help
= "Without arguments, shows the gpnvm register; "
2477 "otherwise, sets or clear the specified bit.",
2481 .handler
= &sam3_handle_info_command
,
2482 .mode
= COMMAND_EXEC
,
2483 .help
= "print information about the current sam3 chip",
2487 .handler
= &sam3_handle_slowclk_command
,
2488 .mode
= COMMAND_EXEC
,
2490 .help
= "set the slowclock frequency (default 32768hz)",
2492 COMMAND_REGISTRATION_DONE
2494 static const struct command_registration at91sam3_command_handlers
[] = {
2497 .mode
= COMMAND_ANY
,
2498 .help
= "at91sam3 flash command group",
2499 .chain
= at91sam3_exec_command_handlers
,
2501 COMMAND_REGISTRATION_DONE
2504 struct flash_driver at91sam3_flash
= {
2506 .commands
= at91sam3_command_handlers
,
2507 .flash_bank_command
= &sam3_flash_bank_command
,
2508 .erase
= &sam3_erase
,
2509 .protect
= &sam3_protect
,
2510 .write
= &sam3_write
,
2511 .probe
= &sam3_probe
,
2512 .auto_probe
= &sam3_auto_probe
,
2513 .erase_check
= &sam3_erase_check
,
2514 .protect_check
= &sam3_protect_check
,
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