1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include <target/arm.h>
32 #include <helper/binarybuffer.h>
33 #include <target/algorithm.h>
36 #define CFI_MAX_BUS_WIDTH 4
37 #define CFI_MAX_CHIP_WIDTH 4
39 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
40 #define CFI_MAX_INTEL_CODESIZE 256
42 static struct cfi_unlock_addresses cfi_unlock_addresses
[] =
44 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
45 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
48 /* CFI fixups foward declarations */
49 static void cfi_fixup_0002_erase_regions(struct flash_bank
*flash
, void *param
);
50 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*flash
, void *param
);
51 static void cfi_fixup_reversed_erase_regions(struct flash_bank
*flash
, void *param
);
53 /* fixup after reading cmdset 0002 primary query table */
54 static const struct cfi_fixup cfi_0002_fixups
[] = {
55 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
56 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
57 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
58 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
59 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
60 {CFI_MFR_SST
, 0x236d, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
61 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_reversed_erase_regions
, NULL
},
62 {CFI_MFR_ST
, 0x22C4, cfi_fixup_reversed_erase_regions
, NULL
}, /* M29W160ET */
63 {CFI_MFR_FUJITSU
, 0x22ea, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
64 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
65 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
66 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
67 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
, &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
68 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
72 /* fixup after reading cmdset 0001 primary query table */
73 static const struct cfi_fixup cfi_0001_fixups
[] = {
77 static void cfi_fixup(struct flash_bank
*bank
, const struct cfi_fixup
*fixups
)
79 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
80 const struct cfi_fixup
*f
;
82 for (f
= fixups
; f
->fixup
; f
++)
84 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
85 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
87 f
->fixup(bank
, f
->param
);
92 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
93 static __inline__
uint32_t flash_address(struct flash_bank
*bank
, int sector
, uint32_t offset
)
95 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
97 if (cfi_info
->x16_as_x8
) offset
*= 2;
99 /* while the sector list isn't built, only accesses to sector 0 work */
101 return bank
->base
+ offset
* bank
->bus_width
;
106 LOG_ERROR("BUG: sector list not yet built");
109 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
113 static void cfi_command(struct flash_bank
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
117 /* clear whole buffer, to ensure bits that exceed the bus_width
120 for (i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
123 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
125 for (i
= bank
->bus_width
; i
> 0; i
--)
127 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
132 for (i
= 1; i
<= bank
->bus_width
; i
++)
134 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
139 static int cfi_send_command(struct flash_bank
*bank
, uint8_t cmd
, uint32_t address
)
141 uint8_t command
[CFI_MAX_BUS_WIDTH
];
143 cfi_command(bank
, cmd
, command
);
144 return target_write_memory(bank
->target
, address
, bank
->bus_width
, 1, command
);
147 /* read unsigned 8-bit value from the bank
148 * flash banks are expected to be made of similar chips
149 * the query result should be the same for all
151 static int cfi_query_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
153 struct target
*target
= bank
->target
;
154 uint8_t data
[CFI_MAX_BUS_WIDTH
];
157 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
158 if (retval
!= ERROR_OK
)
161 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
164 *val
= data
[bank
->bus_width
- 1];
169 /* read unsigned 8-bit value from the bank
170 * in case of a bank made of multiple chips,
171 * the individual values are ORed
173 static int cfi_get_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
175 struct target
*target
= bank
->target
;
176 uint8_t data
[CFI_MAX_BUS_WIDTH
];
180 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 1, data
);
181 if (retval
!= ERROR_OK
)
184 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
186 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
194 for (i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
195 value
|= data
[bank
->bus_width
- 1 - i
];
202 static int cfi_query_u16(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint16_t *val
)
204 struct target
*target
= bank
->target
;
205 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
206 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
209 if (cfi_info
->x16_as_x8
)
212 for (i
= 0;i
< 2;i
++)
214 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
215 &data
[i
*bank
->bus_width
]);
216 if (retval
!= ERROR_OK
)
221 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 2, data
);
222 if (retval
!= ERROR_OK
)
226 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
227 *val
= data
[0] | data
[bank
->bus_width
] << 8;
229 *val
= data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
234 static int cfi_query_u32(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint32_t *val
)
236 struct target
*target
= bank
->target
;
237 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
238 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
241 if (cfi_info
->x16_as_x8
)
244 for (i
= 0;i
< 4;i
++)
246 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
+ i
), bank
->bus_width
, 1,
247 &data
[i
*bank
->bus_width
]);
248 if (retval
!= ERROR_OK
)
254 retval
= target_read_memory(target
, flash_address(bank
, sector
, offset
), bank
->bus_width
, 4, data
);
255 if (retval
!= ERROR_OK
)
259 if (bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
)
260 *val
= data
[0] | data
[bank
->bus_width
] << 8 | data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
262 *val
= data
[bank
->bus_width
- 1] | data
[(2* bank
->bus_width
) - 1] << 8 |
263 data
[(3 * bank
->bus_width
) - 1] << 16 | data
[(4 * bank
->bus_width
) - 1] << 24;
268 static int cfi_reset(struct flash_bank
*bank
)
270 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
271 int retval
= ERROR_OK
;
273 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
278 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
283 if (cfi_info
->manufacturer
== 0x20 &&
284 (cfi_info
->device_id
== 0x227E || cfi_info
->device_id
== 0x7E))
286 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
287 * so we send an extra 0xF0 reset to fix the bug */
288 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x00))) != ERROR_OK
)
297 static void cfi_intel_clear_status_register(struct flash_bank
*bank
)
299 struct target
*target
= bank
->target
;
301 if (target
->state
!= TARGET_HALTED
)
303 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
307 cfi_send_command(bank
, 0x50, flash_address(bank
, 0, 0x0));
310 static int cfi_intel_wait_status_busy(struct flash_bank
*bank
, int timeout
, uint8_t *val
)
314 int retval
= ERROR_OK
;
320 LOG_ERROR("timeout while waiting for WSM to become ready");
324 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
325 if (retval
!= ERROR_OK
)
334 /* mask out bit 0 (reserved) */
335 status
= status
& 0xfe;
337 LOG_DEBUG("status: 0x%x", status
);
341 LOG_ERROR("status register: 0x%x", status
);
343 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
345 LOG_ERROR("Program suspended");
347 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
349 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
351 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
353 LOG_ERROR("Block Erase Suspended");
355 cfi_intel_clear_status_register(bank
);
364 static int cfi_spansion_wait_status_busy(struct flash_bank
*bank
, int timeout
)
366 uint8_t status
, oldstatus
;
367 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
370 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
371 if (retval
!= ERROR_OK
)
375 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
377 if (retval
!= ERROR_OK
)
380 if ((status
^ oldstatus
) & 0x40) {
381 if (status
& cfi_info
->status_poll_mask
& 0x20) {
382 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
383 if (retval
!= ERROR_OK
)
385 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
386 if (retval
!= ERROR_OK
)
388 if ((status
^ oldstatus
) & 0x40) {
389 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
390 return(ERROR_FLASH_OPERATION_FAILED
);
392 LOG_DEBUG("status: 0x%x", status
);
396 } else { /* no toggle: finished, OK */
397 LOG_DEBUG("status: 0x%x", status
);
403 } while (timeout
-- > 0);
405 LOG_ERROR("timeout, status: 0x%x", status
);
407 return(ERROR_FLASH_BUSY
);
410 static int cfi_read_intel_pri_ext(struct flash_bank
*bank
)
413 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
414 struct cfi_intel_pri_ext
*pri_ext
;
416 if (cfi_info
->pri_ext
)
417 free(cfi_info
->pri_ext
);
419 pri_ext
= malloc(sizeof(struct cfi_intel_pri_ext
));
422 LOG_ERROR("Out of memory");
425 cfi_info
->pri_ext
= pri_ext
;
427 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
428 if (retval
!= ERROR_OK
)
430 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
431 if (retval
!= ERROR_OK
)
433 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
434 if (retval
!= ERROR_OK
)
437 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
439 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
443 LOG_ERROR("Could not read bank flash bank information");
444 return ERROR_FLASH_BANK_INVALID
;
447 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
448 if (retval
!= ERROR_OK
)
450 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
451 if (retval
!= ERROR_OK
)
454 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
456 retval
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->feature_support
);
457 if (retval
!= ERROR_OK
)
459 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->suspend_cmd_support
);
460 if (retval
!= ERROR_OK
)
462 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa, &pri_ext
->blk_status_reg_mask
);
463 if (retval
!= ERROR_OK
)
466 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x",
467 pri_ext
->feature_support
,
468 pri_ext
->suspend_cmd_support
,
469 pri_ext
->blk_status_reg_mask
);
471 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc, &pri_ext
->vcc_optimal
);
472 if (retval
!= ERROR_OK
)
474 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd, &pri_ext
->vpp_optimal
);
475 if (retval
!= ERROR_OK
)
478 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
479 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
480 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
482 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe, &pri_ext
->num_protection_fields
);
483 if (retval
!= ERROR_OK
)
485 if (pri_ext
->num_protection_fields
!= 1)
487 LOG_WARNING("expected one protection register field, but found %i", pri_ext
->num_protection_fields
);
490 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf, &pri_ext
->prot_reg_addr
);
491 if (retval
!= ERROR_OK
)
493 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11, &pri_ext
->fact_prot_reg_size
);
494 if (retval
!= ERROR_OK
)
496 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12, &pri_ext
->user_prot_reg_size
);
497 if (retval
!= ERROR_OK
)
500 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
505 static int cfi_read_spansion_pri_ext(struct flash_bank
*bank
)
508 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
509 struct cfi_spansion_pri_ext
*pri_ext
;
511 if (cfi_info
->pri_ext
)
512 free(cfi_info
->pri_ext
);
514 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
517 LOG_ERROR("Out of memory");
520 cfi_info
->pri_ext
= pri_ext
;
522 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
523 if (retval
!= ERROR_OK
)
525 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
526 if (retval
!= ERROR_OK
)
528 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
529 if (retval
!= ERROR_OK
)
532 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I'))
534 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
538 LOG_ERROR("Could not read spansion bank information");
539 return ERROR_FLASH_BANK_INVALID
;
542 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
543 if (retval
!= ERROR_OK
)
545 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
546 if (retval
!= ERROR_OK
)
549 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
551 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->SiliconRevision
);
552 if (retval
!= ERROR_OK
)
554 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &pri_ext
->EraseSuspend
);
555 if (retval
!= ERROR_OK
)
557 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &pri_ext
->BlkProt
);
558 if (retval
!= ERROR_OK
)
560 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &pri_ext
->TmpBlkUnprotect
);
561 if (retval
!= ERROR_OK
)
563 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->BlkProtUnprot
);
564 if (retval
!= ERROR_OK
)
566 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10, &pri_ext
->SimultaneousOps
);
567 if (retval
!= ERROR_OK
)
569 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11, &pri_ext
->BurstMode
);
570 if (retval
!= ERROR_OK
)
572 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12, &pri_ext
->PageMode
);
573 if (retval
!= ERROR_OK
)
575 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13, &pri_ext
->VppMin
);
576 if (retval
!= ERROR_OK
)
578 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14, &pri_ext
->VppMax
);
579 if (retval
!= ERROR_OK
)
581 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15, &pri_ext
->TopBottom
);
582 if (retval
!= ERROR_OK
)
585 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext
->SiliconRevision
,
586 pri_ext
->EraseSuspend
, pri_ext
->BlkProt
);
588 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext
->TmpBlkUnprotect
,
589 pri_ext
->BlkProtUnprot
, pri_ext
->SimultaneousOps
);
591 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->BurstMode
, pri_ext
->PageMode
);
594 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
595 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
596 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
598 LOG_DEBUG("WP# protection 0x%x", pri_ext
->TopBottom
);
600 /* default values for implementation specific workarounds */
601 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
602 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
603 pri_ext
->_reversed_geometry
= 0;
608 static int cfi_read_atmel_pri_ext(struct flash_bank
*bank
)
611 struct cfi_atmel_pri_ext atmel_pri_ext
;
612 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
613 struct cfi_spansion_pri_ext
*pri_ext
;
615 if (cfi_info
->pri_ext
)
616 free(cfi_info
->pri_ext
);
618 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
621 LOG_ERROR("Out of memory");
625 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
626 * but a different primary extended query table.
627 * We read the atmel table, and prepare a valid AMD/Spansion query table.
630 memset(pri_ext
, 0, sizeof(struct cfi_spansion_pri_ext
));
632 cfi_info
->pri_ext
= pri_ext
;
634 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &atmel_pri_ext
.pri
[0]);
635 if (retval
!= ERROR_OK
)
637 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &atmel_pri_ext
.pri
[1]);
638 if (retval
!= ERROR_OK
)
640 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &atmel_pri_ext
.pri
[2]);
641 if (retval
!= ERROR_OK
)
644 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R') || (atmel_pri_ext
.pri
[2] != 'I'))
646 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
650 LOG_ERROR("Could not read atmel bank information");
651 return ERROR_FLASH_BANK_INVALID
;
654 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
655 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
656 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
658 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &atmel_pri_ext
.major_version
);
659 if (retval
!= ERROR_OK
)
661 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &atmel_pri_ext
.minor_version
);
662 if (retval
!= ERROR_OK
)
665 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0], atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2], atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
667 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
668 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
670 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &atmel_pri_ext
.features
);
671 if (retval
!= ERROR_OK
)
673 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &atmel_pri_ext
.bottom_boot
);
674 if (retval
!= ERROR_OK
)
676 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &atmel_pri_ext
.burst_mode
);
677 if (retval
!= ERROR_OK
)
679 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &atmel_pri_ext
.page_mode
);
680 if (retval
!= ERROR_OK
)
683 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
684 atmel_pri_ext
.features
, atmel_pri_ext
.bottom_boot
, atmel_pri_ext
.burst_mode
, atmel_pri_ext
.page_mode
);
686 if (atmel_pri_ext
.features
& 0x02)
687 pri_ext
->EraseSuspend
= 2;
689 if (atmel_pri_ext
.bottom_boot
)
690 pri_ext
->TopBottom
= 2;
692 pri_ext
->TopBottom
= 3;
694 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
695 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
700 static int cfi_read_0002_pri_ext(struct flash_bank
*bank
)
702 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
704 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
706 return cfi_read_atmel_pri_ext(bank
);
710 return cfi_read_spansion_pri_ext(bank
);
714 static int cfi_spansion_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
717 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
718 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
720 printed
= snprintf(buf
, buf_size
, "\nSpansion primary algorithm extend information:\n");
724 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0],
725 pri_ext
->pri
[1], pri_ext
->pri
[2],
726 pri_ext
->major_version
, pri_ext
->minor_version
);
730 printed
= snprintf(buf
, buf_size
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
731 (pri_ext
->SiliconRevision
) >> 2,
732 (pri_ext
->SiliconRevision
) & 0x03);
736 printed
= snprintf(buf
, buf_size
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
737 pri_ext
->EraseSuspend
,
742 printed
= snprintf(buf
, buf_size
, "VppMin: %u.%x, VppMax: %u.%x\n",
743 (pri_ext
->VppMin
& 0xf0) >> 4, pri_ext
->VppMin
& 0x0f,
744 (pri_ext
->VppMax
& 0xf0) >> 4, pri_ext
->VppMax
& 0x0f);
749 static int cfi_intel_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
752 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
753 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
755 printed
= snprintf(buf
, buf_size
, "\nintel primary algorithm extend information:\n");
759 printed
= snprintf(buf
, buf_size
, "pri: '%c%c%c', version: %c.%c\n", pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
763 printed
= snprintf(buf
, buf_size
, "feature_support: 0x%" PRIx32
", suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext
->feature_support
, pri_ext
->suspend_cmd_support
, pri_ext
->blk_status_reg_mask
);
767 printed
= snprintf(buf
, buf_size
, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
768 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
769 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
773 printed
= snprintf(buf
, buf_size
, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
, 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
778 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
780 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
782 struct cfi_flash_bank
*cfi_info
;
786 LOG_WARNING("incomplete flash_bank cfi configuration");
787 return ERROR_FLASH_BANK_INVALID
;
791 * - not exceed max value;
793 * - be equal to a power of 2.
794 * bus must be wide enought to hold one chip */
795 if ((bank
->chip_width
> CFI_MAX_CHIP_WIDTH
)
796 || (bank
->bus_width
> CFI_MAX_BUS_WIDTH
)
797 || (bank
->chip_width
== 0)
798 || (bank
->bus_width
== 0)
799 || (bank
->chip_width
& (bank
->chip_width
- 1))
800 || (bank
->bus_width
& (bank
->bus_width
- 1))
801 || (bank
->chip_width
> bank
->bus_width
))
803 LOG_ERROR("chip and bus width have to specified in bytes");
804 return ERROR_FLASH_BANK_INVALID
;
807 cfi_info
= malloc(sizeof(struct cfi_flash_bank
));
808 cfi_info
->probed
= 0;
809 cfi_info
->erase_region_info
= NULL
;
810 cfi_info
->pri_ext
= NULL
;
811 bank
->driver_priv
= cfi_info
;
813 cfi_info
->write_algorithm
= NULL
;
815 cfi_info
->x16_as_x8
= 0;
816 cfi_info
->jedec_probe
= 0;
817 cfi_info
->not_cfi
= 0;
819 for (unsigned i
= 6; i
< CMD_ARGC
; i
++)
821 if (strcmp(CMD_ARGV
[i
], "x16_as_x8") == 0)
823 cfi_info
->x16_as_x8
= 1;
825 else if (strcmp(CMD_ARGV
[i
], "jedec_probe") == 0)
827 cfi_info
->jedec_probe
= 1;
831 cfi_info
->write_algorithm
= NULL
;
833 /* bank wasn't probed yet */
834 cfi_info
->qry
[0] = 0xff;
839 static int cfi_intel_erase(struct flash_bank
*bank
, int first
, int last
)
842 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
845 cfi_intel_clear_status_register(bank
);
847 for (i
= first
; i
<= last
; i
++)
849 if ((retval
= cfi_send_command(bank
, 0x20, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
854 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
860 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
), &status
);
861 if (retval
!= ERROR_OK
)
865 bank
->sectors
[i
].is_erased
= 1;
868 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
873 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
874 return ERROR_FLASH_OPERATION_FAILED
;
878 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
881 static int cfi_spansion_erase(struct flash_bank
*bank
, int first
, int last
)
884 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
885 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
888 for (i
= first
; i
<= last
; i
++)
890 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
895 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
900 if ((retval
= cfi_send_command(bank
, 0x80, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
905 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
910 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
915 if ((retval
= cfi_send_command(bank
, 0x30, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
920 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->block_erase_timeout_typ
)) == ERROR_OK
)
921 bank
->sectors
[i
].is_erased
= 1;
924 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
929 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32
, i
, bank
->base
);
930 return ERROR_FLASH_OPERATION_FAILED
;
934 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
937 static int cfi_erase(struct flash_bank
*bank
, int first
, int last
)
939 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
941 if (bank
->target
->state
!= TARGET_HALTED
)
943 LOG_ERROR("Target not halted");
944 return ERROR_TARGET_NOT_HALTED
;
947 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
949 return ERROR_FLASH_SECTOR_INVALID
;
952 if (cfi_info
->qry
[0] != 'Q')
953 return ERROR_FLASH_BANK_NOT_PROBED
;
955 switch (cfi_info
->pri_id
)
959 return cfi_intel_erase(bank
, first
, last
);
962 return cfi_spansion_erase(bank
, first
, last
);
965 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
972 static int cfi_intel_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
975 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
976 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
980 /* if the device supports neither legacy lock/unlock (bit 3) nor
981 * instant individual block locking (bit 5).
983 if (!(pri_ext
->feature_support
& 0x28))
985 LOG_ERROR("lock/unlock not supported on flash");
986 return ERROR_FLASH_OPERATION_FAILED
;
989 cfi_intel_clear_status_register(bank
);
991 for (i
= first
; i
<= last
; i
++)
993 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
999 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1003 bank
->sectors
[i
].is_protected
= 1;
1007 if ((retval
= cfi_send_command(bank
, 0xd0, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1011 bank
->sectors
[i
].is_protected
= 0;
1014 /* instant individual block locking doesn't require reading of the status register */
1015 if (!(pri_ext
->feature_support
& 0x20))
1017 /* Clear lock bits operation may take up to 1.4s */
1019 retval
= cfi_intel_wait_status_busy(bank
, 1400, &status
);
1020 if (retval
!= ERROR_OK
)
1025 uint8_t block_status
;
1026 /* read block lock bit, to verify status */
1027 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
1031 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
1032 if (retval
!= ERROR_OK
)
1035 if ((block_status
& 0x1) != set
)
1037 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set
, block_status
);
1038 if ((retval
= cfi_send_command(bank
, 0x70, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
1043 retval
= cfi_intel_wait_status_busy(bank
, 10, &status
);
1044 if (retval
!= ERROR_OK
)
1048 return ERROR_FLASH_OPERATION_FAILED
;
1058 /* if the device doesn't support individual block lock bits set/clear,
1059 * all blocks have been unlocked in parallel, so we set those that should be protected
1061 if ((!set
) && (!(pri_ext
->feature_support
& 0x20)))
1063 /* FIX!!! this code path is broken!!!
1065 * The correct approach is:
1067 * 1. read out current protection status
1069 * 2. override read out protection status w/unprotected.
1071 * 3. re-protect what should be protected.
1074 for (i
= 0; i
< bank
->num_sectors
; i
++)
1076 if (bank
->sectors
[i
].is_protected
== 1)
1078 cfi_intel_clear_status_register(bank
);
1080 if ((retval
= cfi_send_command(bank
, 0x60, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1085 if ((retval
= cfi_send_command(bank
, 0x01, flash_address(bank
, i
, 0x0))) != ERROR_OK
)
1091 retval
= cfi_intel_wait_status_busy(bank
, 100, &status
);
1092 if (retval
!= ERROR_OK
)
1098 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
1101 static int cfi_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
1103 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1105 if (bank
->target
->state
!= TARGET_HALTED
)
1107 LOG_ERROR("Target not halted");
1108 return ERROR_TARGET_NOT_HALTED
;
1111 if ((first
< 0) || (last
< first
) || (last
>= bank
->num_sectors
))
1113 LOG_ERROR("Invalid sector range");
1114 return ERROR_FLASH_SECTOR_INVALID
;
1117 if (cfi_info
->qry
[0] != 'Q')
1118 return ERROR_FLASH_BANK_NOT_PROBED
;
1120 switch (cfi_info
->pri_id
)
1124 return cfi_intel_protect(bank
, set
, first
, last
);
1127 LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
1132 /* Convert code image to target endian */
1133 /* FIXME create general block conversion fcts in target.c?) */
1134 static void cfi_fix_code_endian(struct target
*target
, uint8_t *dest
, const uint32_t *src
, uint32_t count
)
1137 for (i
= 0; i
< count
; i
++)
1139 target_buffer_set_u32(target
, dest
, *src
);
1145 static uint32_t cfi_command_val(struct flash_bank
*bank
, uint8_t cmd
)
1147 struct target
*target
= bank
->target
;
1149 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
1150 cfi_command(bank
, cmd
, buf
);
1151 switch (bank
->bus_width
)
1157 return target_buffer_get_u16(target
, buf
);
1160 return target_buffer_get_u32(target
, buf
);
1163 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1168 static int cfi_intel_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1170 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1171 struct target
*target
= bank
->target
;
1172 struct reg_param reg_params
[7];
1173 struct arm_algorithm armv4_5_info
;
1174 struct working_area
*source
;
1175 uint32_t buffer_size
= 32768;
1176 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
1178 /* algorithm register usage:
1179 * r0: source address (in RAM)
1180 * r1: target address (in Flash)
1182 * r3: flash write command
1183 * r4: status byte (returned to host)
1184 * r5: busy test pattern
1185 * r6: error test pattern
1188 static const uint32_t word_32_code
[] = {
1189 0xe4904004, /* loop: ldr r4, [r0], #4 */
1190 0xe5813000, /* str r3, [r1] */
1191 0xe5814000, /* str r4, [r1] */
1192 0xe5914000, /* busy: ldr r4, [r1] */
1193 0xe0047005, /* and r7, r4, r5 */
1194 0xe1570005, /* cmp r7, r5 */
1195 0x1afffffb, /* bne busy */
1196 0xe1140006, /* tst r4, r6 */
1197 0x1a000003, /* bne done */
1198 0xe2522001, /* subs r2, r2, #1 */
1199 0x0a000001, /* beq done */
1200 0xe2811004, /* add r1, r1 #4 */
1201 0xeafffff2, /* b loop */
1202 0xeafffffe /* done: b -2 */
1205 static const uint32_t word_16_code
[] = {
1206 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1207 0xe1c130b0, /* strh r3, [r1] */
1208 0xe1c140b0, /* strh r4, [r1] */
1209 0xe1d140b0, /* busy ldrh r4, [r1] */
1210 0xe0047005, /* and r7, r4, r5 */
1211 0xe1570005, /* cmp r7, r5 */
1212 0x1afffffb, /* bne busy */
1213 0xe1140006, /* tst r4, r6 */
1214 0x1a000003, /* bne done */
1215 0xe2522001, /* subs r2, r2, #1 */
1216 0x0a000001, /* beq done */
1217 0xe2811002, /* add r1, r1 #2 */
1218 0xeafffff2, /* b loop */
1219 0xeafffffe /* done: b -2 */
1222 static const uint32_t word_8_code
[] = {
1223 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1224 0xe5c13000, /* strb r3, [r1] */
1225 0xe5c14000, /* strb r4, [r1] */
1226 0xe5d14000, /* busy ldrb r4, [r1] */
1227 0xe0047005, /* and r7, r4, r5 */
1228 0xe1570005, /* cmp r7, r5 */
1229 0x1afffffb, /* bne busy */
1230 0xe1140006, /* tst r4, r6 */
1231 0x1a000003, /* bne done */
1232 0xe2522001, /* subs r2, r2, #1 */
1233 0x0a000001, /* beq done */
1234 0xe2811001, /* add r1, r1 #1 */
1235 0xeafffff2, /* b loop */
1236 0xeafffffe /* done: b -2 */
1238 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1239 const uint32_t *target_code_src
;
1240 uint32_t target_code_size
;
1241 int retval
= ERROR_OK
;
1244 cfi_intel_clear_status_register(bank
);
1246 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1247 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1248 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1250 /* If we are setting up the write_algorith, we need target_code_src */
1251 /* if not we only need target_code_size. */
1253 /* However, we don't want to create multiple code paths, so we */
1254 /* do the unecessary evaluation of target_code_src, which the */
1255 /* compiler will probably nicely optimize away if not needed */
1257 /* prepare algorithm code for target endian */
1258 switch (bank
->bus_width
)
1261 target_code_src
= word_8_code
;
1262 target_code_size
= sizeof(word_8_code
);
1265 target_code_src
= word_16_code
;
1266 target_code_size
= sizeof(word_16_code
);
1269 target_code_src
= word_32_code
;
1270 target_code_size
= sizeof(word_32_code
);
1273 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1274 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1277 /* flash write code */
1278 if (!cfi_info
->write_algorithm
)
1280 if (target_code_size
> sizeof(target_code
))
1282 LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1283 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1285 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1287 /* Get memory for block write handler */
1288 retval
= target_alloc_working_area(target
, target_code_size
, &cfi_info
->write_algorithm
);
1289 if (retval
!= ERROR_OK
)
1291 LOG_WARNING("No working area available, can't do block memory writes");
1292 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1295 /* write algorithm code to working area */
1296 retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
, target_code_size
, target_code
);
1297 if (retval
!= ERROR_OK
)
1299 LOG_ERROR("Unable to write block write code to target");
1304 /* Get a workspace buffer for the data to flash starting with 32k size.
1305 Half size until buffer would be smaller 256 Bytem then fail back */
1306 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1307 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1310 if (buffer_size
<= 256)
1312 LOG_WARNING("no large enough working area available, can't do block memory writes");
1313 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1318 /* setup algo registers */
1319 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1320 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1321 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1322 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1323 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1324 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1325 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1327 /* prepare command and status register patterns */
1328 write_command_val
= cfi_command_val(bank
, 0x40);
1329 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1330 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1332 LOG_DEBUG("Using target buffer at 0x%08" PRIx32
" and of size 0x%04" PRIx32
, source
->address
, buffer_size
);
1334 /* Programming main loop */
1337 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1340 if ((retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
)) != ERROR_OK
)
1345 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1346 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1347 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1349 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1350 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1351 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1353 LOG_DEBUG("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
, thisrun_count
, address
);
1355 /* Execute algorithm, assume breakpoint for last instruction */
1356 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1357 cfi_info
->write_algorithm
->address
,
1358 cfi_info
->write_algorithm
->address
+ target_code_size
- sizeof(uint32_t),
1359 10000, /* 10s should be enough for max. 32k of data */
1362 /* On failure try a fall back to direct word writes */
1363 if (retval
!= ERROR_OK
)
1365 cfi_intel_clear_status_register(bank
);
1366 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1367 retval
= ERROR_FLASH_OPERATION_FAILED
;
1368 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1369 /* FIXME To allow fall back or recovery, we must save the actual status
1370 somewhere, so that a higher level code can start recovery. */
1374 /* Check return value from algo code */
1375 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1378 /* read status register (outputs debug inforation) */
1380 cfi_intel_wait_status_busy(bank
, 100, &status
);
1381 cfi_intel_clear_status_register(bank
);
1382 retval
= ERROR_FLASH_OPERATION_FAILED
;
1386 buffer
+= thisrun_count
;
1387 address
+= thisrun_count
;
1388 count
-= thisrun_count
;
1393 /* free up resources */
1396 target_free_working_area(target
, source
);
1398 if (cfi_info
->write_algorithm
)
1400 target_free_working_area(target
, cfi_info
->write_algorithm
);
1401 cfi_info
->write_algorithm
= NULL
;
1404 destroy_reg_param(®_params
[0]);
1405 destroy_reg_param(®_params
[1]);
1406 destroy_reg_param(®_params
[2]);
1407 destroy_reg_param(®_params
[3]);
1408 destroy_reg_param(®_params
[4]);
1409 destroy_reg_param(®_params
[5]);
1410 destroy_reg_param(®_params
[6]);
1415 static int cfi_spansion_write_block(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t address
, uint32_t count
)
1417 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1418 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1419 struct target
*target
= bank
->target
;
1420 struct reg_param reg_params
[10];
1421 struct arm_algorithm armv4_5_info
;
1422 struct working_area
*source
;
1423 uint32_t buffer_size
= 32768;
1425 int retval
= ERROR_OK
;
1427 /* input parameters - */
1428 /* R0 = source address */
1429 /* R1 = destination address */
1430 /* R2 = number of writes */
1431 /* R3 = flash write command */
1432 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1433 /* output parameters - */
1434 /* R5 = 0x80 ok 0x00 bad */
1435 /* temp registers - */
1436 /* R6 = value read from flash to test status */
1437 /* R7 = holding register */
1438 /* unlock registers - */
1439 /* R8 = unlock1_addr */
1440 /* R9 = unlock1_cmd */
1441 /* R10 = unlock2_addr */
1442 /* R11 = unlock2_cmd */
1444 static const uint32_t word_32_code
[] = {
1445 /* 00008100 <sp_32_code>: */
1446 0xe4905004, /* ldr r5, [r0], #4 */
1447 0xe5889000, /* str r9, [r8] */
1448 0xe58ab000, /* str r11, [r10] */
1449 0xe5883000, /* str r3, [r8] */
1450 0xe5815000, /* str r5, [r1] */
1451 0xe1a00000, /* nop */
1453 /* 00008110 <sp_32_busy>: */
1454 0xe5916000, /* ldr r6, [r1] */
1455 0xe0257006, /* eor r7, r5, r6 */
1456 0xe0147007, /* ands r7, r4, r7 */
1457 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1458 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1459 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1460 0xe5916000, /* ldr r6, [r1] */
1461 0xe0257006, /* eor r7, r5, r6 */
1462 0xe0147007, /* ands r7, r4, r7 */
1463 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1464 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1465 0x1a000004, /* bne 8154 <sp_32_done> */
1467 /* 00008140 <sp_32_cont>: */
1468 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1469 0x03a05080, /* moveq r5, #128 ; 0x80 */
1470 0x0a000001, /* beq 8154 <sp_32_done> */
1471 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1472 0xeaffffe8, /* b 8100 <sp_32_code> */
1474 /* 00008154 <sp_32_done>: */
1475 0xeafffffe /* b 8154 <sp_32_done> */
1478 static const uint32_t word_16_code
[] = {
1479 /* 00008158 <sp_16_code>: */
1480 0xe0d050b2, /* ldrh r5, [r0], #2 */
1481 0xe1c890b0, /* strh r9, [r8] */
1482 0xe1cab0b0, /* strh r11, [r10] */
1483 0xe1c830b0, /* strh r3, [r8] */
1484 0xe1c150b0, /* strh r5, [r1] */
1485 0xe1a00000, /* nop (mov r0,r0) */
1487 /* 00008168 <sp_16_busy>: */
1488 0xe1d160b0, /* ldrh r6, [r1] */
1489 0xe0257006, /* eor r7, r5, r6 */
1490 0xe0147007, /* ands r7, r4, r7 */
1491 0x0a000007, /* beq 8198 <sp_16_cont> */
1492 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1493 0x0afffff9, /* beq 8168 <sp_16_busy> */
1494 0xe1d160b0, /* ldrh r6, [r1] */
1495 0xe0257006, /* eor r7, r5, r6 */
1496 0xe0147007, /* ands r7, r4, r7 */
1497 0x0a000001, /* beq 8198 <sp_16_cont> */
1498 0xe3a05000, /* mov r5, #0 ; 0x0 */
1499 0x1a000004, /* bne 81ac <sp_16_done> */
1501 /* 00008198 <sp_16_cont>: */
1502 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1503 0x03a05080, /* moveq r5, #128 ; 0x80 */
1504 0x0a000001, /* beq 81ac <sp_16_done> */
1505 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1506 0xeaffffe8, /* b 8158 <sp_16_code> */
1508 /* 000081ac <sp_16_done>: */
1509 0xeafffffe /* b 81ac <sp_16_done> */
1512 static const uint32_t word_16_code_dq7only
[] = {
1514 0xe0d050b2, /* ldrh r5, [r0], #2 */
1515 0xe1c890b0, /* strh r9, [r8] */
1516 0xe1cab0b0, /* strh r11, [r10] */
1517 0xe1c830b0, /* strh r3, [r8] */
1518 0xe1c150b0, /* strh r5, [r1] */
1519 0xe1a00000, /* nop (mov r0,r0) */
1522 0xe1d160b0, /* ldrh r6, [r1] */
1523 0xe0257006, /* eor r7, r5, r6 */
1524 0xe2177080, /* ands r7, #0x80 */
1525 0x1afffffb, /* bne 8168 <sp_16_busy> */
1527 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1528 0x03a05080, /* moveq r5, #128 ; 0x80 */
1529 0x0a000001, /* beq 81ac <sp_16_done> */
1530 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1531 0xeafffff0, /* b 8158 <sp_16_code> */
1533 /* 000081ac <sp_16_done>: */
1534 0xeafffffe /* b 81ac <sp_16_done> */
1537 static const uint32_t word_8_code
[] = {
1538 /* 000081b0 <sp_16_code_end>: */
1539 0xe4d05001, /* ldrb r5, [r0], #1 */
1540 0xe5c89000, /* strb r9, [r8] */
1541 0xe5cab000, /* strb r11, [r10] */
1542 0xe5c83000, /* strb r3, [r8] */
1543 0xe5c15000, /* strb r5, [r1] */
1544 0xe1a00000, /* nop (mov r0,r0) */
1546 /* 000081c0 <sp_8_busy>: */
1547 0xe5d16000, /* ldrb r6, [r1] */
1548 0xe0257006, /* eor r7, r5, r6 */
1549 0xe0147007, /* ands r7, r4, r7 */
1550 0x0a000007, /* beq 81f0 <sp_8_cont> */
1551 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1552 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1553 0xe5d16000, /* ldrb r6, [r1] */
1554 0xe0257006, /* eor r7, r5, r6 */
1555 0xe0147007, /* ands r7, r4, r7 */
1556 0x0a000001, /* beq 81f0 <sp_8_cont> */
1557 0xe3a05000, /* mov r5, #0 ; 0x0 */
1558 0x1a000004, /* bne 8204 <sp_8_done> */
1560 /* 000081f0 <sp_8_cont>: */
1561 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1562 0x03a05080, /* moveq r5, #128 ; 0x80 */
1563 0x0a000001, /* beq 8204 <sp_8_done> */
1564 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1565 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1567 /* 00008204 <sp_8_done>: */
1568 0xeafffffe /* b 8204 <sp_8_done> */
1571 armv4_5_info
.common_magic
= ARM_COMMON_MAGIC
;
1572 armv4_5_info
.core_mode
= ARM_MODE_SVC
;
1573 armv4_5_info
.core_state
= ARM_STATE_ARM
;
1575 int target_code_size
;
1576 const uint32_t *target_code_src
;
1578 switch (bank
->bus_width
)
1581 target_code_src
= word_8_code
;
1582 target_code_size
= sizeof(word_8_code
);
1585 /* Check for DQ5 support */
1586 if( cfi_info
->status_poll_mask
& (1 << 5) )
1588 target_code_src
= word_16_code
;
1589 target_code_size
= sizeof(word_16_code
);
1593 /* No DQ5 support. Use DQ7 DATA# polling only. */
1594 target_code_src
= word_16_code_dq7only
;
1595 target_code_size
= sizeof(word_16_code_dq7only
);
1599 target_code_src
= word_32_code
;
1600 target_code_size
= sizeof(word_32_code
);
1603 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank
->bus_width
);
1604 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1607 /* flash write code */
1608 if (!cfi_info
->write_algorithm
)
1610 uint8_t *target_code
;
1612 /* convert bus-width dependent algorithm code to correct endiannes */
1613 target_code
= malloc(target_code_size
);
1614 if (target_code
== NULL
)
1616 LOG_ERROR("Out of memory");
1619 cfi_fix_code_endian(target
, target_code
, target_code_src
, target_code_size
/ 4);
1621 /* allocate working area */
1622 retval
= target_alloc_working_area(target
, target_code_size
,
1623 &cfi_info
->write_algorithm
);
1624 if (retval
!= ERROR_OK
)
1630 /* write algorithm code to working area */
1631 if ((retval
= target_write_buffer(target
, cfi_info
->write_algorithm
->address
,
1632 target_code_size
, target_code
)) != ERROR_OK
)
1640 /* the following code still assumes target code is fixed 24*4 bytes */
1642 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
)
1645 if (buffer_size
<= 256)
1647 /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1648 if (cfi_info
->write_algorithm
)
1649 target_free_working_area(target
, cfi_info
->write_algorithm
);
1651 LOG_WARNING("not enough working area available, can't do block memory writes");
1652 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1656 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1657 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1658 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1659 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1660 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1661 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1662 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1663 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1664 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1665 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1669 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1671 retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1672 if (retval
!= ERROR_OK
)
1677 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1678 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1679 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1680 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1681 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1682 buf_set_u32(reg_params
[6].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock1
));
1683 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1684 buf_set_u32(reg_params
[8].value
, 0, 32, flash_address(bank
, 0, pri_ext
->_unlock2
));
1685 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1687 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1688 cfi_info
->write_algorithm
->address
,
1689 cfi_info
->write_algorithm
->address
+ ((target_code_size
) - 4),
1690 10000, &armv4_5_info
);
1691 if (retval
!= ERROR_OK
)
1696 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1699 LOG_ERROR("flash write block failed status: 0x%" PRIx32
, status
);
1700 retval
= ERROR_FLASH_OPERATION_FAILED
;
1704 buffer
+= thisrun_count
;
1705 address
+= thisrun_count
;
1706 count
-= thisrun_count
;
1709 target_free_all_working_areas(target
);
1711 destroy_reg_param(®_params
[0]);
1712 destroy_reg_param(®_params
[1]);
1713 destroy_reg_param(®_params
[2]);
1714 destroy_reg_param(®_params
[3]);
1715 destroy_reg_param(®_params
[4]);
1716 destroy_reg_param(®_params
[5]);
1717 destroy_reg_param(®_params
[6]);
1718 destroy_reg_param(®_params
[7]);
1719 destroy_reg_param(®_params
[8]);
1720 destroy_reg_param(®_params
[9]);
1725 static int cfi_intel_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1728 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1729 struct target
*target
= bank
->target
;
1731 cfi_intel_clear_status_register(bank
);
1732 if ((retval
= cfi_send_command(bank
, 0x40, address
)) != ERROR_OK
)
1737 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1743 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
), &status
);
1746 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1751 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1752 return ERROR_FLASH_OPERATION_FAILED
;
1758 static int cfi_intel_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1761 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1762 struct target
*target
= bank
->target
;
1764 /* Calculate buffer size and boundary mask */
1765 /* buffersize is (buffer size per chip) * (number of chips) */
1766 /* bufferwsize is buffersize in words */
1767 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1768 uint32_t buffermask
= buffersize
-1;
1769 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
1771 /* Check for valid range */
1772 if (address
& buffermask
)
1774 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary",
1775 bank
->base
, address
, cfi_info
->max_buf_write_size
);
1776 return ERROR_FLASH_OPERATION_FAILED
;
1779 /* Check for valid size */
1780 if (wordcount
> bufferwsize
)
1782 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1783 return ERROR_FLASH_OPERATION_FAILED
;
1786 /* Write to flash buffer */
1787 cfi_intel_clear_status_register(bank
);
1789 /* Initiate buffer operation _*/
1790 if ((retval
= cfi_send_command(bank
, 0xe8, address
)) != ERROR_OK
)
1795 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
), &status
);
1796 if (retval
!= ERROR_OK
)
1800 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1805 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1806 return ERROR_FLASH_OPERATION_FAILED
;
1809 /* Write buffer wordcount-1 and data words */
1810 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1815 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1820 /* Commit write operation */
1821 if ((retval
= cfi_send_command(bank
, 0xd0, address
)) != ERROR_OK
)
1826 retval
= cfi_intel_wait_status_busy(bank
, 1000 * (1 << cfi_info
->buf_write_timeout_max
), &status
);
1827 if (retval
!= ERROR_OK
)
1832 if ((retval
= cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1837 LOG_ERROR("Buffer write at base 0x%" PRIx32
", address %" PRIx32
" failed.", bank
->base
, address
);
1838 return ERROR_FLASH_OPERATION_FAILED
;
1844 static int cfi_spansion_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1847 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1848 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1849 struct target
*target
= bank
->target
;
1851 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1856 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1861 if ((retval
= cfi_send_command(bank
, 0xa0, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1866 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, 1, word
)) != ERROR_OK
)
1871 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1873 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1878 LOG_ERROR("couldn't write word at base 0x%" PRIx32
", address %" PRIx32
, bank
->base
, address
);
1879 return ERROR_FLASH_OPERATION_FAILED
;
1885 static int cfi_spansion_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1888 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1889 struct target
*target
= bank
->target
;
1890 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1892 /* Calculate buffer size and boundary mask */
1893 /* buffersize is (buffer size per chip) * (number of chips) */
1894 /* bufferwsize is buffersize in words */
1895 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
1896 uint32_t buffermask
= buffersize
-1;
1897 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
1899 /* Check for valid range */
1900 if (address
& buffermask
)
1902 LOG_ERROR("Write address at base 0x%" PRIx32
", address %" PRIx32
" not aligned to 2^%d boundary", bank
->base
, address
, cfi_info
->max_buf_write_size
);
1903 return ERROR_FLASH_OPERATION_FAILED
;
1906 /* Check for valid size */
1907 if (wordcount
> bufferwsize
)
1909 LOG_ERROR("Number of data words %" PRId32
" exceeds available buffersize %" PRId32
, wordcount
, buffersize
);
1910 return ERROR_FLASH_OPERATION_FAILED
;
1914 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
1919 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
1924 // Buffer load command
1925 if ((retval
= cfi_send_command(bank
, 0x25, address
)) != ERROR_OK
)
1930 /* Write buffer wordcount-1 and data words */
1931 if ((retval
= cfi_send_command(bank
, bufferwsize
-1, address
)) != ERROR_OK
)
1936 if ((retval
= target_write_memory(target
, address
, bank
->bus_width
, bufferwsize
, word
)) != ERROR_OK
)
1941 /* Commit write operation */
1942 if ((retval
= cfi_send_command(bank
, 0x29, address
)) != ERROR_OK
)
1947 if (cfi_spansion_wait_status_busy(bank
, 1000 * (1 << cfi_info
->word_write_timeout_max
)) != ERROR_OK
)
1949 if ((retval
= cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0))) != ERROR_OK
)
1954 LOG_ERROR("couldn't write block at base 0x%" PRIx32
", address %" PRIx32
", size %" PRIx32
, bank
->base
, address
, bufferwsize
);
1955 return ERROR_FLASH_OPERATION_FAILED
;
1961 static int cfi_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1963 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1965 switch (cfi_info
->pri_id
)
1969 return cfi_intel_write_word(bank
, word
, address
);
1972 return cfi_spansion_write_word(bank
, word
, address
);
1975 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
1979 return ERROR_FLASH_OPERATION_FAILED
;
1982 static int cfi_write_words(struct flash_bank
*bank
, uint8_t *word
, uint32_t wordcount
, uint32_t address
)
1984 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1986 switch (cfi_info
->pri_id
)
1990 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
1993 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
1996 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2000 return ERROR_FLASH_OPERATION_FAILED
;
2003 static int cfi_read(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2005 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2006 struct target
*target
= bank
->target
;
2007 uint32_t address
= bank
->base
+ offset
;
2009 int align
; /* number of unaligned bytes */
2010 uint8_t current_word
[CFI_MAX_BUS_WIDTH
];
2014 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2015 (int)count
, (unsigned)offset
);
2017 if (bank
->target
->state
!= TARGET_HALTED
)
2019 LOG_ERROR("Target not halted");
2020 return ERROR_TARGET_NOT_HALTED
;
2023 if (offset
+ count
> bank
->size
)
2024 return ERROR_FLASH_DST_OUT_OF_BANK
;
2026 if (cfi_info
->qry
[0] != 'Q')
2027 return ERROR_FLASH_BANK_NOT_PROBED
;
2029 /* start at the first byte of the first word (bus_width size) */
2030 read_p
= address
& ~(bank
->bus_width
- 1);
2031 if ((align
= address
- read_p
) != 0)
2033 LOG_INFO("Fixup %d unaligned read head bytes", align
);
2035 /* read a complete word from flash */
2036 if ((retval
= target_read_memory(target
, read_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2039 /* take only bytes we need */
2040 for (i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2041 *buffer
++ = current_word
[i
];
2043 read_p
+= bank
->bus_width
;
2046 align
= count
/ bank
->bus_width
;
2049 if ((retval
= target_read_memory(target
, read_p
, bank
->bus_width
, align
, buffer
)) != ERROR_OK
)
2052 read_p
+= align
* bank
->bus_width
;
2053 buffer
+= align
* bank
->bus_width
;
2054 count
-= align
* bank
->bus_width
;
2059 LOG_INFO("Fixup %d unaligned read tail bytes", count
);
2061 /* read a complete word from flash */
2062 if ((retval
= target_read_memory(target
, read_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2065 /* take only bytes we need */
2066 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2067 *buffer
++ = current_word
[i
];
2073 static int cfi_write(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2075 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2076 struct target
*target
= bank
->target
;
2077 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
2079 int align
; /* number of unaligned bytes */
2080 int blk_count
; /* number of bus_width bytes for block copy */
2081 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being programmed */
2085 if (bank
->target
->state
!= TARGET_HALTED
)
2087 LOG_ERROR("Target not halted");
2088 return ERROR_TARGET_NOT_HALTED
;
2091 if (offset
+ count
> bank
->size
)
2092 return ERROR_FLASH_DST_OUT_OF_BANK
;
2094 if (cfi_info
->qry
[0] != 'Q')
2095 return ERROR_FLASH_BANK_NOT_PROBED
;
2097 /* start at the first byte of the first word (bus_width size) */
2098 write_p
= address
& ~(bank
->bus_width
- 1);
2099 if ((align
= address
- write_p
) != 0)
2101 LOG_INFO("Fixup %d unaligned head bytes", align
);
2103 /* read a complete word from flash */
2104 if ((retval
= target_read_memory(target
, write_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2107 /* replace only bytes that must be written */
2108 for (i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2109 current_word
[i
] = *buffer
++;
2111 retval
= cfi_write_word(bank
, current_word
, write_p
);
2112 if (retval
!= ERROR_OK
)
2114 write_p
+= bank
->bus_width
;
2117 /* handle blocks of bus_size aligned bytes */
2118 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
2119 switch (cfi_info
->pri_id
)
2121 /* try block writes (fails without working area) */
2124 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
2127 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
2130 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2131 retval
= ERROR_FLASH_OPERATION_FAILED
;
2134 if (retval
== ERROR_OK
)
2136 /* Increment pointers and decrease count on succesful block write */
2137 buffer
+= blk_count
;
2138 write_p
+= blk_count
;
2143 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
)
2145 /* Calculate buffer size and boundary mask */
2146 /* buffersize is (buffer size per chip) * (number of chips) */
2147 /* bufferwsize is buffersize in words */
2148 uint32_t buffersize
= (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
2149 uint32_t buffermask
= buffersize
-1;
2150 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
2152 /* fall back to memory writes */
2153 while (count
>= (uint32_t)bank
->bus_width
)
2156 if ((write_p
& 0xff) == 0)
2158 LOG_INFO("Programming at %08" PRIx32
", count %08" PRIx32
" bytes remaining", write_p
, count
);
2161 if ((bufferwsize
> 0) && (count
>= buffersize
) && !(write_p
& buffermask
))
2163 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
2164 if (retval
== ERROR_OK
)
2166 buffer
+= buffersize
;
2167 write_p
+= buffersize
;
2168 count
-= buffersize
;
2172 /* try the slow way? */
2175 for (i
= 0; i
< bank
->bus_width
; i
++)
2176 current_word
[i
] = *buffer
++;
2178 retval
= cfi_write_word(bank
, current_word
, write_p
);
2179 if (retval
!= ERROR_OK
)
2182 write_p
+= bank
->bus_width
;
2183 count
-= bank
->bus_width
;
2191 /* return to read array mode, so we can read from flash again for padding */
2192 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2197 /* handle unaligned tail bytes */
2200 LOG_INFO("Fixup %" PRId32
" unaligned tail bytes", count
);
2202 /* read a complete word from flash */
2203 if ((retval
= target_read_memory(target
, write_p
, bank
->bus_width
, 1, current_word
)) != ERROR_OK
)
2206 /* replace only bytes that must be written */
2207 for (i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2208 current_word
[i
] = *buffer
++;
2210 retval
= cfi_write_word(bank
, current_word
, write_p
);
2211 if (retval
!= ERROR_OK
)
2215 /* return to read array mode */
2216 return cfi_reset(bank
);
2219 static void cfi_fixup_reversed_erase_regions(struct flash_bank
*bank
, void *param
)
2222 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2223 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2225 pri_ext
->_reversed_geometry
= 1;
2228 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, void *param
)
2231 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2232 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2235 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->TopBottom
== 3))
2237 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2239 for (i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++)
2241 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2244 swap
= cfi_info
->erase_region_info
[i
];
2245 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2246 cfi_info
->erase_region_info
[j
] = swap
;
2251 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, void *param
)
2253 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2254 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2255 struct cfi_unlock_addresses
*unlock_addresses
= param
;
2257 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2258 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2262 static int cfi_query_string(struct flash_bank
*bank
, int address
)
2264 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2267 if ((retval
= cfi_send_command(bank
, 0x98, flash_address(bank
, 0, address
))) != ERROR_OK
)
2272 retval
= cfi_query_u8(bank
, 0, 0x10, &cfi_info
->qry
[0]);
2273 if (retval
!= ERROR_OK
)
2275 retval
= cfi_query_u8(bank
, 0, 0x11, &cfi_info
->qry
[1]);
2276 if (retval
!= ERROR_OK
)
2278 retval
= cfi_query_u8(bank
, 0, 0x12, &cfi_info
->qry
[2]);
2279 if (retval
!= ERROR_OK
)
2282 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2284 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y'))
2286 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2290 LOG_ERROR("Could not probe bank: no QRY");
2291 return ERROR_FLASH_BANK_INVALID
;
2297 static int cfi_probe(struct flash_bank
*bank
)
2299 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2300 struct target
*target
= bank
->target
;
2301 int num_sectors
= 0;
2304 uint32_t unlock1
= 0x555;
2305 uint32_t unlock2
= 0x2aa;
2307 uint8_t value_buf0
[CFI_MAX_BUS_WIDTH
], value_buf1
[CFI_MAX_BUS_WIDTH
];
2309 if (bank
->target
->state
!= TARGET_HALTED
)
2311 LOG_ERROR("Target not halted");
2312 return ERROR_TARGET_NOT_HALTED
;
2315 cfi_info
->probed
= 0;
2318 free(bank
->sectors
);
2319 bank
->sectors
= NULL
;
2321 if(cfi_info
->erase_region_info
)
2323 free(cfi_info
->erase_region_info
);
2324 cfi_info
->erase_region_info
= NULL
;
2327 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2328 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2330 if (cfi_info
->jedec_probe
)
2336 /* switch to read identifier codes mode ("AUTOSELECT") */
2337 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2341 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, unlock2
))) != ERROR_OK
)
2345 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, unlock1
))) != ERROR_OK
)
2350 if ((retval
= target_read_memory(target
, flash_address(bank
, 0, 0x00), bank
->bus_width
, 1, value_buf0
)) != ERROR_OK
)
2354 if ((retval
= target_read_memory(target
, flash_address(bank
, 0, 0x01), bank
->bus_width
, 1, value_buf1
)) != ERROR_OK
)
2358 switch (bank
->chip_width
) {
2360 cfi_info
->manufacturer
= *value_buf0
;
2361 cfi_info
->device_id
= *value_buf1
;
2364 cfi_info
->manufacturer
= target_buffer_get_u16(target
, value_buf0
);
2365 cfi_info
->device_id
= target_buffer_get_u16(target
, value_buf1
);
2368 cfi_info
->manufacturer
= target_buffer_get_u32(target
, value_buf0
);
2369 cfi_info
->device_id
= target_buffer_get_u32(target
, value_buf1
);
2372 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank
->chip_width
);
2373 return ERROR_FLASH_OPERATION_FAILED
;
2376 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info
->manufacturer
, cfi_info
->device_id
);
2377 /* switch back to read array mode */
2378 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2383 /* check device/manufacturer ID for known non-CFI flashes. */
2384 cfi_fixup_non_cfi(bank
);
2386 /* query only if this is a CFI compatible flash,
2387 * otherwise the relevant info has already been filled in
2389 if (cfi_info
->not_cfi
== 0)
2391 /* enter CFI query mode
2392 * according to JEDEC Standard No. 68.01,
2393 * a single bus sequence with address = 0x55, data = 0x98 should put
2394 * the device into CFI query mode.
2396 * SST flashes clearly violate this, and we will consider them incompatbile for now
2399 retval
= cfi_query_string(bank
, 0x55);
2400 if (retval
!= ERROR_OK
)
2403 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2404 * be harmless enough:
2406 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2408 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2409 retval
= cfi_query_string(bank
, 0x555);
2411 if (retval
!= ERROR_OK
)
2414 retval
= cfi_query_u16(bank
, 0, 0x13, &cfi_info
->pri_id
);
2415 if (retval
!= ERROR_OK
)
2417 retval
= cfi_query_u16(bank
, 0, 0x15, &cfi_info
->pri_addr
);
2418 if (retval
!= ERROR_OK
)
2420 retval
= cfi_query_u16(bank
, 0, 0x17, &cfi_info
->alt_id
);
2421 if (retval
!= ERROR_OK
)
2423 retval
= cfi_query_u16(bank
, 0, 0x19, &cfi_info
->alt_addr
);
2424 if (retval
!= ERROR_OK
)
2427 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2429 retval
= cfi_query_u8(bank
, 0, 0x1b, &cfi_info
->vcc_min
);
2430 if (retval
!= ERROR_OK
)
2432 retval
= cfi_query_u8(bank
, 0, 0x1c, &cfi_info
->vcc_max
);
2433 if (retval
!= ERROR_OK
)
2435 retval
= cfi_query_u8(bank
, 0, 0x1d, &cfi_info
->vpp_min
);
2436 if (retval
!= ERROR_OK
)
2438 retval
= cfi_query_u8(bank
, 0, 0x1e, &cfi_info
->vpp_max
);
2439 if (retval
!= ERROR_OK
)
2441 retval
= cfi_query_u8(bank
, 0, 0x1f, &cfi_info
->word_write_timeout_typ
);
2442 if (retval
!= ERROR_OK
)
2444 retval
= cfi_query_u8(bank
, 0, 0x20, &cfi_info
->buf_write_timeout_typ
);
2445 if (retval
!= ERROR_OK
)
2447 retval
= cfi_query_u8(bank
, 0, 0x21, &cfi_info
->block_erase_timeout_typ
);
2448 if (retval
!= ERROR_OK
)
2450 retval
= cfi_query_u8(bank
, 0, 0x22, &cfi_info
->chip_erase_timeout_typ
);
2451 if (retval
!= ERROR_OK
)
2453 retval
= cfi_query_u8(bank
, 0, 0x23, &cfi_info
->word_write_timeout_max
);
2454 if (retval
!= ERROR_OK
)
2456 retval
= cfi_query_u8(bank
, 0, 0x24, &cfi_info
->buf_write_timeout_max
);
2457 if (retval
!= ERROR_OK
)
2459 retval
= cfi_query_u8(bank
, 0, 0x25, &cfi_info
->block_erase_timeout_max
);
2460 if (retval
!= ERROR_OK
)
2462 retval
= cfi_query_u8(bank
, 0, 0x26, &cfi_info
->chip_erase_timeout_max
);
2463 if (retval
!= ERROR_OK
)
2466 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2467 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2468 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2469 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2470 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2471 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2472 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2473 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2474 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2475 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2476 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2479 retval
= cfi_query_u8(bank
, 0, 0x27, &data
);
2480 if (retval
!= ERROR_OK
)
2482 cfi_info
->dev_size
= 1 << data
;
2484 retval
= cfi_query_u16(bank
, 0, 0x28, &cfi_info
->interface_desc
);
2485 if (retval
!= ERROR_OK
)
2487 retval
= cfi_query_u16(bank
, 0, 0x2a, &cfi_info
->max_buf_write_size
);
2488 if (retval
!= ERROR_OK
)
2490 retval
= cfi_query_u8(bank
, 0, 0x2c, &cfi_info
->num_erase_regions
);
2491 if (retval
!= ERROR_OK
)
2494 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x", cfi_info
->dev_size
, cfi_info
->interface_desc
, (1 << cfi_info
->max_buf_write_size
));
2496 if (cfi_info
->num_erase_regions
)
2498 cfi_info
->erase_region_info
= malloc(sizeof(*cfi_info
->erase_region_info
)
2499 * cfi_info
->num_erase_regions
);
2500 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2502 retval
= cfi_query_u32(bank
, 0, 0x2d + (4 * i
), &cfi_info
->erase_region_info
[i
]);
2503 if (retval
!= ERROR_OK
)
2505 LOG_DEBUG("erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"",
2507 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2508 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2513 cfi_info
->erase_region_info
= NULL
;
2516 /* We need to read the primary algorithm extended query table before calculating
2517 * the sector layout to be able to apply fixups
2519 switch (cfi_info
->pri_id
)
2521 /* Intel command set (standard and extended) */
2524 cfi_read_intel_pri_ext(bank
);
2526 /* AMD/Spansion, Atmel, ... command set */
2528 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /* default for all CFI flashs */
2529 cfi_read_0002_pri_ext(bank
);
2532 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2536 /* return to read array mode
2537 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2539 if ((retval
= cfi_reset(bank
)) != ERROR_OK
)
2543 } /* end CFI case */
2545 /* apply fixups depending on the primary command set */
2546 switch (cfi_info
->pri_id
)
2548 /* Intel command set (standard and extended) */
2551 cfi_fixup(bank
, cfi_0001_fixups
);
2553 /* AMD/Spansion, Atmel, ... command set */
2555 cfi_fixup(bank
, cfi_0002_fixups
);
2558 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2562 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
)
2564 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
" size flash was found", bank
->size
, cfi_info
->dev_size
);
2567 if (cfi_info
->num_erase_regions
== 0)
2569 /* a device might have only one erase block, spanning the whole device */
2570 bank
->num_sectors
= 1;
2571 bank
->sectors
= malloc(sizeof(struct flash_sector
));
2573 bank
->sectors
[sector
].offset
= 0x0;
2574 bank
->sectors
[sector
].size
= bank
->size
;
2575 bank
->sectors
[sector
].is_erased
= -1;
2576 bank
->sectors
[sector
].is_protected
= -1;
2580 uint32_t offset
= 0;
2582 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2584 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2587 bank
->num_sectors
= num_sectors
;
2588 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
2590 for (i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2593 for (j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++)
2595 bank
->sectors
[sector
].offset
= offset
;
2596 bank
->sectors
[sector
].size
= ((cfi_info
->erase_region_info
[i
] >> 16) * 256) * bank
->bus_width
/ bank
->chip_width
;
2597 offset
+= bank
->sectors
[sector
].size
;
2598 bank
->sectors
[sector
].is_erased
= -1;
2599 bank
->sectors
[sector
].is_protected
= -1;
2603 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
))
2605 LOG_WARNING("CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"", \
2606 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
), offset
);
2610 cfi_info
->probed
= 1;
2615 static int cfi_auto_probe(struct flash_bank
*bank
)
2617 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2618 if (cfi_info
->probed
)
2620 return cfi_probe(bank
);
2623 static int cfi_intel_protect_check(struct flash_bank
*bank
)
2626 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2627 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2630 /* check if block lock bits are supported on this device */
2631 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2632 return ERROR_FLASH_OPERATION_FAILED
;
2634 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, 0x55))) != ERROR_OK
)
2639 for (i
= 0; i
< bank
->num_sectors
; i
++)
2641 uint8_t block_status
;
2642 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2643 if (retval
!= ERROR_OK
)
2646 if (block_status
& 1)
2647 bank
->sectors
[i
].is_protected
= 1;
2649 bank
->sectors
[i
].is_protected
= 0;
2652 return cfi_send_command(bank
, 0xff, flash_address(bank
, 0, 0x0));
2655 static int cfi_spansion_protect_check(struct flash_bank
*bank
)
2658 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2659 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2662 if ((retval
= cfi_send_command(bank
, 0xaa, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2667 if ((retval
= cfi_send_command(bank
, 0x55, flash_address(bank
, 0, pri_ext
->_unlock2
))) != ERROR_OK
)
2672 if ((retval
= cfi_send_command(bank
, 0x90, flash_address(bank
, 0, pri_ext
->_unlock1
))) != ERROR_OK
)
2677 for (i
= 0; i
< bank
->num_sectors
; i
++)
2679 uint8_t block_status
;
2680 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2681 if (retval
!= ERROR_OK
)
2684 if (block_status
& 1)
2685 bank
->sectors
[i
].is_protected
= 1;
2687 bank
->sectors
[i
].is_protected
= 0;
2690 return cfi_send_command(bank
, 0xf0, flash_address(bank
, 0, 0x0));
2693 static int cfi_protect_check(struct flash_bank
*bank
)
2695 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2697 if (bank
->target
->state
!= TARGET_HALTED
)
2699 LOG_ERROR("Target not halted");
2700 return ERROR_TARGET_NOT_HALTED
;
2703 if (cfi_info
->qry
[0] != 'Q')
2704 return ERROR_FLASH_BANK_NOT_PROBED
;
2706 switch (cfi_info
->pri_id
)
2710 return cfi_intel_protect_check(bank
);
2713 return cfi_spansion_protect_check(bank
);
2716 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2723 static int get_cfi_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
2726 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2728 if (cfi_info
->qry
[0] == 0xff)
2730 printed
= snprintf(buf
, buf_size
, "\ncfi flash bank not probed yet\n");
2734 if (cfi_info
->not_cfi
== 0)
2735 printed
= snprintf(buf
, buf_size
, "\ncfi information:\n");
2737 printed
= snprintf(buf
, buf_size
, "\nnon-cfi flash:\n");
2739 buf_size
-= printed
;
2741 printed
= snprintf(buf
, buf_size
, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2742 cfi_info
->manufacturer
, cfi_info
->device_id
);
2744 buf_size
-= printed
;
2746 if (cfi_info
->not_cfi
== 0)
2748 printed
= snprintf(buf
, buf_size
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2750 buf_size
-= printed
;
2752 printed
= snprintf(buf
, buf_size
, "Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x\n",
2753 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2754 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2755 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2756 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2758 buf_size
-= printed
;
2760 printed
= snprintf(buf
, buf_size
, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2761 1 << cfi_info
->word_write_timeout_typ
,
2762 1 << cfi_info
->buf_write_timeout_typ
,
2763 1 << cfi_info
->block_erase_timeout_typ
,
2764 1 << cfi_info
->chip_erase_timeout_typ
);
2766 buf_size
-= printed
;
2768 printed
= snprintf(buf
, buf_size
, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2769 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2770 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2771 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2772 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2774 buf_size
-= printed
;
2776 printed
= snprintf(buf
, buf_size
, "size: 0x%" PRIx32
", interface desc: %i, max buffer write size: %x\n",
2778 cfi_info
->interface_desc
,
2779 1 << cfi_info
->max_buf_write_size
);
2781 buf_size
-= printed
;
2783 switch (cfi_info
->pri_id
)
2787 cfi_intel_info(bank
, buf
, buf_size
);
2790 cfi_spansion_info(bank
, buf
, buf_size
);
2793 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2801 struct flash_driver cfi_flash
= {
2803 .flash_bank_command
= cfi_flash_bank_command
,
2805 .protect
= cfi_protect
,
2809 .auto_probe
= cfi_auto_probe
,
2810 /* FIXME: access flash at bus_width size */
2811 .erase_check
= default_flash_blank_check
,
2812 .protect_check
= cfi_protect_check
,
2813 .info
= get_cfi_info
,
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