1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
21 ***************************************************************************/
30 #include <target/arm.h>
31 #include <target/arm7_9_common.h>
32 #include <target/armv7m.h>
33 #include <target/mips32.h>
34 #include <helper/binarybuffer.h>
35 #include <target/algorithm.h>
37 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
38 #define CFI_MAX_INTEL_CODESIZE 256
40 /* some id-types with specific handling */
41 #define AT49BV6416 0x00d6
42 #define AT49BV6416T 0x00d2
44 static const struct cfi_unlock_addresses cfi_unlock_addresses
[] = {
45 [CFI_UNLOCK_555_2AA
] = { .unlock1
= 0x555, .unlock2
= 0x2aa },
46 [CFI_UNLOCK_5555_2AAA
] = { .unlock1
= 0x5555, .unlock2
= 0x2aaa },
49 static const int cfi_status_poll_mask_dq6_dq7
= CFI_STATUS_POLL_MASK_DQ6_DQ7
;
51 /* CFI fixups forward declarations */
52 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, const void *param
);
53 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, const void *param
);
54 static void cfi_fixup_reversed_erase_regions(struct flash_bank
*bank
, const void *param
);
55 static void cfi_fixup_0002_write_buffer(struct flash_bank
*bank
, const void *param
);
56 static void cfi_fixup_0002_polling_bits(struct flash_bank
*bank
, const void *param
);
58 /* fixup after reading cmdset 0002 primary query table */
59 static const struct cfi_fixup cfi_0002_fixups
[] = {
60 {CFI_MFR_SST
, 0x00D4, cfi_fixup_0002_unlock_addresses
,
61 &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
62 {CFI_MFR_SST
, 0x00D5, cfi_fixup_0002_unlock_addresses
,
63 &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
64 {CFI_MFR_SST
, 0x00D6, cfi_fixup_0002_unlock_addresses
,
65 &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
66 {CFI_MFR_SST
, 0x00D7, cfi_fixup_0002_unlock_addresses
,
67 &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
68 {CFI_MFR_SST
, 0x2780, cfi_fixup_0002_unlock_addresses
,
69 &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
70 {CFI_MFR_SST
, 0x274b, cfi_fixup_0002_unlock_addresses
,
71 &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
72 {CFI_MFR_SST
, 0x235f, cfi_fixup_0002_polling_bits
, /* 39VF3201C */
73 &cfi_status_poll_mask_dq6_dq7
},
74 {CFI_MFR_SST
, 0x236d, cfi_fixup_0002_unlock_addresses
,
75 &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
76 {CFI_MFR_ATMEL
, 0x00C8, cfi_fixup_reversed_erase_regions
, NULL
},
77 {CFI_MFR_ST
, 0x22C4, cfi_fixup_reversed_erase_regions
, NULL
}, /* M29W160ET */
78 {CFI_MFR_FUJITSU
, 0x22ea, cfi_fixup_0002_unlock_addresses
,
79 &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
80 {CFI_MFR_FUJITSU
, 0x226b, cfi_fixup_0002_unlock_addresses
,
81 &cfi_unlock_addresses
[CFI_UNLOCK_5555_2AAA
]},
82 {CFI_MFR_AMIC
, 0xb31a, cfi_fixup_0002_unlock_addresses
,
83 &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
84 {CFI_MFR_MX
, 0x225b, cfi_fixup_0002_unlock_addresses
,
85 &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
86 {CFI_MFR_EON
, 0x225b, cfi_fixup_0002_unlock_addresses
,
87 &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
88 {CFI_MFR_AMD
, 0x225b, cfi_fixup_0002_unlock_addresses
,
89 &cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
]},
90 {CFI_MFR_ANY
, CFI_ID_ANY
, cfi_fixup_0002_erase_regions
, NULL
},
91 {CFI_MFR_ST
, 0x227E, cfi_fixup_0002_write_buffer
, NULL
},/* M29W128G */
95 /* fixup after reading cmdset 0001 primary query table */
96 static const struct cfi_fixup cfi_0001_fixups
[] = {
100 static void cfi_fixup(struct flash_bank
*bank
, const struct cfi_fixup
*fixups
)
102 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
104 for (const struct cfi_fixup
*f
= fixups
; f
->fixup
; f
++) {
105 if (((f
->mfr
== CFI_MFR_ANY
) || (f
->mfr
== cfi_info
->manufacturer
)) &&
106 ((f
->id
== CFI_ID_ANY
) || (f
->id
== cfi_info
->device_id
)))
107 f
->fixup(bank
, f
->param
);
111 uint32_t cfi_flash_address(struct flash_bank
*bank
, int sector
, uint32_t offset
)
113 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
115 if (cfi_info
->x16_as_x8
)
118 /* while the sector list isn't built, only accesses to sector 0 work */
120 return bank
->base
+ offset
* bank
->bus_width
;
122 if (!bank
->sectors
) {
123 LOG_ERROR("BUG: sector list not yet built");
126 return bank
->base
+ bank
->sectors
[sector
].offset
+ offset
* bank
->bus_width
;
130 static int cfi_target_write_memory(struct flash_bank
*bank
, target_addr_t addr
,
131 uint32_t count
, const uint8_t *buffer
)
133 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
134 if (cfi_info
->write_mem
) {
135 return cfi_info
->write_mem(bank
, addr
, count
, buffer
);
137 return target_write_memory(bank
->target
, addr
, bank
->bus_width
,
142 int cfi_target_read_memory(struct flash_bank
*bank
, target_addr_t addr
,
143 uint32_t count
, uint8_t *buffer
)
145 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
146 if (cfi_info
->read_mem
) {
147 return cfi_info
->read_mem(bank
, addr
, count
, buffer
);
149 return target_read_memory(bank
->target
, addr
, bank
->bus_width
,
154 static void cfi_command(struct flash_bank
*bank
, uint8_t cmd
, uint8_t *cmd_buf
)
156 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
158 /* clear whole buffer, to ensure bits that exceed the bus_width
161 for (size_t i
= 0; i
< CFI_MAX_BUS_WIDTH
; i
++)
164 if (cfi_info
->endianness
== TARGET_LITTLE_ENDIAN
) {
165 for (unsigned int i
= bank
->bus_width
; i
> 0; i
--)
166 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
168 for (unsigned int i
= 1; i
<= bank
->bus_width
; i
++)
169 *cmd_buf
++ = (i
& (bank
->chip_width
- 1)) ? 0x0 : cmd
;
173 int cfi_send_command(struct flash_bank
*bank
, uint8_t cmd
, uint32_t address
)
175 uint8_t command
[CFI_MAX_BUS_WIDTH
];
177 cfi_command(bank
, cmd
, command
);
178 return cfi_target_write_memory(bank
, address
, 1, command
);
181 /* read unsigned 8-bit value from the bank
182 * flash banks are expected to be made of similar chips
183 * the query result should be the same for all
185 static int cfi_query_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
187 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
188 uint8_t data
[CFI_MAX_BUS_WIDTH
];
191 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, sector
, offset
),
193 if (retval
!= ERROR_OK
)
196 if (cfi_info
->endianness
== TARGET_LITTLE_ENDIAN
)
199 *val
= data
[bank
->bus_width
- 1];
204 /* read unsigned 8-bit value from the bank
205 * in case of a bank made of multiple chips,
206 * the individual values are ORed
208 static int cfi_get_u8(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint8_t *val
)
210 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
211 uint8_t data
[CFI_MAX_BUS_WIDTH
];
214 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, sector
, offset
),
216 if (retval
!= ERROR_OK
)
219 if (cfi_info
->endianness
== TARGET_LITTLE_ENDIAN
) {
220 for (unsigned int i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
226 for (unsigned int i
= 0; i
< bank
->bus_width
/ bank
->chip_width
; i
++)
227 value
|= data
[bank
->bus_width
- 1 - i
];
234 static int cfi_query_u16(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint16_t *val
)
236 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
237 uint8_t data
[CFI_MAX_BUS_WIDTH
* 2];
240 if (cfi_info
->x16_as_x8
) {
241 for (uint8_t i
= 0; i
< 2; i
++) {
242 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, sector
, offset
+ i
),
243 1, &data
[i
* bank
->bus_width
]);
244 if (retval
!= ERROR_OK
)
248 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, sector
, offset
),
250 if (retval
!= ERROR_OK
)
254 if (cfi_info
->endianness
== TARGET_LITTLE_ENDIAN
)
255 *val
= data
[0] | data
[bank
->bus_width
] << 8;
257 *val
= data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8;
262 static int cfi_query_u32(struct flash_bank
*bank
, int sector
, uint32_t offset
, uint32_t *val
)
264 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
265 uint8_t data
[CFI_MAX_BUS_WIDTH
* 4];
268 if (cfi_info
->x16_as_x8
) {
269 for (uint8_t i
= 0; i
< 4; i
++) {
270 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, sector
, offset
+ i
),
271 1, &data
[i
* bank
->bus_width
]);
272 if (retval
!= ERROR_OK
)
276 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, sector
, offset
),
278 if (retval
!= ERROR_OK
)
282 if (cfi_info
->endianness
== TARGET_LITTLE_ENDIAN
)
283 *val
= data
[0] | data
[bank
->bus_width
] << 8 |
284 data
[bank
->bus_width
* 2] << 16 | data
[bank
->bus_width
* 3] << 24;
286 *val
= data
[bank
->bus_width
- 1] | data
[(2 * bank
->bus_width
) - 1] << 8 |
287 data
[(3 * bank
->bus_width
) - 1] << 16 |
288 data
[(4 * bank
->bus_width
) - 1] << 24;
293 int cfi_reset(struct flash_bank
*bank
)
295 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
296 int retval
= ERROR_OK
;
298 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
299 if (retval
!= ERROR_OK
)
302 retval
= cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
303 if (retval
!= ERROR_OK
)
306 if (cfi_info
->manufacturer
== 0x20 &&
307 (cfi_info
->device_id
== 0x227E || cfi_info
->device_id
== 0x7E)) {
308 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
309 * so we send an extra 0xF0 reset to fix the bug */
310 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x00));
311 if (retval
!= ERROR_OK
)
318 static void cfi_intel_clear_status_register(struct flash_bank
*bank
)
320 cfi_send_command(bank
, 0x50, cfi_flash_address(bank
, 0, 0x0));
323 static int cfi_intel_wait_status_busy(struct flash_bank
*bank
, int timeout
, uint8_t *val
)
327 int retval
= ERROR_OK
;
331 LOG_ERROR("timeout while waiting for WSM to become ready");
335 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
336 if (retval
!= ERROR_OK
)
345 /* mask out bit 0 (reserved) */
346 status
= status
& 0xfe;
348 LOG_DEBUG("status: 0x%x", status
);
350 if (status
!= 0x80) {
351 LOG_ERROR("status register: 0x%x", status
);
353 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
355 LOG_ERROR("Program suspended");
357 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
359 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
361 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
363 LOG_ERROR("Block Erase Suspended");
365 cfi_intel_clear_status_register(bank
);
374 int cfi_spansion_wait_status_busy(struct flash_bank
*bank
, int timeout
)
376 uint8_t status
, oldstatus
;
377 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
380 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
381 if (retval
!= ERROR_OK
)
385 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
387 if (retval
!= ERROR_OK
)
390 if ((status
^ oldstatus
) & 0x40) {
391 if (status
& cfi_info
->status_poll_mask
& 0x20) {
392 retval
= cfi_get_u8(bank
, 0, 0x0, &oldstatus
);
393 if (retval
!= ERROR_OK
)
395 retval
= cfi_get_u8(bank
, 0, 0x0, &status
);
396 if (retval
!= ERROR_OK
)
398 if ((status
^ oldstatus
) & 0x40) {
399 LOG_ERROR("dq5 timeout, status: 0x%x", status
);
400 return ERROR_FLASH_OPERATION_FAILED
;
402 LOG_DEBUG("status: 0x%x", status
);
406 } else {/* no toggle: finished, OK */
407 LOG_DEBUG("status: 0x%x", status
);
413 } while (timeout
-- > 0);
415 LOG_ERROR("timeout, status: 0x%x", status
);
417 return ERROR_FLASH_BUSY
;
420 static int cfi_read_intel_pri_ext(struct flash_bank
*bank
)
423 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
424 struct cfi_intel_pri_ext
*pri_ext
;
426 free(cfi_info
->pri_ext
);
428 pri_ext
= malloc(sizeof(struct cfi_intel_pri_ext
));
430 LOG_ERROR("Out of memory");
433 cfi_info
->pri_ext
= pri_ext
;
435 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
436 if (retval
!= ERROR_OK
)
438 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
439 if (retval
!= ERROR_OK
)
441 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
442 if (retval
!= ERROR_OK
)
445 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I')) {
446 retval
= cfi_reset(bank
);
447 if (retval
!= ERROR_OK
)
449 LOG_ERROR("Could not read bank flash bank information");
450 return ERROR_FLASH_BANK_INVALID
;
453 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
454 if (retval
!= ERROR_OK
)
456 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
457 if (retval
!= ERROR_OK
)
460 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1],
461 pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
463 retval
= cfi_query_u32(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->feature_support
);
464 if (retval
!= ERROR_OK
)
466 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->suspend_cmd_support
);
467 if (retval
!= ERROR_OK
)
469 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xa, &pri_ext
->blk_status_reg_mask
);
470 if (retval
!= ERROR_OK
)
473 LOG_DEBUG("feature_support: 0x%" PRIx32
", suspend_cmd_support: "
474 "0x%x, blk_status_reg_mask: 0x%x",
475 pri_ext
->feature_support
,
476 pri_ext
->suspend_cmd_support
,
477 pri_ext
->blk_status_reg_mask
);
479 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xc, &pri_ext
->vcc_optimal
);
480 if (retval
!= ERROR_OK
)
482 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xd, &pri_ext
->vpp_optimal
);
483 if (retval
!= ERROR_OK
)
486 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
487 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
488 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
490 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0xe, &pri_ext
->num_protection_fields
);
491 if (retval
!= ERROR_OK
)
493 if (pri_ext
->num_protection_fields
!= 1) {
494 LOG_WARNING("expected one protection register field, but found %i",
495 pri_ext
->num_protection_fields
);
498 retval
= cfi_query_u16(bank
, 0, cfi_info
->pri_addr
+ 0xf, &pri_ext
->prot_reg_addr
);
499 if (retval
!= ERROR_OK
)
501 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x11, &pri_ext
->fact_prot_reg_size
);
502 if (retval
!= ERROR_OK
)
504 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0x12, &pri_ext
->user_prot_reg_size
);
505 if (retval
!= ERROR_OK
)
508 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
509 "factory pre-programmed: %i, user programmable: %i",
510 pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
,
511 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
516 static int cfi_read_spansion_pri_ext(struct flash_bank
*bank
)
519 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
520 struct cfi_spansion_pri_ext
*pri_ext
;
522 free(cfi_info
->pri_ext
);
524 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
526 LOG_ERROR("Out of memory");
529 cfi_info
->pri_ext
= pri_ext
;
531 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &pri_ext
->pri
[0]);
532 if (retval
!= ERROR_OK
)
534 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &pri_ext
->pri
[1]);
535 if (retval
!= ERROR_OK
)
537 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &pri_ext
->pri
[2]);
538 if (retval
!= ERROR_OK
)
541 /* default values for implementation specific workarounds */
542 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
543 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
544 pri_ext
->_reversed_geometry
= 0;
546 if ((pri_ext
->pri
[0] != 'P') || (pri_ext
->pri
[1] != 'R') || (pri_ext
->pri
[2] != 'I')) {
547 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
548 if (retval
!= ERROR_OK
)
550 LOG_ERROR("Could not read spansion bank information");
551 return ERROR_FLASH_BANK_INVALID
;
554 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &pri_ext
->major_version
);
555 if (retval
!= ERROR_OK
)
557 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &pri_ext
->minor_version
);
558 if (retval
!= ERROR_OK
)
561 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext
->pri
[0], pri_ext
->pri
[1],
562 pri_ext
->pri
[2], pri_ext
->major_version
, pri_ext
->minor_version
);
564 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &pri_ext
->silicon_revision
);
565 if (retval
!= ERROR_OK
)
567 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &pri_ext
->erase_suspend
);
568 if (retval
!= ERROR_OK
)
570 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &pri_ext
->blk_prot
);
571 if (retval
!= ERROR_OK
)
573 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &pri_ext
->tmp_blk_unprotected
);
574 if (retval
!= ERROR_OK
)
576 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 9, &pri_ext
->blk_prot_unprot
);
577 if (retval
!= ERROR_OK
)
579 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 10, &pri_ext
->simultaneous_ops
);
580 if (retval
!= ERROR_OK
)
582 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 11, &pri_ext
->burst_mode
);
583 if (retval
!= ERROR_OK
)
585 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 12, &pri_ext
->page_mode
);
586 if (retval
!= ERROR_OK
)
588 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 13, &pri_ext
->vpp_min
);
589 if (retval
!= ERROR_OK
)
591 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 14, &pri_ext
->vpp_max
);
592 if (retval
!= ERROR_OK
)
594 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 15, &pri_ext
->top_bottom
);
595 if (retval
!= ERROR_OK
)
598 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
599 pri_ext
->silicon_revision
, pri_ext
->erase_suspend
, pri_ext
->blk_prot
);
601 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
602 "Simultaneous Ops: 0x%x", pri_ext
->tmp_blk_unprotected
,
603 pri_ext
->blk_prot_unprot
, pri_ext
->simultaneous_ops
);
605 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext
->burst_mode
, pri_ext
->page_mode
);
608 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
609 (pri_ext
->vpp_min
& 0xf0) >> 4, pri_ext
->vpp_min
& 0x0f,
610 (pri_ext
->vpp_max
& 0xf0) >> 4, pri_ext
->vpp_max
& 0x0f);
612 LOG_DEBUG("WP# protection 0x%x", pri_ext
->top_bottom
);
617 static int cfi_read_atmel_pri_ext(struct flash_bank
*bank
)
620 struct cfi_atmel_pri_ext atmel_pri_ext
;
621 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
622 struct cfi_spansion_pri_ext
*pri_ext
;
624 free(cfi_info
->pri_ext
);
626 pri_ext
= malloc(sizeof(struct cfi_spansion_pri_ext
));
628 LOG_ERROR("Out of memory");
632 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
633 * but a different primary extended query table.
634 * We read the atmel table, and prepare a valid AMD/Spansion query table.
637 memset(pri_ext
, 0, sizeof(struct cfi_spansion_pri_ext
));
639 cfi_info
->pri_ext
= pri_ext
;
641 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 0, &atmel_pri_ext
.pri
[0]);
642 if (retval
!= ERROR_OK
)
644 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 1, &atmel_pri_ext
.pri
[1]);
645 if (retval
!= ERROR_OK
)
647 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 2, &atmel_pri_ext
.pri
[2]);
648 if (retval
!= ERROR_OK
)
651 if ((atmel_pri_ext
.pri
[0] != 'P') || (atmel_pri_ext
.pri
[1] != 'R')
652 || (atmel_pri_ext
.pri
[2] != 'I')) {
653 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
654 if (retval
!= ERROR_OK
)
656 LOG_ERROR("Could not read atmel bank information");
657 return ERROR_FLASH_BANK_INVALID
;
660 pri_ext
->pri
[0] = atmel_pri_ext
.pri
[0];
661 pri_ext
->pri
[1] = atmel_pri_ext
.pri
[1];
662 pri_ext
->pri
[2] = atmel_pri_ext
.pri
[2];
664 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 3, &atmel_pri_ext
.major_version
);
665 if (retval
!= ERROR_OK
)
667 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 4, &atmel_pri_ext
.minor_version
);
668 if (retval
!= ERROR_OK
)
671 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext
.pri
[0],
672 atmel_pri_ext
.pri
[1], atmel_pri_ext
.pri
[2],
673 atmel_pri_ext
.major_version
, atmel_pri_ext
.minor_version
);
675 pri_ext
->major_version
= atmel_pri_ext
.major_version
;
676 pri_ext
->minor_version
= atmel_pri_ext
.minor_version
;
678 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 5, &atmel_pri_ext
.features
);
679 if (retval
!= ERROR_OK
)
681 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 6, &atmel_pri_ext
.bottom_boot
);
682 if (retval
!= ERROR_OK
)
684 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 7, &atmel_pri_ext
.burst_mode
);
685 if (retval
!= ERROR_OK
)
687 retval
= cfi_query_u8(bank
, 0, cfi_info
->pri_addr
+ 8, &atmel_pri_ext
.page_mode
);
688 if (retval
!= ERROR_OK
)
692 "features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
693 atmel_pri_ext
.features
,
694 atmel_pri_ext
.bottom_boot
,
695 atmel_pri_ext
.burst_mode
,
696 atmel_pri_ext
.page_mode
);
698 if (atmel_pri_ext
.features
& 0x02)
699 pri_ext
->erase_suspend
= 2;
701 /* some chips got it backwards... */
702 if (cfi_info
->device_id
== AT49BV6416
||
703 cfi_info
->device_id
== AT49BV6416T
) {
704 if (atmel_pri_ext
.bottom_boot
)
705 pri_ext
->top_bottom
= 3;
707 pri_ext
->top_bottom
= 2;
709 if (atmel_pri_ext
.bottom_boot
)
710 pri_ext
->top_bottom
= 2;
712 pri_ext
->top_bottom
= 3;
715 pri_ext
->_unlock1
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock1
;
716 pri_ext
->_unlock2
= cfi_unlock_addresses
[CFI_UNLOCK_555_2AA
].unlock2
;
721 static int cfi_read_0002_pri_ext(struct flash_bank
*bank
)
723 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
725 if (cfi_info
->manufacturer
== CFI_MFR_ATMEL
)
726 return cfi_read_atmel_pri_ext(bank
);
728 return cfi_read_spansion_pri_ext(bank
);
731 static int cfi_spansion_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
733 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
734 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
736 command_print_sameline(cmd
, "\nSpansion primary algorithm extend information:\n");
738 command_print_sameline(cmd
, "pri: '%c%c%c', version: %c.%c\n",
739 pri_ext
->pri
[0], pri_ext
->pri
[1], pri_ext
->pri
[2],
740 pri_ext
->major_version
, pri_ext
->minor_version
);
742 command_print_sameline(cmd
, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
743 (pri_ext
->silicon_revision
) >> 2,
744 (pri_ext
->silicon_revision
) & 0x03);
746 command_print_sameline(cmd
, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
747 pri_ext
->erase_suspend
,
750 command_print_sameline(cmd
, "VppMin: %u.%x, VppMax: %u.%x\n",
751 (pri_ext
->vpp_min
& 0xf0) >> 4, pri_ext
->vpp_min
& 0x0f,
752 (pri_ext
->vpp_max
& 0xf0) >> 4, pri_ext
->vpp_max
& 0x0f);
757 static int cfi_intel_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
759 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
760 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
762 command_print_sameline(cmd
, "\nintel primary algorithm extend information:\n");
764 command_print_sameline(cmd
, "pri: '%c%c%c', version: %c.%c\n",
768 pri_ext
->major_version
,
769 pri_ext
->minor_version
);
771 command_print_sameline(cmd
, "feature_support: 0x%" PRIx32
", "
772 "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
773 pri_ext
->feature_support
,
774 pri_ext
->suspend_cmd_support
,
775 pri_ext
->blk_status_reg_mask
);
777 command_print_sameline(cmd
, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
778 (pri_ext
->vcc_optimal
& 0xf0) >> 4, pri_ext
->vcc_optimal
& 0x0f,
779 (pri_ext
->vpp_optimal
& 0xf0) >> 4, pri_ext
->vpp_optimal
& 0x0f);
781 command_print_sameline(cmd
, "protection_fields: %i, prot_reg_addr: 0x%x, "
782 "factory pre-programmed: %i, user programmable: %i\n",
783 pri_ext
->num_protection_fields
, pri_ext
->prot_reg_addr
,
784 1 << pri_ext
->fact_prot_reg_size
, 1 << pri_ext
->user_prot_reg_size
);
789 int cfi_flash_bank_cmd(struct flash_bank
*bank
, unsigned int argc
, const char **argv
)
791 struct cfi_flash_bank
*cfi_info
;
792 bool bus_swap
= false;
795 return ERROR_COMMAND_SYNTAX_ERROR
;
798 * - not exceed max value;
800 * - be equal to a power of 2.
801 * bus must be wide enough to hold one chip */
802 if ((bank
->chip_width
> CFI_MAX_CHIP_WIDTH
)
803 || (bank
->bus_width
> CFI_MAX_BUS_WIDTH
)
804 || (bank
->chip_width
== 0)
805 || (bank
->bus_width
== 0)
806 || (bank
->chip_width
& (bank
->chip_width
- 1))
807 || (bank
->bus_width
& (bank
->bus_width
- 1))
808 || (bank
->chip_width
> bank
->bus_width
)) {
809 LOG_ERROR("chip and bus width have to specified in bytes");
810 return ERROR_FLASH_BANK_INVALID
;
813 cfi_info
= calloc(1, sizeof(struct cfi_flash_bank
));
815 LOG_ERROR("No memory for flash bank info");
818 bank
->driver_priv
= cfi_info
;
820 for (unsigned i
= 6; i
< argc
; i
++) {
821 if (strcmp(argv
[i
], "x16_as_x8") == 0)
822 cfi_info
->x16_as_x8
= true;
823 else if (strcmp(argv
[i
], "data_swap") == 0)
824 cfi_info
->data_swap
= true;
825 else if (strcmp(argv
[i
], "bus_swap") == 0)
827 else if (strcmp(argv
[i
], "jedec_probe") == 0)
828 cfi_info
->jedec_probe
= true;
832 cfi_info
->endianness
=
833 bank
->target
->endianness
== TARGET_LITTLE_ENDIAN
?
834 TARGET_BIG_ENDIAN
: TARGET_LITTLE_ENDIAN
;
836 cfi_info
->endianness
= bank
->target
->endianness
;
838 /* bank wasn't probed yet */
839 cfi_info
->qry
[0] = 0xff;
844 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
846 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command
)
848 return cfi_flash_bank_cmd(bank
, CMD_ARGC
, CMD_ARGV
);
851 static int cfi_intel_erase(struct flash_bank
*bank
, unsigned int first
,
855 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
857 cfi_intel_clear_status_register(bank
);
859 for (unsigned int i
= first
; i
<= last
; i
++) {
860 retval
= cfi_send_command(bank
, 0x20, cfi_flash_address(bank
, i
, 0x0));
861 if (retval
!= ERROR_OK
)
864 retval
= cfi_send_command(bank
, 0xd0, cfi_flash_address(bank
, i
, 0x0));
865 if (retval
!= ERROR_OK
)
869 retval
= cfi_intel_wait_status_busy(bank
, cfi_info
->block_erase_timeout
, &status
);
870 if (retval
!= ERROR_OK
)
873 if (status
!= 0x80) {
874 retval
= cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
875 if (retval
!= ERROR_OK
)
878 LOG_ERROR("couldn't erase block %u of flash bank at base "
879 TARGET_ADDR_FMT
, i
, bank
->base
);
880 return ERROR_FLASH_OPERATION_FAILED
;
884 return cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
887 int cfi_spansion_unlock_seq(struct flash_bank
*bank
)
890 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
891 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
893 retval
= cfi_send_command(bank
, 0xaa, cfi_flash_address(bank
, 0, pri_ext
->_unlock1
));
894 if (retval
!= ERROR_OK
)
897 retval
= cfi_send_command(bank
, 0x55, cfi_flash_address(bank
, 0, pri_ext
->_unlock2
));
898 if (retval
!= ERROR_OK
)
904 static int cfi_spansion_erase(struct flash_bank
*bank
, unsigned int first
,
908 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
909 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
911 for (unsigned int i
= first
; i
<= last
; i
++) {
912 retval
= cfi_spansion_unlock_seq(bank
);
913 if (retval
!= ERROR_OK
)
916 retval
= cfi_send_command(bank
, 0x80, cfi_flash_address(bank
, 0, pri_ext
->_unlock1
));
917 if (retval
!= ERROR_OK
)
920 retval
= cfi_spansion_unlock_seq(bank
);
921 if (retval
!= ERROR_OK
)
924 retval
= cfi_send_command(bank
, 0x30, cfi_flash_address(bank
, i
, 0x0));
925 if (retval
!= ERROR_OK
)
928 if (cfi_spansion_wait_status_busy(bank
, cfi_info
->block_erase_timeout
) != ERROR_OK
) {
929 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
930 if (retval
!= ERROR_OK
)
933 LOG_ERROR("couldn't erase block %i of flash bank at base "
934 TARGET_ADDR_FMT
, i
, bank
->base
);
935 return ERROR_FLASH_OPERATION_FAILED
;
939 return cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
942 int cfi_erase(struct flash_bank
*bank
, unsigned int first
,
945 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
947 if (bank
->target
->state
!= TARGET_HALTED
) {
948 LOG_ERROR("Target not halted");
949 return ERROR_TARGET_NOT_HALTED
;
952 if ((last
< first
) || (last
>= bank
->num_sectors
))
953 return ERROR_FLASH_SECTOR_INVALID
;
955 if (cfi_info
->qry
[0] != 'Q')
956 return ERROR_FLASH_BANK_NOT_PROBED
;
958 switch (cfi_info
->pri_id
) {
961 return cfi_intel_erase(bank
, first
, last
);
963 return cfi_spansion_erase(bank
, first
, last
);
965 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
972 static int cfi_intel_protect(struct flash_bank
*bank
, int set
,
973 unsigned int first
, unsigned int last
)
976 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
977 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
980 /* if the device supports neither legacy lock/unlock (bit 3) nor
981 * instant individual block locking (bit 5).
983 if (!(pri_ext
->feature_support
& 0x28)) {
984 LOG_ERROR("lock/unlock not supported on flash");
985 return ERROR_FLASH_OPERATION_FAILED
;
988 cfi_intel_clear_status_register(bank
);
990 for (unsigned int i
= first
; i
<= last
; i
++) {
991 retval
= cfi_send_command(bank
, 0x60, cfi_flash_address(bank
, i
, 0x0));
992 if (retval
!= ERROR_OK
)
995 retval
= cfi_send_command(bank
, 0x01, cfi_flash_address(bank
, i
, 0x0));
996 if (retval
!= ERROR_OK
)
998 bank
->sectors
[i
].is_protected
= 1;
1000 retval
= cfi_send_command(bank
, 0xd0, cfi_flash_address(bank
, i
, 0x0));
1001 if (retval
!= ERROR_OK
)
1003 bank
->sectors
[i
].is_protected
= 0;
1006 /* instant individual block locking doesn't require reading of the status register
1008 if (!(pri_ext
->feature_support
& 0x20)) {
1009 /* Clear lock bits operation may take up to 1.4s */
1011 retval
= cfi_intel_wait_status_busy(bank
, 1400, &status
);
1012 if (retval
!= ERROR_OK
)
1015 uint8_t block_status
;
1016 /* read block lock bit, to verify status */
1017 retval
= cfi_send_command(bank
, 0x90, cfi_flash_address(bank
, 0, 0x55));
1018 if (retval
!= ERROR_OK
)
1020 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
1021 if (retval
!= ERROR_OK
)
1024 if ((block_status
& 0x1) != set
) {
1026 "couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
1028 retval
= cfi_send_command(bank
, 0x70, cfi_flash_address(bank
, 0, 0x55));
1029 if (retval
!= ERROR_OK
)
1032 retval
= cfi_intel_wait_status_busy(bank
, 10, &status
);
1033 if (retval
!= ERROR_OK
)
1037 return ERROR_FLASH_OPERATION_FAILED
;
1046 /* if the device doesn't support individual block lock bits set/clear,
1047 * all blocks have been unlocked in parallel, so we set those that should be protected
1049 if ((!set
) && (!(pri_ext
->feature_support
& 0x20))) {
1050 /* FIX!!! this code path is broken!!!
1052 * The correct approach is:
1054 * 1. read out current protection status
1056 * 2. override read out protection status w/unprotected.
1058 * 3. re-protect what should be protected.
1061 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
1062 if (bank
->sectors
[i
].is_protected
== 1) {
1063 cfi_intel_clear_status_register(bank
);
1065 retval
= cfi_send_command(bank
, 0x60, cfi_flash_address(bank
, i
, 0x0));
1066 if (retval
!= ERROR_OK
)
1069 retval
= cfi_send_command(bank
, 0x01, cfi_flash_address(bank
, i
, 0x0));
1070 if (retval
!= ERROR_OK
)
1074 retval
= cfi_intel_wait_status_busy(bank
, 100, &status
);
1075 if (retval
!= ERROR_OK
)
1081 return cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
1084 int cfi_protect(struct flash_bank
*bank
, int set
, unsigned int first
,
1087 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1089 if (bank
->target
->state
!= TARGET_HALTED
) {
1090 LOG_ERROR("Target not halted");
1091 return ERROR_TARGET_NOT_HALTED
;
1094 if (cfi_info
->qry
[0] != 'Q')
1095 return ERROR_FLASH_BANK_NOT_PROBED
;
1097 switch (cfi_info
->pri_id
) {
1100 return cfi_intel_protect(bank
, set
, first
, last
);
1102 LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info
->pri_id
);
1107 static uint32_t cfi_command_val(struct flash_bank
*bank
, uint8_t cmd
)
1109 struct target
*target
= bank
->target
;
1111 uint8_t buf
[CFI_MAX_BUS_WIDTH
];
1112 cfi_command(bank
, cmd
, buf
);
1113 switch (bank
->bus_width
) {
1117 return target_buffer_get_u16(target
, buf
);
1119 return target_buffer_get_u32(target
, buf
);
1121 LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
1127 static int cfi_intel_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1128 uint32_t address
, uint32_t count
)
1130 struct target
*target
= bank
->target
;
1131 struct reg_param reg_params
[7];
1132 struct arm_algorithm arm_algo
;
1133 struct working_area
*write_algorithm
;
1134 struct working_area
*source
= NULL
;
1135 uint32_t buffer_size
= 32768;
1136 uint32_t write_command_val
, busy_pattern_val
, error_pattern_val
;
1138 /* algorithm register usage:
1139 * r0: source address (in RAM)
1140 * r1: target address (in Flash)
1142 * r3: flash write command
1143 * r4: status byte (returned to host)
1144 * r5: busy test pattern
1145 * r6: error test pattern
1148 /* see contrib/loaders/flash/armv4_5_cfi_intel_32.s for src */
1149 static const uint32_t word_32_code
[] = {
1150 0xe4904004, /* loop: ldr r4, [r0], #4 */
1151 0xe5813000, /* str r3, [r1] */
1152 0xe5814000, /* str r4, [r1] */
1153 0xe5914000, /* busy: ldr r4, [r1] */
1154 0xe0047005, /* and r7, r4, r5 */
1155 0xe1570005, /* cmp r7, r5 */
1156 0x1afffffb, /* bne busy */
1157 0xe1140006, /* tst r4, r6 */
1158 0x1a000003, /* bne done */
1159 0xe2522001, /* subs r2, r2, #1 */
1160 0x0a000001, /* beq done */
1161 0xe2811004, /* add r1, r1 #4 */
1162 0xeafffff2, /* b loop */
1163 0xeafffffe /* done: b -2 */
1166 /* see contrib/loaders/flash/armv4_5_cfi_intel_16.s for src */
1167 static const uint32_t word_16_code
[] = {
1168 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1169 0xe1c130b0, /* strh r3, [r1] */
1170 0xe1c140b0, /* strh r4, [r1] */
1171 0xe1d140b0, /* busy ldrh r4, [r1] */
1172 0xe0047005, /* and r7, r4, r5 */
1173 0xe1570005, /* cmp r7, r5 */
1174 0x1afffffb, /* bne busy */
1175 0xe1140006, /* tst r4, r6 */
1176 0x1a000003, /* bne done */
1177 0xe2522001, /* subs r2, r2, #1 */
1178 0x0a000001, /* beq done */
1179 0xe2811002, /* add r1, r1 #2 */
1180 0xeafffff2, /* b loop */
1181 0xeafffffe /* done: b -2 */
1184 /* see contrib/loaders/flash/armv4_5_cfi_intel_8.s for src */
1185 static const uint32_t word_8_code
[] = {
1186 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1187 0xe5c13000, /* strb r3, [r1] */
1188 0xe5c14000, /* strb r4, [r1] */
1189 0xe5d14000, /* busy ldrb r4, [r1] */
1190 0xe0047005, /* and r7, r4, r5 */
1191 0xe1570005, /* cmp r7, r5 */
1192 0x1afffffb, /* bne busy */
1193 0xe1140006, /* tst r4, r6 */
1194 0x1a000003, /* bne done */
1195 0xe2522001, /* subs r2, r2, #1 */
1196 0x0a000001, /* beq done */
1197 0xe2811001, /* add r1, r1 #1 */
1198 0xeafffff2, /* b loop */
1199 0xeafffffe /* done: b -2 */
1201 uint8_t target_code
[4*CFI_MAX_INTEL_CODESIZE
];
1202 const uint32_t *target_code_src
;
1203 uint32_t target_code_size
;
1204 int retval
= ERROR_OK
;
1206 /* check we have a supported arch */
1207 if (is_arm(target_to_arm(target
))) {
1208 /* All other ARM CPUs have 32 bit instructions */
1209 arm_algo
.common_magic
= ARM_COMMON_MAGIC
;
1210 arm_algo
.core_mode
= ARM_MODE_SVC
;
1211 arm_algo
.core_state
= ARM_STATE_ARM
;
1213 LOG_ERROR("Unknown architecture");
1214 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1217 cfi_intel_clear_status_register(bank
);
1219 /* If we are setting up the write_algorithm, we need target_code_src
1220 * if not we only need target_code_size. */
1222 /* However, we don't want to create multiple code paths, so we
1223 * do the unnecessary evaluation of target_code_src, which the
1224 * compiler will probably nicely optimize away if not needed */
1226 /* prepare algorithm code for target endian */
1227 switch (bank
->bus_width
) {
1229 target_code_src
= word_8_code
;
1230 target_code_size
= sizeof(word_8_code
);
1233 target_code_src
= word_16_code
;
1234 target_code_size
= sizeof(word_16_code
);
1237 target_code_src
= word_32_code
;
1238 target_code_size
= sizeof(word_32_code
);
1241 LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
1243 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1246 /* flash write code */
1247 if (target_code_size
> sizeof(target_code
)) {
1248 LOG_WARNING("Internal error - target code buffer to small. "
1249 "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1250 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1253 target_buffer_set_u32_array(target
, target_code
, target_code_size
/ 4, target_code_src
);
1255 /* Get memory for block write handler */
1256 retval
= target_alloc_working_area(target
,
1259 if (retval
!= ERROR_OK
) {
1260 LOG_WARNING("No working area available, can't do block memory writes");
1261 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1264 /* write algorithm code to working area */
1265 retval
= target_write_buffer(target
, write_algorithm
->address
,
1266 target_code_size
, target_code
);
1267 if (retval
!= ERROR_OK
) {
1268 LOG_ERROR("Unable to write block write code to target");
1272 /* Get a workspace buffer for the data to flash starting with 32k size.
1273 * Half size until buffer would be smaller 256 Bytes then fail back */
1274 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1275 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
1277 if (buffer_size
<= 256) {
1279 "no large enough working area available, can't do block memory writes");
1280 retval
= ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1285 /* setup algo registers */
1286 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1287 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1288 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1289 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1290 init_reg_param(®_params
[4], "r4", 32, PARAM_IN
);
1291 init_reg_param(®_params
[5], "r5", 32, PARAM_OUT
);
1292 init_reg_param(®_params
[6], "r6", 32, PARAM_OUT
);
1294 /* prepare command and status register patterns */
1295 write_command_val
= cfi_command_val(bank
, 0x40);
1296 busy_pattern_val
= cfi_command_val(bank
, 0x80);
1297 error_pattern_val
= cfi_command_val(bank
, 0x7e);
1299 LOG_DEBUG("Using target buffer at " TARGET_ADDR_FMT
" and of size 0x%04" PRIx32
,
1300 source
->address
, buffer_size
);
1302 /* Programming main loop */
1304 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1307 retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1308 if (retval
!= ERROR_OK
)
1311 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1312 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1313 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1315 buf_set_u32(reg_params
[3].value
, 0, 32, write_command_val
);
1316 buf_set_u32(reg_params
[5].value
, 0, 32, busy_pattern_val
);
1317 buf_set_u32(reg_params
[6].value
, 0, 32, error_pattern_val
);
1319 LOG_DEBUG("Write 0x%04" PRIx32
" bytes to flash at 0x%08" PRIx32
,
1320 thisrun_count
, address
);
1322 /* Execute algorithm, assume breakpoint for last instruction */
1323 retval
= target_run_algorithm(target
, 0, NULL
, 7, reg_params
,
1324 write_algorithm
->address
,
1325 write_algorithm
->address
+ target_code_size
-
1327 10000, /* 10s should be enough for max. 32k of data */
1330 /* On failure try a fall back to direct word writes */
1331 if (retval
!= ERROR_OK
) {
1332 cfi_intel_clear_status_register(bank
);
1334 "Execution of flash algorithm failed. Can't fall back. Please report.");
1335 retval
= ERROR_FLASH_OPERATION_FAILED
;
1336 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1337 /* FIXME To allow fall back or recovery, we must save the actual status
1338 * somewhere, so that a higher level code can start recovery. */
1342 /* Check return value from algo code */
1343 wsm_error
= buf_get_u32(reg_params
[4].value
, 0, 32) & error_pattern_val
;
1345 /* read status register (outputs debug information) */
1347 cfi_intel_wait_status_busy(bank
, 100, &status
);
1348 cfi_intel_clear_status_register(bank
);
1349 retval
= ERROR_FLASH_OPERATION_FAILED
;
1353 buffer
+= thisrun_count
;
1354 address
+= thisrun_count
;
1355 count
-= thisrun_count
;
1360 /* free up resources */
1362 target_free_working_area(target
, source
);
1363 target_free_working_area(target
, write_algorithm
);
1365 destroy_reg_param(®_params
[0]);
1366 destroy_reg_param(®_params
[1]);
1367 destroy_reg_param(®_params
[2]);
1368 destroy_reg_param(®_params
[3]);
1369 destroy_reg_param(®_params
[4]);
1370 destroy_reg_param(®_params
[5]);
1371 destroy_reg_param(®_params
[6]);
1376 static int cfi_spansion_write_block_mips(struct flash_bank
*bank
, const uint8_t *buffer
,
1377 uint32_t address
, uint32_t count
)
1379 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1380 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1381 struct target
*target
= bank
->target
;
1382 struct reg_param reg_params
[10];
1383 struct mips32_algorithm mips32_info
;
1384 struct working_area
*write_algorithm
;
1385 struct working_area
*source
;
1386 uint32_t buffer_size
= 32768;
1388 int retval
= ERROR_OK
;
1390 /* input parameters -
1391 * 4 A0 = source address
1392 * 5 A1 = destination address
1393 * 6 A2 = number of writes
1394 * 7 A3 = flash write command
1395 * 8 T0 = constant to mask DQ7 bits (also used for Dq5 with shift)
1396 * output parameters -
1397 * 9 T1 = 0x80 ok 0x00 bad
1399 * 10 T2 = value read from flash to test status
1400 * 11 T3 = holding register
1401 * unlock registers -
1402 * 12 T4 = unlock1_addr
1403 * 13 T5 = unlock1_cmd
1404 * 14 T6 = unlock2_addr
1405 * 15 T7 = unlock2_cmd */
1407 static const uint32_t mips_word_16_code
[] = {
1409 MIPS32_LHU(0, 9, 0, 4), /* lhu $t1, ($a0) ; out = &saddr */
1410 MIPS32_ADDI(0, 4, 4, 2), /* addi $a0, $a0, 2 ; saddr += 2 */
1411 MIPS32_SH(0, 13, 0, 12), /* sh $t5, ($t4) ; *fl_unl_addr1 = fl_unl_cmd1 */
1412 MIPS32_SH(0, 15, 0, 14), /* sh $t7, ($t6) ; *fl_unl_addr2 = fl_unl_cmd2 */
1413 MIPS32_SH(0, 7, 0, 12), /* sh $a3, ($t4) ; *fl_unl_addr1 = fl_write_cmd */
1414 MIPS32_SH(0, 9, 0, 5), /* sh $t1, ($a1) ; *daddr = out */
1415 MIPS32_NOP
, /* nop */
1417 MIPS32_LHU(0, 10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */
1418 MIPS32_XOR(0, 11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
1419 MIPS32_AND(0, 11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
1420 MIPS32_BNE(0, 11, 8, 13), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
1421 MIPS32_NOP
, /* nop */
1423 MIPS32_SRL(0, 10, 8, 2), /* srl $t2,$t0,2 ; temp1 = DQ7mask >> 2 */
1424 MIPS32_AND(0, 11, 10, 11), /* and $t3, $t2, $t3 ; temp2 = temp2 & temp1 */
1425 MIPS32_BNE(0, 11, 10, NEG16(8)), /* bne $t3, $t2, busy ; if (temp2 != temp1) goto busy */
1426 MIPS32_NOP
, /* nop */
1428 MIPS32_LHU(0, 10, 0, 5), /* lhu $t2, ($a1) ; temp1 = *daddr */
1429 MIPS32_XOR(0, 11, 9, 10), /* xor $t3, $a0, $t2 ; temp2 = out ^ temp1; */
1430 MIPS32_AND(0, 11, 8, 11), /* and $t3, $t0, $t3 ; temp2 = temp2 & DQ7mask */
1431 MIPS32_BNE(0, 11, 8, 4), /* bne $t3, $t0, cont ; if (temp2 != DQ7mask) goto cont */
1432 MIPS32_NOP
, /* nop */
1434 MIPS32_XOR(0, 9, 9, 9), /* xor $t1, $t1, $t1 ; out = 0 */
1435 MIPS32_BEQ(0, 9, 0, 11), /* beq $t1, $zero, done ; if (out == 0) goto done */
1436 MIPS32_NOP
, /* nop */
1438 MIPS32_ADDI(0, 6, 6, NEG16(1)), /* addi, $a2, $a2, -1 ; numwrites-- */
1439 MIPS32_BNE(0, 6, 0, 5), /* bne $a2, $zero, cont2 ; if (numwrite != 0) goto cont2 */
1440 MIPS32_NOP
, /* nop */
1442 MIPS32_LUI(0, 9, 0), /* lui $t1, 0 */
1443 MIPS32_ORI(0, 9, 9, 0x80), /* ori $t1, $t1, 0x80 ; out = 0x80 */
1445 MIPS32_B(0, 4), /* b done ; goto done */
1446 MIPS32_NOP
, /* nop */
1448 MIPS32_ADDI(0, 5, 5, 2), /* addi $a0, $a0, 2 ; daddr += 2 */
1449 MIPS32_B(0, NEG16(33)), /* b start ; goto start */
1450 MIPS32_NOP
, /* nop */
1452 MIPS32_SDBBP(0), /* sdbbp ; break(); */
1455 mips32_info
.common_magic
= MIPS32_COMMON_MAGIC
;
1456 mips32_info
.isa_mode
= MIPS32_ISA_MIPS32
;
1458 int target_code_size
= 0;
1459 const uint32_t *target_code_src
= NULL
;
1461 switch (bank
->bus_width
) {
1463 /* Check for DQ5 support */
1464 if (cfi_info
->status_poll_mask
& (1 << 5)) {
1465 target_code_src
= mips_word_16_code
;
1466 target_code_size
= sizeof(mips_word_16_code
);
1468 LOG_ERROR("Need DQ5 support");
1469 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1470 /* target_code_src = mips_word_16_code_dq7only; */
1471 /* target_code_size = sizeof(mips_word_16_code_dq7only); */
1475 LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
1477 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1480 /* flash write code */
1481 uint8_t *target_code
;
1483 /* convert bus-width dependent algorithm code to correct endianness */
1484 target_code
= malloc(target_code_size
);
1486 LOG_ERROR("Out of memory");
1490 target_buffer_set_u32_array(target
, target_code
, target_code_size
/ 4, target_code_src
);
1492 /* allocate working area */
1493 retval
= target_alloc_working_area(target
, target_code_size
,
1495 if (retval
!= ERROR_OK
) {
1500 /* write algorithm code to working area */
1501 retval
= target_write_buffer(target
, write_algorithm
->address
,
1502 target_code_size
, target_code
);
1503 if (retval
!= ERROR_OK
) {
1510 /* the following code still assumes target code is fixed 24*4 bytes */
1512 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
1514 if (buffer_size
<= 256) {
1515 /* we already allocated the writing code, but failed to get a
1516 * buffer, free the algorithm */
1517 target_free_working_area(target
, write_algorithm
);
1520 "not enough working area available, can't do block memory writes");
1521 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1525 init_reg_param(®_params
[0], "r4", 32, PARAM_OUT
);
1526 init_reg_param(®_params
[1], "r5", 32, PARAM_OUT
);
1527 init_reg_param(®_params
[2], "r6", 32, PARAM_OUT
);
1528 init_reg_param(®_params
[3], "r7", 32, PARAM_OUT
);
1529 init_reg_param(®_params
[4], "r8", 32, PARAM_OUT
);
1530 init_reg_param(®_params
[5], "r9", 32, PARAM_IN
);
1531 init_reg_param(®_params
[6], "r12", 32, PARAM_OUT
);
1532 init_reg_param(®_params
[7], "r13", 32, PARAM_OUT
);
1533 init_reg_param(®_params
[8], "r14", 32, PARAM_OUT
);
1534 init_reg_param(®_params
[9], "r15", 32, PARAM_OUT
);
1537 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1539 retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1540 if (retval
!= ERROR_OK
)
1543 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1544 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1545 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1546 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1547 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1548 buf_set_u32(reg_params
[6].value
, 0, 32, cfi_flash_address(bank
, 0, pri_ext
->_unlock1
));
1549 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1550 buf_set_u32(reg_params
[8].value
, 0, 32, cfi_flash_address(bank
, 0, pri_ext
->_unlock2
));
1551 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1553 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1554 write_algorithm
->address
,
1555 write_algorithm
->address
+ ((target_code_size
) - 4),
1556 10000, &mips32_info
);
1557 if (retval
!= ERROR_OK
)
1560 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1561 if (status
!= 0x80) {
1562 LOG_ERROR("flash write block failed status: 0x%" PRIx32
, status
);
1563 retval
= ERROR_FLASH_OPERATION_FAILED
;
1567 buffer
+= thisrun_count
;
1568 address
+= thisrun_count
;
1569 count
-= thisrun_count
;
1572 target_free_all_working_areas(target
);
1574 destroy_reg_param(®_params
[0]);
1575 destroy_reg_param(®_params
[1]);
1576 destroy_reg_param(®_params
[2]);
1577 destroy_reg_param(®_params
[3]);
1578 destroy_reg_param(®_params
[4]);
1579 destroy_reg_param(®_params
[5]);
1580 destroy_reg_param(®_params
[6]);
1581 destroy_reg_param(®_params
[7]);
1582 destroy_reg_param(®_params
[8]);
1583 destroy_reg_param(®_params
[9]);
1588 static int cfi_spansion_write_block(struct flash_bank
*bank
, const uint8_t *buffer
,
1589 uint32_t address
, uint32_t count
)
1591 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1592 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
1593 struct target
*target
= bank
->target
;
1594 struct reg_param reg_params
[10];
1596 struct arm_algorithm armv4_5_algo
;
1597 struct armv7m_algorithm armv7m_algo
;
1598 struct working_area
*write_algorithm
;
1599 struct working_area
*source
;
1600 uint32_t buffer_size
= 32768;
1602 int retval
= ERROR_OK
;
1604 /* input parameters -
1605 * R0 = source address
1606 * R1 = destination address
1607 * R2 = number of writes
1608 * R3 = flash write command
1609 * R4 = constant to mask DQ7 bits (also used for Dq5 with shift)
1610 * output parameters -
1611 * R5 = 0x80 ok 0x00 bad
1613 * R6 = value read from flash to test status
1614 * R7 = holding register
1615 * unlock registers -
1618 * R10 = unlock2_addr
1619 * R11 = unlock2_cmd */
1621 /* see contrib/loaders/flash/armv4_5_cfi_span_32.s for src */
1622 static const uint32_t armv4_5_word_32_code
[] = {
1623 /* 00008100 <sp_32_code>: */
1624 0xe4905004, /* ldr r5, [r0], #4 */
1625 0xe5889000, /* str r9, [r8] */
1626 0xe58ab000, /* str r11, [r10] */
1627 0xe5883000, /* str r3, [r8] */
1628 0xe5815000, /* str r5, [r1] */
1629 0xe1a00000, /* nop */
1630 /* 00008110 <sp_32_busy>: */
1631 0xe5916000, /* ldr r6, [r1] */
1632 0xe0257006, /* eor r7, r5, r6 */
1633 0xe0147007, /* ands r7, r4, r7 */
1634 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1635 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1636 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1637 0xe5916000, /* ldr r6, [r1] */
1638 0xe0257006, /* eor r7, r5, r6 */
1639 0xe0147007, /* ands r7, r4, r7 */
1640 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1641 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1642 0x1a000004, /* bne 8154 <sp_32_done> */
1643 /* 00008140 <sp_32_cont>: */
1644 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1645 0x03a05080, /* moveq r5, #128 ; 0x80 */
1646 0x0a000001, /* beq 8154 <sp_32_done> */
1647 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1648 0xeaffffe8, /* b 8100 <sp_32_code> */
1649 /* 00008154 <sp_32_done>: */
1650 0xeafffffe /* b 8154 <sp_32_done> */
1653 /* see contrib/loaders/flash/armv4_5_cfi_span_16.s for src */
1654 static const uint32_t armv4_5_word_16_code
[] = {
1655 /* 00008158 <sp_16_code>: */
1656 0xe0d050b2, /* ldrh r5, [r0], #2 */
1657 0xe1c890b0, /* strh r9, [r8] */
1658 0xe1cab0b0, /* strh r11, [r10] */
1659 0xe1c830b0, /* strh r3, [r8] */
1660 0xe1c150b0, /* strh r5, [r1] */
1661 0xe1a00000, /* nop (mov r0,r0) */
1662 /* 00008168 <sp_16_busy>: */
1663 0xe1d160b0, /* ldrh r6, [r1] */
1664 0xe0257006, /* eor r7, r5, r6 */
1665 0xe0147007, /* ands r7, r4, r7 */
1666 0x0a000007, /* beq 8198 <sp_16_cont> */
1667 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1668 0x0afffff9, /* beq 8168 <sp_16_busy> */
1669 0xe1d160b0, /* ldrh r6, [r1] */
1670 0xe0257006, /* eor r7, r5, r6 */
1671 0xe0147007, /* ands r7, r4, r7 */
1672 0x0a000001, /* beq 8198 <sp_16_cont> */
1673 0xe3a05000, /* mov r5, #0 ; 0x0 */
1674 0x1a000004, /* bne 81ac <sp_16_done> */
1675 /* 00008198 <sp_16_cont>: */
1676 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1677 0x03a05080, /* moveq r5, #128 ; 0x80 */
1678 0x0a000001, /* beq 81ac <sp_16_done> */
1679 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1680 0xeaffffe8, /* b 8158 <sp_16_code> */
1681 /* 000081ac <sp_16_done>: */
1682 0xeafffffe /* b 81ac <sp_16_done> */
1685 /* see contrib/loaders/flash/armv7m_cfi_span_16.s for src */
1686 static const uint32_t armv7m_word_16_code
[] = {
1707 /* see contrib/loaders/flash/armv7m_cfi_span_16_dq7.s for src */
1708 static const uint32_t armv7m_word_16_code_dq7only
[] = {
1709 /* 00000000 <code>: */
1710 0x5B02F830, /* ldrh.w r5, [r0], #2 */
1711 0x9000F8A8, /* strh.w r9, [r8] */
1712 0xB000F8AA, /* strh.w fp, [sl] */
1713 0x3000F8A8, /* strh.w r3, [r8] */
1714 0xBF00800D, /* strh r5, [r1, #0] */
1717 /* 00000014 <busy>: */
1718 0xEA85880E, /* ldrh r6, [r1, #0] */
1719 /* eor.w r7, r5, r6 */
1720 0x40270706, /* ands r7, r4 */
1721 0x3A01D1FA, /* bne.n 14 <busy> */
1723 0xF101D002, /* beq.n 28 <success> */
1724 0xE7EB0102, /* add.w r1, r1, #2 */
1727 /* 00000028 <success>: */
1728 0x0580F04F, /* mov.w r5, #128 */
1729 0xBF00E7FF, /* b.n 30 <done> */
1730 /* nop (for alignment purposes) */
1732 /* 00000030 <done>: */
1733 0x0000BE00 /* bkpt 0x0000 */
1736 /* see contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
1737 static const uint32_t armv4_5_word_16_code_dq7only
[] = {
1739 0xe0d050b2, /* ldrh r5, [r0], #2 */
1740 0xe1c890b0, /* strh r9, [r8] */
1741 0xe1cab0b0, /* strh r11, [r10] */
1742 0xe1c830b0, /* strh r3, [r8] */
1743 0xe1c150b0, /* strh r5, [r1] */
1744 0xe1a00000, /* nop (mov r0,r0) */
1746 0xe1d160b0, /* ldrh r6, [r1] */
1747 0xe0257006, /* eor r7, r5, r6 */
1748 0xe2177080, /* ands r7, #0x80 */
1749 0x1afffffb, /* bne 8168 <sp_16_busy> */
1751 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1752 0x03a05080, /* moveq r5, #128 ; 0x80 */
1753 0x0a000001, /* beq 81ac <sp_16_done> */
1754 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1755 0xeafffff0, /* b 8158 <sp_16_code> */
1756 /* 000081ac <sp_16_done>: */
1757 0xeafffffe /* b 81ac <sp_16_done> */
1760 /* see contrib/loaders/flash/armv4_5_cfi_span_8.s for src */
1761 static const uint32_t armv4_5_word_8_code
[] = {
1762 /* 000081b0 <sp_16_code_end>: */
1763 0xe4d05001, /* ldrb r5, [r0], #1 */
1764 0xe5c89000, /* strb r9, [r8] */
1765 0xe5cab000, /* strb r11, [r10] */
1766 0xe5c83000, /* strb r3, [r8] */
1767 0xe5c15000, /* strb r5, [r1] */
1768 0xe1a00000, /* nop (mov r0,r0) */
1769 /* 000081c0 <sp_8_busy>: */
1770 0xe5d16000, /* ldrb r6, [r1] */
1771 0xe0257006, /* eor r7, r5, r6 */
1772 0xe0147007, /* ands r7, r4, r7 */
1773 0x0a000007, /* beq 81f0 <sp_8_cont> */
1774 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1775 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1776 0xe5d16000, /* ldrb r6, [r1] */
1777 0xe0257006, /* eor r7, r5, r6 */
1778 0xe0147007, /* ands r7, r4, r7 */
1779 0x0a000001, /* beq 81f0 <sp_8_cont> */
1780 0xe3a05000, /* mov r5, #0 ; 0x0 */
1781 0x1a000004, /* bne 8204 <sp_8_done> */
1782 /* 000081f0 <sp_8_cont>: */
1783 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1784 0x03a05080, /* moveq r5, #128 ; 0x80 */
1785 0x0a000001, /* beq 8204 <sp_8_done> */
1786 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1787 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1788 /* 00008204 <sp_8_done>: */
1789 0xeafffffe /* b 8204 <sp_8_done> */
1792 if (strncmp(target_type_name(target
), "mips_m4k", 8) == 0)
1793 return cfi_spansion_write_block_mips(bank
, buffer
, address
, count
);
1795 if (is_armv7m(target_to_armv7m(target
))) { /* armv7m target */
1796 armv7m_algo
.common_magic
= ARMV7M_COMMON_MAGIC
;
1797 armv7m_algo
.core_mode
= ARM_MODE_THREAD
;
1798 arm_algo
= &armv7m_algo
;
1799 } else if (is_arm(target_to_arm(target
))) {
1800 /* All other ARM CPUs have 32 bit instructions */
1801 armv4_5_algo
.common_magic
= ARM_COMMON_MAGIC
;
1802 armv4_5_algo
.core_mode
= ARM_MODE_SVC
;
1803 armv4_5_algo
.core_state
= ARM_STATE_ARM
;
1804 arm_algo
= &armv4_5_algo
;
1806 LOG_ERROR("Unknown architecture");
1807 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1810 int target_code_size
= 0;
1811 const uint32_t *target_code_src
= NULL
;
1813 switch (bank
->bus_width
) {
1815 if (is_armv7m(target_to_armv7m(target
))) {
1816 LOG_ERROR("Unknown ARM architecture");
1819 target_code_src
= armv4_5_word_8_code
;
1820 target_code_size
= sizeof(armv4_5_word_8_code
);
1823 /* Check for DQ5 support */
1824 if (cfi_info
->status_poll_mask
& (1 << 5)) {
1825 if (is_armv7m(target_to_armv7m(target
))) {
1827 target_code_src
= armv7m_word_16_code
;
1828 target_code_size
= sizeof(armv7m_word_16_code
);
1829 } else { /* armv4_5 target */
1830 target_code_src
= armv4_5_word_16_code
;
1831 target_code_size
= sizeof(armv4_5_word_16_code
);
1834 /* No DQ5 support. Use DQ7 DATA# polling only. */
1835 if (is_armv7m(target_to_armv7m(target
))) {
1837 target_code_src
= armv7m_word_16_code_dq7only
;
1838 target_code_size
= sizeof(armv7m_word_16_code_dq7only
);
1839 } else { /* armv4_5 target */
1840 target_code_src
= armv4_5_word_16_code_dq7only
;
1841 target_code_size
= sizeof(armv4_5_word_16_code_dq7only
);
1846 if (is_armv7m(target_to_armv7m(target
))) {
1847 LOG_ERROR("Unknown ARM architecture");
1850 target_code_src
= armv4_5_word_32_code
;
1851 target_code_size
= sizeof(armv4_5_word_32_code
);
1854 LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
1856 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1859 /* flash write code */
1860 uint8_t *target_code
;
1862 /* convert bus-width dependent algorithm code to correct endianness */
1863 target_code
= malloc(target_code_size
);
1865 LOG_ERROR("Out of memory");
1869 target_buffer_set_u32_array(target
, target_code
, target_code_size
/ 4, target_code_src
);
1871 /* allocate working area */
1872 retval
= target_alloc_working_area(target
, target_code_size
,
1874 if (retval
!= ERROR_OK
) {
1879 /* write algorithm code to working area */
1880 retval
= target_write_buffer(target
, write_algorithm
->address
,
1881 target_code_size
, target_code
);
1882 if (retval
!= ERROR_OK
) {
1889 /* the following code still assumes target code is fixed 24*4 bytes */
1891 while (target_alloc_working_area_try(target
, buffer_size
, &source
) != ERROR_OK
) {
1893 if (buffer_size
<= 256) {
1894 /* we already allocated the writing code, but failed to get a
1895 * buffer, free the algorithm */
1896 target_free_working_area(target
, write_algorithm
);
1899 "not enough working area available, can't do block memory writes");
1900 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1904 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
1905 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
1906 init_reg_param(®_params
[2], "r2", 32, PARAM_OUT
);
1907 init_reg_param(®_params
[3], "r3", 32, PARAM_OUT
);
1908 init_reg_param(®_params
[4], "r4", 32, PARAM_OUT
);
1909 init_reg_param(®_params
[5], "r5", 32, PARAM_IN
);
1910 init_reg_param(®_params
[6], "r8", 32, PARAM_OUT
);
1911 init_reg_param(®_params
[7], "r9", 32, PARAM_OUT
);
1912 init_reg_param(®_params
[8], "r10", 32, PARAM_OUT
);
1913 init_reg_param(®_params
[9], "r11", 32, PARAM_OUT
);
1916 uint32_t thisrun_count
= (count
> buffer_size
) ? buffer_size
: count
;
1918 retval
= target_write_buffer(target
, source
->address
, thisrun_count
, buffer
);
1919 if (retval
!= ERROR_OK
)
1922 buf_set_u32(reg_params
[0].value
, 0, 32, source
->address
);
1923 buf_set_u32(reg_params
[1].value
, 0, 32, address
);
1924 buf_set_u32(reg_params
[2].value
, 0, 32, thisrun_count
/ bank
->bus_width
);
1925 buf_set_u32(reg_params
[3].value
, 0, 32, cfi_command_val(bank
, 0xA0));
1926 buf_set_u32(reg_params
[4].value
, 0, 32, cfi_command_val(bank
, 0x80));
1927 buf_set_u32(reg_params
[6].value
, 0, 32, cfi_flash_address(bank
, 0, pri_ext
->_unlock1
));
1928 buf_set_u32(reg_params
[7].value
, 0, 32, 0xaaaaaaaa);
1929 buf_set_u32(reg_params
[8].value
, 0, 32, cfi_flash_address(bank
, 0, pri_ext
->_unlock2
));
1930 buf_set_u32(reg_params
[9].value
, 0, 32, 0x55555555);
1932 retval
= target_run_algorithm(target
, 0, NULL
, 10, reg_params
,
1933 write_algorithm
->address
,
1934 write_algorithm
->address
+ ((target_code_size
) - 4),
1936 if (retval
!= ERROR_OK
)
1939 status
= buf_get_u32(reg_params
[5].value
, 0, 32);
1940 if (status
!= 0x80) {
1941 LOG_ERROR("flash write block failed status: 0x%" PRIx32
, status
);
1942 retval
= ERROR_FLASH_OPERATION_FAILED
;
1946 buffer
+= thisrun_count
;
1947 address
+= thisrun_count
;
1948 count
-= thisrun_count
;
1951 target_free_all_working_areas(target
);
1953 destroy_reg_param(®_params
[0]);
1954 destroy_reg_param(®_params
[1]);
1955 destroy_reg_param(®_params
[2]);
1956 destroy_reg_param(®_params
[3]);
1957 destroy_reg_param(®_params
[4]);
1958 destroy_reg_param(®_params
[5]);
1959 destroy_reg_param(®_params
[6]);
1960 destroy_reg_param(®_params
[7]);
1961 destroy_reg_param(®_params
[8]);
1962 destroy_reg_param(®_params
[9]);
1967 static int cfi_intel_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
1970 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
1972 cfi_intel_clear_status_register(bank
);
1973 retval
= cfi_send_command(bank
, 0x40, address
);
1974 if (retval
!= ERROR_OK
)
1977 retval
= cfi_target_write_memory(bank
, address
, 1, word
);
1978 if (retval
!= ERROR_OK
)
1982 retval
= cfi_intel_wait_status_busy(bank
, cfi_info
->word_write_timeout
, &status
);
1983 if (retval
!= ERROR_OK
)
1985 if (status
!= 0x80) {
1986 retval
= cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
1987 if (retval
!= ERROR_OK
)
1990 LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
1991 ", address 0x%" PRIx32
,
1992 bank
->base
, address
);
1993 return ERROR_FLASH_OPERATION_FAILED
;
1999 static int cfi_intel_write_words(struct flash_bank
*bank
, const uint8_t *word
,
2000 uint32_t wordcount
, uint32_t address
)
2003 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2005 /* Calculate buffer size and boundary mask
2006 * buffersize is (buffer size per chip) * (number of chips)
2007 * bufferwsize is buffersize in words */
2008 uint32_t buffersize
=
2009 (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
2010 uint32_t buffermask
= buffersize
-1;
2011 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
2013 /* Check for valid range */
2014 if (address
& buffermask
) {
2015 LOG_ERROR("Write address at base " TARGET_ADDR_FMT
", address 0x%"
2016 PRIx32
" not aligned to 2^%d boundary",
2017 bank
->base
, address
, cfi_info
->max_buf_write_size
);
2018 return ERROR_FLASH_OPERATION_FAILED
;
2021 /* Check for valid size */
2022 if (wordcount
> bufferwsize
) {
2023 LOG_ERROR("Number of data words %" PRIu32
" exceeds available buffersize %" PRIu32
,
2024 wordcount
, buffersize
);
2025 return ERROR_FLASH_OPERATION_FAILED
;
2028 /* Write to flash buffer */
2029 cfi_intel_clear_status_register(bank
);
2031 /* Initiate buffer operation _*/
2032 retval
= cfi_send_command(bank
, 0xe8, address
);
2033 if (retval
!= ERROR_OK
)
2036 retval
= cfi_intel_wait_status_busy(bank
, cfi_info
->buf_write_timeout
, &status
);
2037 if (retval
!= ERROR_OK
)
2039 if (status
!= 0x80) {
2040 retval
= cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
2041 if (retval
!= ERROR_OK
)
2045 "couldn't start buffer write operation at base " TARGET_ADDR_FMT
2046 ", address 0x%" PRIx32
,
2049 return ERROR_FLASH_OPERATION_FAILED
;
2052 /* Write buffer wordcount-1 and data words */
2053 retval
= cfi_send_command(bank
, bufferwsize
-1, address
);
2054 if (retval
!= ERROR_OK
)
2057 retval
= cfi_target_write_memory(bank
, address
, bufferwsize
, word
);
2058 if (retval
!= ERROR_OK
)
2061 /* Commit write operation */
2062 retval
= cfi_send_command(bank
, 0xd0, address
);
2063 if (retval
!= ERROR_OK
)
2066 retval
= cfi_intel_wait_status_busy(bank
, cfi_info
->buf_write_timeout
, &status
);
2067 if (retval
!= ERROR_OK
)
2070 if (status
!= 0x80) {
2071 retval
= cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
2072 if (retval
!= ERROR_OK
)
2075 LOG_ERROR("Buffer write at base " TARGET_ADDR_FMT
2076 ", address 0x%" PRIx32
" failed.", bank
->base
, address
);
2077 return ERROR_FLASH_OPERATION_FAILED
;
2083 static int cfi_spansion_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
2086 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2087 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2089 retval
= cfi_spansion_unlock_seq(bank
);
2090 if (retval
!= ERROR_OK
)
2093 retval
= cfi_send_command(bank
, 0xa0, cfi_flash_address(bank
, 0, pri_ext
->_unlock1
));
2094 if (retval
!= ERROR_OK
)
2097 retval
= cfi_target_write_memory(bank
, address
, 1, word
);
2098 if (retval
!= ERROR_OK
)
2101 if (cfi_spansion_wait_status_busy(bank
, cfi_info
->word_write_timeout
) != ERROR_OK
) {
2102 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
2103 if (retval
!= ERROR_OK
)
2106 LOG_ERROR("couldn't write word at base " TARGET_ADDR_FMT
2107 ", address 0x%" PRIx32
, bank
->base
, address
);
2108 return ERROR_FLASH_OPERATION_FAILED
;
2114 static int cfi_spansion_write_words(struct flash_bank
*bank
, const uint8_t *word
,
2115 uint32_t wordcount
, uint32_t address
)
2118 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2120 /* Calculate buffer size and boundary mask
2121 * buffersize is (buffer size per chip) * (number of chips)
2122 * bufferwsize is buffersize in words */
2123 uint32_t buffersize
=
2124 (1UL << cfi_info
->max_buf_write_size
) * (bank
->bus_width
/ bank
->chip_width
);
2125 uint32_t buffermask
= buffersize
-1;
2126 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
2128 /* Check for valid range */
2129 if (address
& buffermask
) {
2130 LOG_ERROR("Write address at base " TARGET_ADDR_FMT
2131 ", address 0x%" PRIx32
" not aligned to 2^%d boundary",
2132 bank
->base
, address
, cfi_info
->max_buf_write_size
);
2133 return ERROR_FLASH_OPERATION_FAILED
;
2136 /* Check for valid size */
2137 if (wordcount
> bufferwsize
) {
2138 LOG_ERROR("Number of data words %" PRIu32
" exceeds available buffersize %"
2139 PRIu32
, wordcount
, buffersize
);
2140 return ERROR_FLASH_OPERATION_FAILED
;
2144 retval
= cfi_spansion_unlock_seq(bank
);
2145 if (retval
!= ERROR_OK
)
2148 /* Buffer load command */
2149 retval
= cfi_send_command(bank
, 0x25, address
);
2150 if (retval
!= ERROR_OK
)
2153 /* Write buffer wordcount-1 and data words */
2154 retval
= cfi_send_command(bank
, bufferwsize
-1, address
);
2155 if (retval
!= ERROR_OK
)
2158 retval
= cfi_target_write_memory(bank
, address
, bufferwsize
, word
);
2159 if (retval
!= ERROR_OK
)
2162 /* Commit write operation */
2163 retval
= cfi_send_command(bank
, 0x29, address
);
2164 if (retval
!= ERROR_OK
)
2167 if (cfi_spansion_wait_status_busy(bank
, cfi_info
->buf_write_timeout
) != ERROR_OK
) {
2168 retval
= cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
2169 if (retval
!= ERROR_OK
)
2172 LOG_ERROR("couldn't write block at base " TARGET_ADDR_FMT
2173 ", address 0x%" PRIx32
", size 0x%" PRIx32
, bank
->base
, address
,
2175 return ERROR_FLASH_OPERATION_FAILED
;
2181 int cfi_write_word(struct flash_bank
*bank
, uint8_t *word
, uint32_t address
)
2183 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2185 switch (cfi_info
->pri_id
) {
2188 return cfi_intel_write_word(bank
, word
, address
);
2190 return cfi_spansion_write_word(bank
, word
, address
);
2192 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2196 return ERROR_FLASH_OPERATION_FAILED
;
2199 static int cfi_write_words(struct flash_bank
*bank
, const uint8_t *word
,
2200 uint32_t wordcount
, uint32_t address
)
2202 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2204 if (cfi_info
->buf_write_timeout_typ
== 0) {
2205 /* buffer writes are not supported */
2206 LOG_DEBUG("Buffer Writes Not Supported");
2207 return ERROR_FLASH_OPER_UNSUPPORTED
;
2210 switch (cfi_info
->pri_id
) {
2213 return cfi_intel_write_words(bank
, word
, wordcount
, address
);
2215 return cfi_spansion_write_words(bank
, word
, wordcount
, address
);
2217 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2221 return ERROR_FLASH_OPERATION_FAILED
;
2224 static int cfi_read(struct flash_bank
*bank
, uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2226 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2227 uint32_t address
= bank
->base
+ offset
;
2229 int align
; /* number of unaligned bytes */
2230 uint8_t current_word
[CFI_MAX_BUS_WIDTH
];
2233 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2234 (int)count
, (unsigned)offset
);
2236 if (bank
->target
->state
!= TARGET_HALTED
) {
2237 LOG_ERROR("Target not halted");
2238 return ERROR_TARGET_NOT_HALTED
;
2241 if (offset
+ count
> bank
->size
)
2242 return ERROR_FLASH_DST_OUT_OF_BANK
;
2244 if (cfi_info
->qry
[0] != 'Q')
2245 return ERROR_FLASH_BANK_NOT_PROBED
;
2247 /* start at the first byte of the first word (bus_width size) */
2248 read_p
= address
& ~(bank
->bus_width
- 1);
2249 align
= address
- read_p
;
2251 LOG_INFO("Fixup %d unaligned read head bytes", align
);
2253 /* read a complete word from flash */
2254 retval
= cfi_target_read_memory(bank
, read_p
, 1, current_word
);
2255 if (retval
!= ERROR_OK
)
2258 /* take only bytes we need */
2259 for (unsigned int i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2260 *buffer
++ = current_word
[i
];
2262 read_p
+= bank
->bus_width
;
2265 align
= count
/ bank
->bus_width
;
2267 retval
= cfi_target_read_memory(bank
, read_p
, align
, buffer
);
2268 if (retval
!= ERROR_OK
)
2271 read_p
+= align
* bank
->bus_width
;
2272 buffer
+= align
* bank
->bus_width
;
2273 count
-= align
* bank
->bus_width
;
2277 LOG_INFO("Fixup %" PRIu32
" unaligned read tail bytes", count
);
2279 /* read a complete word from flash */
2280 retval
= cfi_target_read_memory(bank
, read_p
, 1, current_word
);
2281 if (retval
!= ERROR_OK
)
2284 /* take only bytes we need */
2285 for (unsigned int i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2286 *buffer
++ = current_word
[i
];
2292 static int cfi_write(struct flash_bank
*bank
, const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
2294 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2295 uint32_t address
= bank
->base
+ offset
; /* address of first byte to be programmed */
2297 int align
; /* number of unaligned bytes */
2298 int blk_count
; /* number of bus_width bytes for block copy */
2299 uint8_t current_word
[CFI_MAX_BUS_WIDTH
* 4]; /* word (bus_width size) currently being
2301 uint8_t *swapped_buffer
= NULL
;
2302 const uint8_t *real_buffer
= NULL
;
2305 if (bank
->target
->state
!= TARGET_HALTED
) {
2306 LOG_ERROR("Target not halted");
2307 return ERROR_TARGET_NOT_HALTED
;
2310 if (offset
+ count
> bank
->size
)
2311 return ERROR_FLASH_DST_OUT_OF_BANK
;
2313 if (cfi_info
->qry
[0] != 'Q')
2314 return ERROR_FLASH_BANK_NOT_PROBED
;
2316 /* start at the first byte of the first word (bus_width size) */
2317 write_p
= address
& ~(bank
->bus_width
- 1);
2318 align
= address
- write_p
;
2320 LOG_INFO("Fixup %d unaligned head bytes", align
);
2322 /* read a complete word from flash */
2323 retval
= cfi_target_read_memory(bank
, write_p
, 1, current_word
);
2324 if (retval
!= ERROR_OK
)
2327 /* replace only bytes that must be written */
2328 for (unsigned int i
= align
; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2329 if (cfi_info
->data_swap
)
2330 /* data bytes are swapped (reverse endianness) */
2331 current_word
[bank
->bus_width
- i
] = *buffer
++;
2333 current_word
[i
] = *buffer
++;
2335 retval
= cfi_write_word(bank
, current_word
, write_p
);
2336 if (retval
!= ERROR_OK
)
2338 write_p
+= bank
->bus_width
;
2341 if (cfi_info
->data_swap
&& count
) {
2342 swapped_buffer
= malloc(count
& ~(bank
->bus_width
- 1));
2343 switch (bank
->bus_width
) {
2345 buf_bswap16(swapped_buffer
, buffer
,
2346 count
& ~(bank
->bus_width
- 1));
2349 buf_bswap32(swapped_buffer
, buffer
,
2350 count
& ~(bank
->bus_width
- 1));
2353 real_buffer
= buffer
;
2354 buffer
= swapped_buffer
;
2357 /* handle blocks of bus_size aligned bytes */
2358 blk_count
= count
& ~(bank
->bus_width
- 1); /* round down, leave tail bytes */
2359 switch (cfi_info
->pri_id
) {
2360 /* try block writes (fails without working area) */
2363 retval
= cfi_intel_write_block(bank
, buffer
, write_p
, blk_count
);
2366 retval
= cfi_spansion_write_block(bank
, buffer
, write_p
, blk_count
);
2369 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2370 retval
= ERROR_FLASH_OPERATION_FAILED
;
2373 if (retval
== ERROR_OK
) {
2374 /* Increment pointers and decrease count on successful block write */
2375 buffer
+= blk_count
;
2376 write_p
+= blk_count
;
2379 if (retval
== ERROR_TARGET_RESOURCE_NOT_AVAILABLE
) {
2380 /* Calculate buffer size and boundary mask
2381 * buffersize is (buffer size per chip) * (number of chips)
2382 * bufferwsize is buffersize in words */
2383 uint32_t buffersize
=
2385 cfi_info
->max_buf_write_size
) *
2386 (bank
->bus_width
/ bank
->chip_width
);
2387 uint32_t buffermask
= buffersize
-1;
2388 uint32_t bufferwsize
= buffersize
/ bank
->bus_width
;
2390 /* fall back to memory writes */
2391 while (count
>= (uint32_t)bank
->bus_width
) {
2393 if ((write_p
& 0xff) == 0) {
2394 LOG_INFO("Programming at 0x%08" PRIx32
", count 0x%08"
2395 PRIx32
" bytes remaining", write_p
, count
);
2398 if ((bufferwsize
> 0) && (count
>= buffersize
) &&
2399 !(write_p
& buffermask
)) {
2400 retval
= cfi_write_words(bank
, buffer
, bufferwsize
, write_p
);
2401 if (retval
== ERROR_OK
) {
2402 buffer
+= buffersize
;
2403 write_p
+= buffersize
;
2404 count
-= buffersize
;
2406 } else if (retval
!= ERROR_FLASH_OPER_UNSUPPORTED
)
2409 /* try the slow way? */
2411 for (unsigned int i
= 0; i
< bank
->bus_width
; i
++)
2412 current_word
[i
] = *buffer
++;
2414 retval
= cfi_write_word(bank
, current_word
, write_p
);
2415 if (retval
!= ERROR_OK
)
2418 write_p
+= bank
->bus_width
;
2419 count
-= bank
->bus_width
;
2426 if (swapped_buffer
) {
2427 buffer
= real_buffer
+ (buffer
- swapped_buffer
);
2428 free(swapped_buffer
);
2431 /* return to read array mode, so we can read from flash again for padding */
2432 retval
= cfi_reset(bank
);
2433 if (retval
!= ERROR_OK
)
2436 /* handle unaligned tail bytes */
2438 LOG_INFO("Fixup %" PRIu32
" unaligned tail bytes", count
);
2440 /* read a complete word from flash */
2441 retval
= cfi_target_read_memory(bank
, write_p
, 1, current_word
);
2442 if (retval
!= ERROR_OK
)
2445 /* replace only bytes that must be written */
2446 for (unsigned int i
= 0; (i
< bank
->bus_width
) && (count
> 0); i
++, count
--)
2447 if (cfi_info
->data_swap
)
2448 /* data bytes are swapped (reverse endianness) */
2449 current_word
[bank
->bus_width
- i
] = *buffer
++;
2451 current_word
[i
] = *buffer
++;
2453 retval
= cfi_write_word(bank
, current_word
, write_p
);
2454 if (retval
!= ERROR_OK
)
2458 /* return to read array mode */
2459 return cfi_reset(bank
);
2462 static void cfi_fixup_reversed_erase_regions(struct flash_bank
*bank
, const void *param
)
2465 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2466 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2468 pri_ext
->_reversed_geometry
= 1;
2471 static void cfi_fixup_0002_erase_regions(struct flash_bank
*bank
, const void *param
)
2473 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2474 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2477 if ((pri_ext
->_reversed_geometry
) || (pri_ext
->top_bottom
== 3)) {
2478 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2480 for (unsigned int i
= 0; i
< cfi_info
->num_erase_regions
/ 2; i
++) {
2481 int j
= (cfi_info
->num_erase_regions
- 1) - i
;
2484 swap
= cfi_info
->erase_region_info
[i
];
2485 cfi_info
->erase_region_info
[i
] = cfi_info
->erase_region_info
[j
];
2486 cfi_info
->erase_region_info
[j
] = swap
;
2491 static void cfi_fixup_0002_unlock_addresses(struct flash_bank
*bank
, const void *param
)
2493 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2494 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2495 const struct cfi_unlock_addresses
*unlock_addresses
= param
;
2497 pri_ext
->_unlock1
= unlock_addresses
->unlock1
;
2498 pri_ext
->_unlock2
= unlock_addresses
->unlock2
;
2501 static void cfi_fixup_0002_polling_bits(struct flash_bank
*bank
, const void *param
)
2503 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2504 const int *status_poll_mask
= param
;
2506 cfi_info
->status_poll_mask
= *status_poll_mask
;
2510 static int cfi_query_string(struct flash_bank
*bank
, int address
)
2512 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2515 retval
= cfi_send_command(bank
, 0x98, cfi_flash_address(bank
, 0, address
));
2516 if (retval
!= ERROR_OK
)
2519 retval
= cfi_query_u8(bank
, 0, 0x10, &cfi_info
->qry
[0]);
2520 if (retval
!= ERROR_OK
)
2522 retval
= cfi_query_u8(bank
, 0, 0x11, &cfi_info
->qry
[1]);
2523 if (retval
!= ERROR_OK
)
2525 retval
= cfi_query_u8(bank
, 0, 0x12, &cfi_info
->qry
[2]);
2526 if (retval
!= ERROR_OK
)
2529 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
2530 cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2]);
2532 if ((cfi_info
->qry
[0] != 'Q') || (cfi_info
->qry
[1] != 'R') || (cfi_info
->qry
[2] != 'Y')) {
2533 retval
= cfi_reset(bank
);
2534 if (retval
!= ERROR_OK
)
2536 LOG_ERROR("Could not probe bank: no QRY");
2537 return ERROR_FLASH_BANK_INVALID
;
2543 int cfi_probe(struct flash_bank
*bank
)
2545 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2546 struct target
*target
= bank
->target
;
2547 unsigned int num_sectors
= 0;
2549 uint32_t unlock1
= 0x555;
2550 uint32_t unlock2
= 0x2aa;
2552 uint8_t value_buf0
[CFI_MAX_BUS_WIDTH
], value_buf1
[CFI_MAX_BUS_WIDTH
];
2554 if (bank
->target
->state
!= TARGET_HALTED
) {
2555 LOG_ERROR("Target not halted");
2556 return ERROR_TARGET_NOT_HALTED
;
2559 cfi_info
->probed
= false;
2560 cfi_info
->num_erase_regions
= 0;
2562 free(bank
->sectors
);
2563 bank
->sectors
= NULL
;
2565 free(cfi_info
->erase_region_info
);
2566 cfi_info
->erase_region_info
= NULL
;
2568 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2569 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2571 if (cfi_info
->jedec_probe
) {
2576 /* switch to read identifier codes mode ("AUTOSELECT") */
2577 retval
= cfi_send_command(bank
, 0xaa, cfi_flash_address(bank
, 0, unlock1
));
2578 if (retval
!= ERROR_OK
)
2580 retval
= cfi_send_command(bank
, 0x55, cfi_flash_address(bank
, 0, unlock2
));
2581 if (retval
!= ERROR_OK
)
2583 retval
= cfi_send_command(bank
, 0x90, cfi_flash_address(bank
, 0, unlock1
));
2584 if (retval
!= ERROR_OK
)
2587 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, 0, 0x00),
2589 if (retval
!= ERROR_OK
)
2591 retval
= cfi_target_read_memory(bank
, cfi_flash_address(bank
, 0, 0x01),
2593 if (retval
!= ERROR_OK
)
2595 switch (bank
->chip_width
) {
2597 cfi_info
->manufacturer
= *value_buf0
;
2598 cfi_info
->device_id
= *value_buf1
;
2601 cfi_info
->manufacturer
= target_buffer_get_u16(target
, value_buf0
);
2602 cfi_info
->device_id
= target_buffer_get_u16(target
, value_buf1
);
2605 cfi_info
->manufacturer
= target_buffer_get_u32(target
, value_buf0
);
2606 cfi_info
->device_id
= target_buffer_get_u32(target
, value_buf1
);
2609 LOG_ERROR("Unsupported bank chipwidth %u, can't probe memory",
2611 return ERROR_FLASH_OPERATION_FAILED
;
2614 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
2615 cfi_info
->manufacturer
, cfi_info
->device_id
);
2616 /* switch back to read array mode */
2617 retval
= cfi_reset(bank
);
2618 if (retval
!= ERROR_OK
)
2621 /* check device/manufacturer ID for known non-CFI flashes. */
2622 cfi_fixup_non_cfi(bank
);
2624 /* query only if this is a CFI compatible flash,
2625 * otherwise the relevant info has already been filled in
2627 if (!cfi_info
->not_cfi
) {
2628 /* enter CFI query mode
2629 * according to JEDEC Standard No. 68.01,
2630 * a single bus sequence with address = 0x55, data = 0x98 should put
2631 * the device into CFI query mode.
2633 * SST flashes clearly violate this, and we will consider them incompatible for now
2636 retval
= cfi_query_string(bank
, 0x55);
2637 if (retval
!= ERROR_OK
) {
2639 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2640 * be harmless enough:
2642 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2644 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2645 retval
= cfi_query_string(bank
, 0x555);
2647 if (retval
!= ERROR_OK
)
2650 retval
= cfi_query_u16(bank
, 0, 0x13, &cfi_info
->pri_id
);
2651 if (retval
!= ERROR_OK
)
2653 retval
= cfi_query_u16(bank
, 0, 0x15, &cfi_info
->pri_addr
);
2654 if (retval
!= ERROR_OK
)
2656 retval
= cfi_query_u16(bank
, 0, 0x17, &cfi_info
->alt_id
);
2657 if (retval
!= ERROR_OK
)
2659 retval
= cfi_query_u16(bank
, 0, 0x19, &cfi_info
->alt_addr
);
2660 if (retval
!= ERROR_OK
)
2663 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
2664 "0x%4.4x, alt_addr: 0x%4.4x", cfi_info
->qry
[0], cfi_info
->qry
[1],
2665 cfi_info
->qry
[2], cfi_info
->pri_id
, cfi_info
->pri_addr
,
2666 cfi_info
->alt_id
, cfi_info
->alt_addr
);
2668 retval
= cfi_query_u8(bank
, 0, 0x1b, &cfi_info
->vcc_min
);
2669 if (retval
!= ERROR_OK
)
2671 retval
= cfi_query_u8(bank
, 0, 0x1c, &cfi_info
->vcc_max
);
2672 if (retval
!= ERROR_OK
)
2674 retval
= cfi_query_u8(bank
, 0, 0x1d, &cfi_info
->vpp_min
);
2675 if (retval
!= ERROR_OK
)
2677 retval
= cfi_query_u8(bank
, 0, 0x1e, &cfi_info
->vpp_max
);
2678 if (retval
!= ERROR_OK
)
2681 retval
= cfi_query_u8(bank
, 0, 0x1f, &cfi_info
->word_write_timeout_typ
);
2682 if (retval
!= ERROR_OK
)
2684 retval
= cfi_query_u8(bank
, 0, 0x20, &cfi_info
->buf_write_timeout_typ
);
2685 if (retval
!= ERROR_OK
)
2687 retval
= cfi_query_u8(bank
, 0, 0x21, &cfi_info
->block_erase_timeout_typ
);
2688 if (retval
!= ERROR_OK
)
2690 retval
= cfi_query_u8(bank
, 0, 0x22, &cfi_info
->chip_erase_timeout_typ
);
2691 if (retval
!= ERROR_OK
)
2693 retval
= cfi_query_u8(bank
, 0, 0x23, &cfi_info
->word_write_timeout_max
);
2694 if (retval
!= ERROR_OK
)
2696 retval
= cfi_query_u8(bank
, 0, 0x24, &cfi_info
->buf_write_timeout_max
);
2697 if (retval
!= ERROR_OK
)
2699 retval
= cfi_query_u8(bank
, 0, 0x25, &cfi_info
->block_erase_timeout_max
);
2700 if (retval
!= ERROR_OK
)
2702 retval
= cfi_query_u8(bank
, 0, 0x26, &cfi_info
->chip_erase_timeout_max
);
2703 if (retval
!= ERROR_OK
)
2707 retval
= cfi_query_u8(bank
, 0, 0x27, &data
);
2708 if (retval
!= ERROR_OK
)
2710 cfi_info
->dev_size
= 1 << data
;
2712 retval
= cfi_query_u16(bank
, 0, 0x28, &cfi_info
->interface_desc
);
2713 if (retval
!= ERROR_OK
)
2715 retval
= cfi_query_u16(bank
, 0, 0x2a, &cfi_info
->max_buf_write_size
);
2716 if (retval
!= ERROR_OK
)
2718 retval
= cfi_query_u8(bank
, 0, 0x2c, &cfi_info
->num_erase_regions
);
2719 if (retval
!= ERROR_OK
)
2722 LOG_DEBUG("size: 0x%" PRIx32
", interface desc: %i, max buffer write size: 0x%x",
2723 cfi_info
->dev_size
, cfi_info
->interface_desc
,
2724 (1 << cfi_info
->max_buf_write_size
));
2726 if (cfi_info
->num_erase_regions
) {
2727 cfi_info
->erase_region_info
= malloc(sizeof(*cfi_info
->erase_region_info
)
2728 * cfi_info
->num_erase_regions
);
2729 for (unsigned int i
= 0; i
< cfi_info
->num_erase_regions
; i
++) {
2730 retval
= cfi_query_u32(bank
,
2733 &cfi_info
->erase_region_info
[i
]);
2734 if (retval
!= ERROR_OK
)
2737 "erase region[%i]: %" PRIu32
" blocks of size 0x%" PRIx32
"",
2739 (cfi_info
->erase_region_info
[i
] & 0xffff) + 1,
2740 (cfi_info
->erase_region_info
[i
] >> 16) * 256);
2743 cfi_info
->erase_region_info
= NULL
;
2745 /* We need to read the primary algorithm extended query table before calculating
2746 * the sector layout to be able to apply fixups
2748 switch (cfi_info
->pri_id
) {
2749 /* Intel command set (standard and extended) */
2752 cfi_read_intel_pri_ext(bank
);
2754 /* AMD/Spansion, Atmel, ... command set */
2756 cfi_info
->status_poll_mask
= CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7
; /*
2763 cfi_read_0002_pri_ext(bank
);
2766 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2770 /* return to read array mode
2771 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2773 retval
= cfi_reset(bank
);
2774 if (retval
!= ERROR_OK
)
2776 } /* end CFI case */
2778 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2779 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2780 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2781 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2782 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2784 LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
2785 "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
2786 1 << cfi_info
->word_write_timeout_typ
, 1 << cfi_info
->buf_write_timeout_typ
,
2787 1 << cfi_info
->block_erase_timeout_typ
, 1 << cfi_info
->chip_erase_timeout_typ
);
2789 LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
2790 "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
2791 (1 << cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
2792 (1 << cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
2793 (1 << cfi_info
->block_erase_timeout_max
) * (1 << cfi_info
->block_erase_timeout_typ
),
2794 (1 << cfi_info
->chip_erase_timeout_max
) * (1 << cfi_info
->chip_erase_timeout_typ
));
2796 /* convert timeouts to real values in ms */
2797 cfi_info
->word_write_timeout
= DIV_ROUND_UP((1L << cfi_info
->word_write_timeout_typ
) *
2798 (1L << cfi_info
->word_write_timeout_max
), 1000);
2799 cfi_info
->buf_write_timeout
= DIV_ROUND_UP((1L << cfi_info
->buf_write_timeout_typ
) *
2800 (1L << cfi_info
->buf_write_timeout_max
), 1000);
2801 cfi_info
->block_erase_timeout
= (1L << cfi_info
->block_erase_timeout_typ
) *
2802 (1L << cfi_info
->block_erase_timeout_max
);
2803 cfi_info
->chip_erase_timeout
= (1L << cfi_info
->chip_erase_timeout_typ
) *
2804 (1L << cfi_info
->chip_erase_timeout_max
);
2806 LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
2807 "block erase timeout: %u ms, chip erase timeout: %u ms",
2808 cfi_info
->word_write_timeout
, cfi_info
->buf_write_timeout
,
2809 cfi_info
->block_erase_timeout
, cfi_info
->chip_erase_timeout
);
2811 /* apply fixups depending on the primary command set */
2812 switch (cfi_info
->pri_id
) {
2813 /* Intel command set (standard and extended) */
2816 cfi_fixup(bank
, cfi_0001_fixups
);
2818 /* AMD/Spansion, Atmel, ... command set */
2820 cfi_fixup(bank
, cfi_0002_fixups
);
2823 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2827 if ((cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
) != bank
->size
) {
2828 LOG_WARNING("configuration specifies 0x%" PRIx32
" size, but a 0x%" PRIx32
2829 " size flash was found", bank
->size
, cfi_info
->dev_size
);
2832 if (cfi_info
->num_erase_regions
== 0) {
2833 /* a device might have only one erase block, spanning the whole device */
2834 bank
->num_sectors
= 1;
2835 bank
->sectors
= malloc(sizeof(struct flash_sector
));
2837 bank
->sectors
[sector
].offset
= 0x0;
2838 bank
->sectors
[sector
].size
= bank
->size
;
2839 bank
->sectors
[sector
].is_erased
= -1;
2840 bank
->sectors
[sector
].is_protected
= -1;
2842 uint32_t offset
= 0;
2844 for (unsigned int i
= 0; i
< cfi_info
->num_erase_regions
; i
++)
2845 num_sectors
+= (cfi_info
->erase_region_info
[i
] & 0xffff) + 1;
2847 bank
->num_sectors
= num_sectors
;
2848 bank
->sectors
= malloc(sizeof(struct flash_sector
) * num_sectors
);
2850 for (unsigned int i
= 0; i
< cfi_info
->num_erase_regions
; i
++) {
2851 for (uint32_t j
= 0; j
< (cfi_info
->erase_region_info
[i
] & 0xffff) + 1; j
++) {
2852 bank
->sectors
[sector
].offset
= offset
;
2853 bank
->sectors
[sector
].size
=
2854 ((cfi_info
->erase_region_info
[i
] >> 16) * 256)
2855 * bank
->bus_width
/ bank
->chip_width
;
2856 offset
+= bank
->sectors
[sector
].size
;
2857 bank
->sectors
[sector
].is_erased
= -1;
2858 bank
->sectors
[sector
].is_protected
= -1;
2862 if (offset
!= (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
)) {
2864 "CFI size is 0x%" PRIx32
", but total sector size is 0x%" PRIx32
"",
2865 (cfi_info
->dev_size
* bank
->bus_width
/ bank
->chip_width
),
2870 cfi_info
->probed
= true;
2875 int cfi_auto_probe(struct flash_bank
*bank
)
2877 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2878 if (cfi_info
->probed
)
2880 return cfi_probe(bank
);
2883 static int cfi_intel_protect_check(struct flash_bank
*bank
)
2886 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2887 struct cfi_intel_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2889 /* check if block lock bits are supported on this device */
2890 if (!(pri_ext
->blk_status_reg_mask
& 0x1))
2891 return ERROR_FLASH_OPERATION_FAILED
;
2893 retval
= cfi_send_command(bank
, 0x90, cfi_flash_address(bank
, 0, 0x55));
2894 if (retval
!= ERROR_OK
)
2897 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
2898 uint8_t block_status
;
2899 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2900 if (retval
!= ERROR_OK
)
2903 if (block_status
& 1)
2904 bank
->sectors
[i
].is_protected
= 1;
2906 bank
->sectors
[i
].is_protected
= 0;
2909 return cfi_send_command(bank
, 0xff, cfi_flash_address(bank
, 0, 0x0));
2912 static int cfi_spansion_protect_check(struct flash_bank
*bank
)
2915 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2916 struct cfi_spansion_pri_ext
*pri_ext
= cfi_info
->pri_ext
;
2918 retval
= cfi_spansion_unlock_seq(bank
);
2919 if (retval
!= ERROR_OK
)
2922 retval
= cfi_send_command(bank
, 0x90, cfi_flash_address(bank
, 0, pri_ext
->_unlock1
));
2923 if (retval
!= ERROR_OK
)
2926 for (unsigned int i
= 0; i
< bank
->num_sectors
; i
++) {
2927 uint8_t block_status
;
2928 retval
= cfi_get_u8(bank
, i
, 0x2, &block_status
);
2929 if (retval
!= ERROR_OK
)
2932 if (block_status
& 1)
2933 bank
->sectors
[i
].is_protected
= 1;
2935 bank
->sectors
[i
].is_protected
= 0;
2938 return cfi_send_command(bank
, 0xf0, cfi_flash_address(bank
, 0, 0x0));
2941 int cfi_protect_check(struct flash_bank
*bank
)
2943 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2945 if (bank
->target
->state
!= TARGET_HALTED
) {
2946 LOG_ERROR("Target not halted");
2947 return ERROR_TARGET_NOT_HALTED
;
2950 if (cfi_info
->qry
[0] != 'Q')
2951 return ERROR_FLASH_BANK_NOT_PROBED
;
2953 switch (cfi_info
->pri_id
) {
2956 return cfi_intel_protect_check(bank
);
2958 return cfi_spansion_protect_check(bank
);
2960 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
2967 int cfi_get_info(struct flash_bank
*bank
, struct command_invocation
*cmd
)
2969 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
2971 if (cfi_info
->qry
[0] == 0xff) {
2972 command_print_sameline(cmd
, "\ncfi flash bank not probed yet\n");
2976 if (!cfi_info
->not_cfi
)
2977 command_print_sameline(cmd
, "\nCFI flash: ");
2979 command_print_sameline(cmd
, "\nnon-CFI flash: ");
2981 command_print_sameline(cmd
, "mfr: 0x%4.4x, id:0x%4.4x\n",
2982 cfi_info
->manufacturer
, cfi_info
->device_id
);
2984 command_print_sameline(cmd
, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
2985 "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
2986 cfi_info
->qry
[0], cfi_info
->qry
[1], cfi_info
->qry
[2],
2987 cfi_info
->pri_id
, cfi_info
->pri_addr
, cfi_info
->alt_id
, cfi_info
->alt_addr
);
2989 command_print_sameline(cmd
, "Vcc min: %x.%x, Vcc max: %x.%x, "
2990 "Vpp min: %u.%x, Vpp max: %u.%x\n",
2991 (cfi_info
->vcc_min
& 0xf0) >> 4, cfi_info
->vcc_min
& 0x0f,
2992 (cfi_info
->vcc_max
& 0xf0) >> 4, cfi_info
->vcc_max
& 0x0f,
2993 (cfi_info
->vpp_min
& 0xf0) >> 4, cfi_info
->vpp_min
& 0x0f,
2994 (cfi_info
->vpp_max
& 0xf0) >> 4, cfi_info
->vpp_max
& 0x0f);
2996 command_print_sameline(cmd
, "typ. word write timeout: %u us, "
2997 "typ. buf write timeout: %u us, "
2998 "typ. block erase timeout: %u ms, "
2999 "typ. chip erase timeout: %u ms\n",
3000 1 << cfi_info
->word_write_timeout_typ
,
3001 1 << cfi_info
->buf_write_timeout_typ
,
3002 1 << cfi_info
->block_erase_timeout_typ
,
3003 1 << cfi_info
->chip_erase_timeout_typ
);
3005 command_print_sameline(cmd
, "max. word write timeout: %u us, "
3006 "max. buf write timeout: %u us, max. "
3007 "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
3009 cfi_info
->word_write_timeout_max
) * (1 << cfi_info
->word_write_timeout_typ
),
3011 cfi_info
->buf_write_timeout_max
) * (1 << cfi_info
->buf_write_timeout_typ
),
3013 cfi_info
->block_erase_timeout_max
) *
3014 (1 << cfi_info
->block_erase_timeout_typ
),
3016 cfi_info
->chip_erase_timeout_max
) *
3017 (1 << cfi_info
->chip_erase_timeout_typ
));
3019 command_print_sameline(cmd
, "size: 0x%" PRIx32
", interface desc: %i, "
3020 "max buffer write size: 0x%x\n",
3022 cfi_info
->interface_desc
,
3023 1 << cfi_info
->max_buf_write_size
);
3025 switch (cfi_info
->pri_id
) {
3028 cfi_intel_info(bank
, cmd
);
3031 cfi_spansion_info(bank
, cmd
);
3034 LOG_ERROR("cfi primary command set %i unsupported", cfi_info
->pri_id
);
3041 static void cfi_fixup_0002_write_buffer(struct flash_bank
*bank
, const void *param
)
3043 struct cfi_flash_bank
*cfi_info
= bank
->driver_priv
;
3045 /* disable write buffer for M29W128G */
3046 cfi_info
->buf_write_timeout_typ
= 0;
3049 const struct flash_driver cfi_flash
= {
3051 .flash_bank_command
= cfi_flash_bank_command
,
3053 .protect
= cfi_protect
,
3057 .auto_probe
= cfi_auto_probe
,
3058 /* FIXME: access flash at bus_width size */
3059 .erase_check
= default_flash_blank_check
,
3060 .protect_check
= cfi_protect_check
,
3061 .info
= cfi_get_info
,
3062 .free_driver_priv
= default_flash_free_driver_priv
,