1 /***************************************************************************
2 * Copyright (C) 2013 Synapse Product Development *
3 * Andrey Smirnov <andrew.smironv@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
28 NRF51_FLASH_BASE
= 0x00000000,
31 enum nrf51_ficr_registers
{
32 NRF51_FICR_BASE
= 0x10000000, /* Factory Information Configuration Registers */
34 #define NRF51_FICR_REG(offset) (NRF51_FICR_BASE + offset)
36 NRF51_FICR_CODEPAGESIZE
= NRF51_FICR_REG(0x010),
37 NRF51_FICR_CODESIZE
= NRF51_FICR_REG(0x014),
38 NRF51_FICR_CLENR0
= NRF51_FICR_REG(0x028),
39 NRF51_FICR_PPFC
= NRF51_FICR_REG(0x02C),
40 NRF51_FICR_NUMRAMBLOCK
= NRF51_FICR_REG(0x034),
41 NRF51_FICR_SIZERAMBLOCK0
= NRF51_FICR_REG(0x038),
42 NRF51_FICR_SIZERAMBLOCK1
= NRF51_FICR_REG(0x03C),
43 NRF51_FICR_SIZERAMBLOCK2
= NRF51_FICR_REG(0x040),
44 NRF51_FICR_SIZERAMBLOCK3
= NRF51_FICR_REG(0x044),
45 NRF51_FICR_CONFIGID
= NRF51_FICR_REG(0x05C),
46 NRF51_FICR_DEVICEID0
= NRF51_FICR_REG(0x060),
47 NRF51_FICR_DEVICEID1
= NRF51_FICR_REG(0x064),
48 NRF51_FICR_ER0
= NRF51_FICR_REG(0x080),
49 NRF51_FICR_ER1
= NRF51_FICR_REG(0x084),
50 NRF51_FICR_ER2
= NRF51_FICR_REG(0x088),
51 NRF51_FICR_ER3
= NRF51_FICR_REG(0x08C),
52 NRF51_FICR_IR0
= NRF51_FICR_REG(0x090),
53 NRF51_FICR_IR1
= NRF51_FICR_REG(0x094),
54 NRF51_FICR_IR2
= NRF51_FICR_REG(0x098),
55 NRF51_FICR_IR3
= NRF51_FICR_REG(0x09C),
56 NRF51_FICR_DEVICEADDRTYPE
= NRF51_FICR_REG(0x0A0),
57 NRF51_FICR_DEVICEADDR0
= NRF51_FICR_REG(0x0A4),
58 NRF51_FICR_DEVICEADDR1
= NRF51_FICR_REG(0x0A8),
59 NRF51_FICR_OVERRIDEN
= NRF51_FICR_REG(0x0AC),
60 NRF51_FICR_NRF_1MBIT0
= NRF51_FICR_REG(0x0B0),
61 NRF51_FICR_NRF_1MBIT1
= NRF51_FICR_REG(0x0B4),
62 NRF51_FICR_NRF_1MBIT2
= NRF51_FICR_REG(0x0B8),
63 NRF51_FICR_NRF_1MBIT3
= NRF51_FICR_REG(0x0BC),
64 NRF51_FICR_NRF_1MBIT4
= NRF51_FICR_REG(0x0C0),
65 NRF51_FICR_BLE_1MBIT0
= NRF51_FICR_REG(0x0EC),
66 NRF51_FICR_BLE_1MBIT1
= NRF51_FICR_REG(0x0F0),
67 NRF51_FICR_BLE_1MBIT2
= NRF51_FICR_REG(0x0F4),
68 NRF51_FICR_BLE_1MBIT3
= NRF51_FICR_REG(0x0F8),
69 NRF51_FICR_BLE_1MBIT4
= NRF51_FICR_REG(0x0FC),
72 enum nrf51_uicr_registers
{
73 NRF51_UICR_BASE
= 0x10001000, /* User Information
74 * Configuration Regsters */
76 NRF51_UICR_SIZE
= 0x100,
78 #define NRF51_UICR_REG(offset) (NRF51_UICR_BASE + offset)
80 NRF51_UICR_CLENR0
= NRF51_UICR_REG(0x000),
81 NRF51_UICR_RBPCONF
= NRF51_UICR_REG(0x004),
82 NRF51_UICR_XTALFREQ
= NRF51_UICR_REG(0x008),
83 NRF51_UICR_FWID
= NRF51_UICR_REG(0x010),
86 enum nrf51_nvmc_registers
{
87 NRF51_NVMC_BASE
= 0x4001E000, /* Non-Volatile Memory
88 * Controller Regsters */
90 #define NRF51_NVMC_REG(offset) (NRF51_NVMC_BASE + offset)
92 NRF51_NVMC_READY
= NRF51_NVMC_REG(0x400),
93 NRF51_NVMC_CONFIG
= NRF51_NVMC_REG(0x504),
94 NRF51_NVMC_ERASEPAGE
= NRF51_NVMC_REG(0x508),
95 NRF51_NVMC_ERASEALL
= NRF51_NVMC_REG(0x50C),
96 NRF51_NVMC_ERASEUICR
= NRF51_NVMC_REG(0x514),
99 enum nrf51_nvmc_config_bits
{
100 NRF51_NVMC_CONFIG_REN
= 0x00,
101 NRF51_NVMC_CONFIG_WEN
= 0x01,
102 NRF51_NVMC_CONFIG_EEN
= 0x02,
107 uint32_t code_page_size
;
108 uint32_t code_memory_size
;
112 int (*write
) (struct flash_bank
*bank
,
113 struct nrf51_info
*chip
,
114 const uint8_t *buffer
, uint32_t offset
, uint32_t count
);
116 struct target
*target
;
119 struct nrf51_device_spec
{
122 const char *build_code
;
123 unsigned int flash_size_kb
;
126 static const struct nrf51_device_spec nrf51_known_devices_table
[] = {
130 .build_code
= "CA/C0",
131 .flash_size_kb
= 256,
137 .flash_size_kb
= 256,
143 .flash_size_kb
= 256,
149 .flash_size_kb
= 256,
156 .flash_size_kb
= 256,
162 .flash_size_kb
= 256,
168 .flash_size_kb
= 256,
174 .flash_size_kb
= 256,
180 .flash_size_kb
= 256,
187 .flash_size_kb
= 128,
193 .flash_size_kb
= 128,
199 .flash_size_kb
= 128,
204 static int nrf51_bank_is_probed(struct flash_bank
*bank
)
206 struct nrf51_info
*chip
= bank
->driver_priv
;
208 assert(chip
!= NULL
);
210 return chip
->bank
[bank
->bank_number
].probed
;
212 static int nrf51_probe(struct flash_bank
*bank
);
214 static int nrf51_get_probed_chip_if_halted(struct flash_bank
*bank
, struct nrf51_info
**chip
)
216 if (bank
->target
->state
!= TARGET_HALTED
) {
217 LOG_ERROR("Target not halted");
218 return ERROR_TARGET_NOT_HALTED
;
221 *chip
= bank
->driver_priv
;
223 int probed
= nrf51_bank_is_probed(bank
);
227 return nrf51_probe(bank
);
232 static int nrf51_wait_for_nvmc(struct nrf51_info
*chip
)
239 res
= target_read_u32(chip
->target
, NRF51_NVMC_READY
, &ready
);
240 if (res
!= ERROR_OK
) {
241 LOG_ERROR("Couldn't read NVMC_READY register");
245 if (ready
== 0x00000001)
251 return ERROR_FLASH_BUSY
;
254 static int nrf51_nvmc_erase_enable(struct nrf51_info
*chip
)
257 res
= target_write_u32(chip
->target
,
259 NRF51_NVMC_CONFIG_EEN
);
261 if (res
!= ERROR_OK
) {
262 LOG_ERROR("Failed to enable erase operation");
267 According to NVMC examples in Nordic SDK busy status must be
268 checked after writing to NVMC_CONFIG
270 res
= nrf51_wait_for_nvmc(chip
);
272 LOG_ERROR("Erase enable did not complete");
277 static int nrf51_nvmc_write_enable(struct nrf51_info
*chip
)
280 res
= target_write_u32(chip
->target
,
282 NRF51_NVMC_CONFIG_WEN
);
284 if (res
!= ERROR_OK
) {
285 LOG_ERROR("Failed to enable write operation");
290 According to NVMC examples in Nordic SDK busy status must be
291 checked after writing to NVMC_CONFIG
293 res
= nrf51_wait_for_nvmc(chip
);
295 LOG_ERROR("Write enable did not complete");
300 static int nrf51_nvmc_read_only(struct nrf51_info
*chip
)
303 res
= target_write_u32(chip
->target
,
305 NRF51_NVMC_CONFIG_REN
);
307 if (res
!= ERROR_OK
) {
308 LOG_ERROR("Failed to enable read-only operation");
312 According to NVMC examples in Nordic SDK busy status must be
313 checked after writing to NVMC_CONFIG
315 res
= nrf51_wait_for_nvmc(chip
);
317 LOG_ERROR("Read only enable did not complete");
322 static int nrf51_nvmc_generic_erase(struct nrf51_info
*chip
,
323 uint32_t erase_register
, uint32_t erase_value
)
327 res
= nrf51_nvmc_erase_enable(chip
);
331 res
= target_write_u32(chip
->target
,
337 res
= nrf51_wait_for_nvmc(chip
);
341 return nrf51_nvmc_read_only(chip
);
344 nrf51_nvmc_read_only(chip
);
346 LOG_ERROR("Failed to erase reg: 0x%08"PRIx32
" val: 0x%08"PRIx32
,
347 erase_register
, erase_value
);
351 static int nrf51_protect_check(struct flash_bank
*bank
)
356 /* UICR cannot be write protected so just return early */
357 if (bank
->base
== NRF51_UICR_BASE
)
360 struct nrf51_info
*chip
= bank
->driver_priv
;
362 assert(chip
!= NULL
);
364 res
= target_read_u32(chip
->target
, NRF51_FICR_CLENR0
,
366 if (res
!= ERROR_OK
) {
367 LOG_ERROR("Couldn't read code region 0 size[FICR]");
371 if (clenr0
== 0xFFFFFFFF) {
372 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
374 if (res
!= ERROR_OK
) {
375 LOG_ERROR("Couldn't read code region 0 size[UICR]");
380 for (int i
= 0; i
< bank
->num_sectors
; i
++)
381 bank
->sectors
[i
].is_protected
=
382 clenr0
!= 0xFFFFFFFF && bank
->sectors
[i
].offset
< clenr0
;
387 static int nrf51_protect(struct flash_bank
*bank
, int set
, int first
, int last
)
390 uint32_t clenr0
, ppfc
;
391 struct nrf51_info
*chip
;
393 /* UICR cannot be write protected so just bail out early */
394 if (bank
->base
== NRF51_UICR_BASE
)
397 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
402 LOG_ERROR("Code region 0 must start at the begining of the bank");
406 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
408 if (res
!= ERROR_OK
) {
409 LOG_ERROR("Couldn't read PPFC register");
413 if ((ppfc
& 0xFF) == 0x00) {
414 LOG_ERROR("Code region 0 size was pre-programmed at the factory, can't change flash protection settings");
418 res
= target_read_u32(chip
->target
, NRF51_UICR_CLENR0
,
420 if (res
!= ERROR_OK
) {
421 LOG_ERROR("Couldn't read code region 0 size[UICR]");
425 if (clenr0
== 0xFFFFFFFF) {
426 res
= target_write_u32(chip
->target
, NRF51_UICR_CLENR0
,
428 if (res
!= ERROR_OK
) {
429 LOG_ERROR("Couldn't write code region 0 size[UICR]");
434 LOG_ERROR("You need to perform chip erase before changing the protection settings");
437 nrf51_protect_check(bank
);
442 static int nrf51_probe(struct flash_bank
*bank
)
446 struct nrf51_info
*chip
= bank
->driver_priv
;
448 res
= target_read_u32(chip
->target
, NRF51_FICR_CONFIGID
, &hwid
);
449 if (res
!= ERROR_OK
) {
450 LOG_ERROR("Couldn't read CONFIGID register");
454 hwid
&= 0xFFFF; /* HWID is stored in the lower two
455 * bytes of the CONFIGID register */
457 const struct nrf51_device_spec
*spec
= NULL
;
458 for (size_t i
= 0; i
< ARRAY_SIZE(nrf51_known_devices_table
); i
++)
459 if (hwid
== nrf51_known_devices_table
[i
].hwid
) {
460 spec
= &nrf51_known_devices_table
[i
];
464 if (!chip
->bank
[0].probed
&& !chip
->bank
[1].probed
) {
466 LOG_INFO("nRF51822-%s(build code: %s) %ukB Flash",
467 spec
->variant
, spec
->build_code
, spec
->flash_size_kb
);
469 LOG_WARNING("Unknown device (HWID 0x%08" PRIx32
")", hwid
);
473 if (bank
->base
== NRF51_FLASH_BASE
) {
474 res
= target_read_u32(chip
->target
, NRF51_FICR_CODEPAGESIZE
,
475 &chip
->code_page_size
);
476 if (res
!= ERROR_OK
) {
477 LOG_ERROR("Couldn't read code page size");
481 res
= target_read_u32(chip
->target
, NRF51_FICR_CODESIZE
,
482 &chip
->code_memory_size
);
483 if (res
!= ERROR_OK
) {
484 LOG_ERROR("Couldn't read code memory size");
488 if (spec
&& chip
->code_memory_size
!= spec
->flash_size_kb
) {
489 LOG_ERROR("Chip's reported Flash capacity does not match expected one");
493 bank
->size
= chip
->code_memory_size
* 1024;
494 bank
->num_sectors
= bank
->size
/ chip
->code_page_size
;
495 bank
->sectors
= calloc(bank
->num_sectors
,
496 sizeof((bank
->sectors
)[0]));
498 return ERROR_FLASH_BANK_NOT_PROBED
;
500 /* Fill out the sector information: all NRF51 sectors are the same size and
501 * there is always a fixed number of them. */
502 for (int i
= 0; i
< bank
->num_sectors
; i
++) {
503 bank
->sectors
[i
].size
= chip
->code_page_size
;
504 bank
->sectors
[i
].offset
= i
* chip
->code_page_size
;
506 /* mark as unknown */
507 bank
->sectors
[i
].is_erased
= -1;
508 bank
->sectors
[i
].is_protected
= -1;
511 nrf51_protect_check(bank
);
513 chip
->bank
[0].probed
= true;
515 bank
->size
= NRF51_UICR_SIZE
;
516 bank
->num_sectors
= 1;
517 bank
->sectors
= calloc(bank
->num_sectors
,
518 sizeof((bank
->sectors
)[0]));
520 return ERROR_FLASH_BANK_NOT_PROBED
;
522 bank
->sectors
[0].size
= bank
->size
;
523 bank
->sectors
[0].offset
= 0;
525 /* mark as unknown */
526 bank
->sectors
[0].is_erased
= 0;
527 bank
->sectors
[0].is_protected
= 0;
529 chip
->bank
[1].probed
= true;
535 static int nrf51_auto_probe(struct flash_bank
*bank
)
537 int probed
= nrf51_bank_is_probed(bank
);
544 return nrf51_probe(bank
);
547 static struct flash_sector
*nrf51_find_sector_by_address(struct flash_bank
*bank
, uint32_t address
)
549 struct nrf51_info
*chip
= bank
->driver_priv
;
551 for (int i
= 0; i
< bank
->num_sectors
; i
++)
552 if (bank
->sectors
[i
].offset
<= address
&&
553 address
< (bank
->sectors
[i
].offset
+ chip
->code_page_size
))
554 return &bank
->sectors
[i
];
558 static int nrf51_erase_all(struct nrf51_info
*chip
)
560 return nrf51_nvmc_generic_erase(chip
,
565 static int nrf51_erase_page(struct nrf51_info
*chip
, struct flash_sector
*sector
)
569 if (sector
->is_protected
)
572 if (sector
->offset
== NRF51_UICR_BASE
) {
574 res
= target_read_u32(chip
->target
, NRF51_FICR_PPFC
,
576 if (res
!= ERROR_OK
) {
577 LOG_ERROR("Couldn't read PPFC register");
581 if ((ppfc
& 0xFF) == 0xFF) {
582 LOG_ERROR("The chip was not pre-programmed with SoftDevice stack and UICR cannot be erased separately. Please issue mass erase before trying to write to this region");
586 res
= nrf51_nvmc_generic_erase(chip
,
587 NRF51_NVMC_ERASEUICR
,
592 res
= nrf51_nvmc_generic_erase(chip
,
593 NRF51_NVMC_ERASEPAGE
,
598 sector
->is_erased
= 1;
603 static int nrf51_ll_flash_write(struct nrf51_info
*chip
, uint32_t offset
, const uint8_t *buffer
, uint32_t buffer_size
)
606 assert(buffer_size
% 4 == 0);
608 for (; buffer_size
> 0; buffer_size
-= 4) {
609 res
= target_write_memory(chip
->target
, offset
, 4, 1, buffer
);
613 res
= nrf51_wait_for_nvmc(chip
);
624 static int nrf51_write_page(struct flash_bank
*bank
, uint32_t offset
, const uint8_t *buffer
)
626 assert(offset
% 4 == 0);
627 int res
= ERROR_FAIL
;
628 struct nrf51_info
*chip
= bank
->driver_priv
;
629 struct flash_sector
*sector
= nrf51_find_sector_by_address(bank
, offset
);
632 return ERROR_FLASH_SECTOR_INVALID
;
634 if (sector
->is_protected
)
637 if (!sector
->is_erased
) {
638 res
= nrf51_erase_page(chip
, sector
);
639 if (res
!= ERROR_OK
) {
640 LOG_ERROR("Failed to erase sector @ 0x%08"PRIx32
, sector
->offset
);
645 res
= nrf51_nvmc_write_enable(chip
);
649 sector
->is_erased
= 0;
651 res
= nrf51_ll_flash_write(chip
, offset
, buffer
, chip
->code_page_size
);
655 return nrf51_nvmc_read_only(chip
);
658 nrf51_nvmc_read_only(chip
);
660 LOG_ERROR("Failed to write sector @ 0x%08"PRIx32
, sector
->offset
);
664 static int nrf51_erase(struct flash_bank
*bank
, int first
, int last
)
667 struct nrf51_info
*chip
;
669 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
673 /* For each sector to be erased */
674 for (int s
= first
; s
<= last
&& res
== ERROR_OK
; s
++)
675 res
= nrf51_erase_page(chip
, &bank
->sectors
[s
]);
680 static int nrf51_code_flash_write(struct flash_bank
*bank
,
681 struct nrf51_info
*chip
,
682 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
689 region
.start
= offset
;
690 region
.end
= offset
+ count
;
694 const uint8_t *buffer
;
695 } start_extra
, end_extra
;
697 start_extra
.length
= region
.start
% chip
->code_page_size
;
698 start_extra
.buffer
= buffer
;
699 end_extra
.length
= region
.end
% chip
->code_page_size
;
700 end_extra
.buffer
= buffer
+ count
- end_extra
.length
;
702 if (start_extra
.length
) {
703 uint8_t page
[chip
->code_page_size
];
705 res
= target_read_memory(bank
->target
,
706 region
.start
- start_extra
.length
,
707 1, start_extra
.length
, page
);
711 memcpy(page
+ start_extra
.length
,
713 chip
->code_page_size
- start_extra
.length
);
715 res
= nrf51_write_page(bank
,
716 region
.start
- start_extra
.length
,
722 if (end_extra
.length
) {
723 uint8_t page
[chip
->code_page_size
];
725 /* Retrieve the full row contents from Flash */
726 res
= target_read_memory(bank
->target
,
729 (chip
->code_page_size
- end_extra
.length
),
730 page
+ end_extra
.length
);
734 memcpy(page
, end_extra
.buffer
, end_extra
.length
);
736 res
= nrf51_write_page(bank
,
737 region
.end
- end_extra
.length
,
744 region
.start
+= start_extra
.length
;
745 region
.end
-= end_extra
.length
;
747 for (uint32_t address
= region
.start
; address
< region
.end
;
748 address
+= chip
->code_page_size
) {
749 res
= nrf51_write_page(bank
, address
, &buffer
[address
- region
.start
]);
759 static int nrf51_uicr_flash_write(struct flash_bank
*bank
,
760 struct nrf51_info
*chip
,
761 const uint8_t *buffer
, uint32_t offset
, uint32_t count
)
764 uint8_t uicr
[NRF51_UICR_SIZE
];
765 struct flash_sector
*sector
= &bank
->sectors
[0];
767 if ((offset
+ count
) > NRF51_UICR_SIZE
)
770 res
= target_read_memory(bank
->target
,
779 if (!sector
->is_erased
) {
780 res
= nrf51_erase_page(chip
, sector
);
785 res
= nrf51_nvmc_write_enable(chip
);
789 memcpy(&uicr
[offset
], buffer
, count
);
791 res
= nrf51_ll_flash_write(chip
, NRF51_UICR_BASE
, uicr
, NRF51_UICR_SIZE
);
792 if (res
!= ERROR_OK
) {
793 nrf51_nvmc_read_only(chip
);
797 return nrf51_nvmc_read_only(chip
);
801 static int nrf51_write(struct flash_bank
*bank
, const uint8_t *buffer
,
802 uint32_t offset
, uint32_t count
)
805 struct nrf51_info
*chip
;
807 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
811 return chip
->bank
[bank
->bank_number
].write(bank
, chip
, buffer
, offset
, count
);
815 FLASH_BANK_COMMAND_HANDLER(nrf51_flash_bank_command
)
817 static struct nrf51_info
*chip
;
819 switch (bank
->base
) {
820 case NRF51_FLASH_BASE
:
821 bank
->bank_number
= 0;
823 case NRF51_UICR_BASE
:
824 bank
->bank_number
= 1;
827 LOG_ERROR("Invalid bank address 0x%08" PRIx32
, bank
->base
);
832 /* Create a new chip */
833 chip
= calloc(1, sizeof(*chip
));
837 chip
->target
= bank
->target
;
840 switch (bank
->base
) {
841 case NRF51_FLASH_BASE
:
842 chip
->bank
[bank
->bank_number
].write
= nrf51_code_flash_write
;
844 case NRF51_UICR_BASE
:
845 chip
->bank
[bank
->bank_number
].write
= nrf51_uicr_flash_write
;
849 chip
->bank
[bank
->bank_number
].probed
= false;
850 bank
->driver_priv
= chip
;
855 COMMAND_HANDLER(nrf51_handle_mass_erase_command
)
858 struct flash_bank
*bank
= NULL
;
859 struct target
*target
= get_current_target(CMD_CTX
);
861 res
= get_flash_bank_by_addr(target
, NRF51_FLASH_BASE
, true, &bank
);
865 assert(bank
!= NULL
);
867 struct nrf51_info
*chip
;
869 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
875 res
= target_read_u32(target
, NRF51_FICR_PPFC
,
877 if (res
!= ERROR_OK
) {
878 LOG_ERROR("Couldn't read PPFC register");
882 if ((ppfc
& 0xFF) == 0x00) {
883 LOG_ERROR("Code region 0 size was pre-programmed at the factory, "
884 "mass erase command won't work.");
888 res
= nrf51_erase_all(chip
);
889 if (res
!= ERROR_OK
) {
890 LOG_ERROR("Failed to erase the chip");
891 nrf51_protect_check(bank
);
895 for (int i
= 0; i
< bank
->num_sectors
; i
++)
896 bank
->sectors
[i
].is_erased
= 1;
898 res
= nrf51_protect_check(bank
);
899 if (res
!= ERROR_OK
) {
900 LOG_ERROR("Failed to check chip's write protection");
904 res
= get_flash_bank_by_addr(target
, NRF51_UICR_BASE
, true, &bank
);
908 bank
->sectors
[0].is_erased
= 1;
913 static int nrf51_info(struct flash_bank
*bank
, char *buf
, int buf_size
)
917 struct nrf51_info
*chip
;
919 res
= nrf51_get_probed_chip_if_halted(bank
, &chip
);
924 const uint32_t address
;
927 { .address
= NRF51_FICR_CODEPAGESIZE
},
928 { .address
= NRF51_FICR_CODESIZE
},
929 { .address
= NRF51_FICR_CLENR0
},
930 { .address
= NRF51_FICR_PPFC
},
931 { .address
= NRF51_FICR_NUMRAMBLOCK
},
932 { .address
= NRF51_FICR_SIZERAMBLOCK0
},
933 { .address
= NRF51_FICR_SIZERAMBLOCK1
},
934 { .address
= NRF51_FICR_SIZERAMBLOCK2
},
935 { .address
= NRF51_FICR_SIZERAMBLOCK3
},
936 { .address
= NRF51_FICR_CONFIGID
},
937 { .address
= NRF51_FICR_DEVICEID0
},
938 { .address
= NRF51_FICR_DEVICEID1
},
939 { .address
= NRF51_FICR_ER0
},
940 { .address
= NRF51_FICR_ER1
},
941 { .address
= NRF51_FICR_ER2
},
942 { .address
= NRF51_FICR_ER3
},
943 { .address
= NRF51_FICR_IR0
},
944 { .address
= NRF51_FICR_IR1
},
945 { .address
= NRF51_FICR_IR2
},
946 { .address
= NRF51_FICR_IR3
},
947 { .address
= NRF51_FICR_DEVICEADDRTYPE
},
948 { .address
= NRF51_FICR_DEVICEADDR0
},
949 { .address
= NRF51_FICR_DEVICEADDR1
},
950 { .address
= NRF51_FICR_OVERRIDEN
},
951 { .address
= NRF51_FICR_NRF_1MBIT0
},
952 { .address
= NRF51_FICR_NRF_1MBIT1
},
953 { .address
= NRF51_FICR_NRF_1MBIT2
},
954 { .address
= NRF51_FICR_NRF_1MBIT3
},
955 { .address
= NRF51_FICR_NRF_1MBIT4
},
956 { .address
= NRF51_FICR_BLE_1MBIT0
},
957 { .address
= NRF51_FICR_BLE_1MBIT1
},
958 { .address
= NRF51_FICR_BLE_1MBIT2
},
959 { .address
= NRF51_FICR_BLE_1MBIT3
},
960 { .address
= NRF51_FICR_BLE_1MBIT4
},
962 { .address
= NRF51_UICR_CLENR0
, },
963 { .address
= NRF51_UICR_RBPCONF
},
964 { .address
= NRF51_UICR_XTALFREQ
},
965 { .address
= NRF51_UICR_FWID
},
968 for (size_t i
= 0; i
< ARRAY_SIZE(ficr
); i
++) {
969 res
= target_read_u32(chip
->target
, ficr
[i
].address
,
971 if (res
!= ERROR_OK
) {
972 LOG_ERROR("Couldn't read %" PRIx32
, ficr
[i
].address
);
977 for (size_t i
= 0; i
< ARRAY_SIZE(uicr
); i
++) {
978 res
= target_read_u32(chip
->target
, uicr
[i
].address
,
980 if (res
!= ERROR_OK
) {
981 LOG_ERROR("Couldn't read %" PRIx32
, uicr
[i
].address
);
986 snprintf(buf
, buf_size
,
987 "\n[factory information control block]\n\n"
988 "code page size: %"PRIu32
"B\n"
989 "code memory size: %"PRIu32
"kB\n"
990 "code region 0 size: %"PRIu32
"kB\n"
991 "pre-programmed code: %s\n"
992 "number of ram blocks: %"PRIu32
"\n"
993 "ram block 0 size: %"PRIu32
"B\n"
994 "ram block 1 size: %"PRIu32
"B\n"
995 "ram block 2 size: %"PRIu32
"B\n"
996 "ram block 3 size: %"PRIu32
"B\n"
997 "config id: %" PRIx32
"\n"
998 "device id: 0x%"PRIx32
"%08"PRIx32
"\n"
999 "encryption root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1000 "identity root: 0x%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"%08"PRIx32
"\n"
1001 "device address type: 0x%"PRIx32
"\n"
1002 "device address: 0x%"PRIx32
"%08"PRIx32
"\n"
1003 "override enable: %"PRIx32
"\n"
1004 "NRF_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1005 "BLE_1MBIT values: %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
" %"PRIx32
"\n"
1006 "\n[user information control block]\n\n"
1007 "code region 0 size: %"PRIu32
"kB\n"
1008 "read back protection configuration: %"PRIx32
"\n"
1009 "reset value for XTALFREQ: %"PRIx32
"\n"
1010 "firmware id: 0x%04"PRIx32
,
1013 (ficr
[2].value
== 0xFFFFFFFF) ? 0 : ficr
[2].value
/ 1024,
1014 ((ficr
[3].value
& 0xFF) == 0x00) ? "present" : "not present",
1017 (ficr
[6].value
== 0xFFFFFFFF) ? 0 : ficr
[6].value
,
1018 (ficr
[7].value
== 0xFFFFFFFF) ? 0 : ficr
[7].value
,
1019 (ficr
[8].value
== 0xFFFFFFFF) ? 0 : ficr
[8].value
,
1021 ficr
[10].value
, ficr
[11].value
,
1022 ficr
[12].value
, ficr
[13].value
, ficr
[14].value
, ficr
[15].value
,
1023 ficr
[16].value
, ficr
[17].value
, ficr
[18].value
, ficr
[19].value
,
1025 ficr
[21].value
, ficr
[22].value
,
1027 ficr
[24].value
, ficr
[25].value
, ficr
[26].value
, ficr
[27].value
, ficr
[28].value
,
1028 ficr
[29].value
, ficr
[30].value
, ficr
[31].value
, ficr
[32].value
, ficr
[33].value
,
1029 (uicr
[0].value
== 0xFFFFFFFF) ? 0 : uicr
[0].value
/ 1024,
1030 uicr
[1].value
& 0xFFFF,
1031 uicr
[2].value
& 0xFF,
1032 uicr
[3].value
& 0xFFFF);
1037 static const struct command_registration nrf51_exec_command_handlers
[] = {
1039 .name
= "mass_erase",
1040 .handler
= nrf51_handle_mass_erase_command
,
1041 .mode
= COMMAND_EXEC
,
1042 .help
= "Erase all flash contents of the chip.",
1044 COMMAND_REGISTRATION_DONE
1047 static const struct command_registration nrf51_command_handlers
[] = {
1050 .mode
= COMMAND_ANY
,
1051 .help
= "nrf51 flash command group",
1053 .chain
= nrf51_exec_command_handlers
,
1055 COMMAND_REGISTRATION_DONE
1058 struct flash_driver nrf51_flash
= {
1060 .commands
= nrf51_command_handlers
,
1061 .flash_bank_command
= nrf51_flash_bank_command
,
1063 .erase
= nrf51_erase
,
1064 .protect
= nrf51_protect
,
1065 .write
= nrf51_write
,
1066 .read
= default_flash_read
,
1067 .probe
= nrf51_probe
,
1068 .auto_probe
= nrf51_auto_probe
,
1069 .erase_check
= default_flash_blank_check
,
1070 .protect_check
= nrf51_protect_check
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)